128K x 24 Three Megabit 3.3V CMOS Static RAM Features ◆ Description High density 3 megabit 3.3V static RAM Low profile 119 lead, 14mm x 22mm BGA (Ball Grid Array) Fast RAM access times: 10,12,15ns Single 3.3V power supply Multiple Vcc & GND pins for maximum noise immunity Inputs/outputs directly LVTTL compatible Commercial (0O C to +70O C) Industrial (-40O C to +85O C) temperature options – Commercial: 10 / 12 / 15 ns – Industrial: 12 / 15 ns ◆ ◆ ◆ ◆ ◆ ◆ IDT7MMV4101 The IDT7MMV4101 is a three megabit static RAM constructed on an multilayer laminate substrate using three 3.3V, 128K x 8 (IDT71V124) static RAMS encapsulated in a Ball Grid Array (BGA). The IDT7MMV4101 is packaged in a plastic BGA. The BGA configuration allows 119 leads to be placed on a package 14mm by 22mm. At a maximum of 3.5mm high, this low-profile surface mount package is ideal for ultra dense systems. All inputs and outputs of the IDT7MMV4101 are LVTTL compatible and operate from a single 3.3V supply. Full asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use. Functional Block Diagram Pin Names I/O0 - 23 Data Inputs/Outputs A0 - 16 Addresses CS Chip Select WE Write Enable OE Output Enable VCC Power GND Ground NC No Connect A0-16 CS WE OE 17 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM 8 8 I/O0-7 8 , I/O16-23 I/O8-15 4083 drw 01 4083 tbl 01 Pin Configuration NC NC I/O0 I/O1 I/O2 I/O3 6 A4 A8 NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC A12 A16 5 A3 A7 NC GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A11 A15 4 A2 CS NC GND GND GND GND GND GND GND GND GND GND GND NC WE OE 3 A1 A6 NC GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A10 A14 2 A0 A5 NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC A9 7 1 NC NC A B I/O4 I/O5 NC I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 NC NC A13 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC C D E F G H J K Top View L M N P R T U 4083 drw 02 JANUARY 2003 1 ©2003 Integrated Device Technology, Inc. DSC-4083/05 , IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges Truth Table Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter Conditions Max. Unit Mode CS OE WE I/O Power VIN = 3dV 20 pF Standby H X X High-Z Standby VOUT = 3dV 10 pF Read L L H DATA OUT Active 4083 tbl 02 Write L X L DATA IN Active Outputs Disabled L H H High-Z Active (1) CIN Input Capacitance CI/O I/O Capacitance NOTE: 1. This parameter is guaranteed by design but not tested. 4083 tbl 04 Absolute Maximum Ratings(1) Recommended DC Operating Conditions Symbol Symbol VCC Parameter Min. Typ. Max. Unit VCC(1) Supply Voltage 3.15 3.3 3.6 V VCC(2) Supply Voltage 3.0 3.3 3.6 V GND Ground 0 0 0 V VIH Input High Voltage 2.0 ____ VCC + 0.3(4) V VIL Input Low Voltage -0.3(3) ____ 0.8 V NOTES: 1. For 7MMV4101S10BG only. 2. For all speed grades except 7MMV4101S10BG. 3. VIL (min) = –1.5V for pulse width less than 5ns, once per cycle. 4. VIH (max) = Vcc + 1.5V for pulse width less than 5ns, once per cycle. VTERM 4083 tbl 03 Rating Supply Voltage Relative to GND Commercial Industrial Unit -0.5 to +4.6 -0.5 to +4.6 V Terminal Voltage with -0.5 to VCC+0.5 -0.5 to VCC+0.5 Respect to GND V TA Operating Temperature 0 to +70 -40 to +85 °C TBIAS Temperature Under Bias -10 to +85 -10 to +85 °C TSTG Storage Temperature -55 to +125 -55 to +125 °C IOUT DC Output Current 50 50 mA 4083 tbl 05 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (VCC = 3.3V ±10%) Symbol Parameter Test Condition Min. Max. Unit Input Leakage Current V CC = Max., VIN = GND to V CC ____ 15 µA IILOI Output Leakage Current V CC = Max., CS > VIH, VOUT = GND to V CC, ____ 5 µA VOL Output Low Voltage IOL = 8mA, VCC = Min. ____ 0.4 V VOH Output High Voltage IOH = -4mA, VCC = Min. 2.4 ____ IILII V 4083 tbl 06 Symbol Parameter Test Condition -10(1) -12 -15 Max. Max. Max. Unit ICC Dynamic Operating Current VCC = Max., CS < VIL, f = fMAX, Outputs Open 295 275 255 mA ISB Standby Power Supply Current VCC = Max., CS > VIH, f = fMAX, Outputs Open 95 85 85 mA ISB1 Full Standby Power Supply Current CS > VCC - 0.2V, f =0 VIN > VCC - 0.2V or < 0.2V 10 10 10 mA 4083 tbl 07 NOTES: 1. Commercial temperature only, Vcc = -5% to +10%. 2 IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels Output Reference Levels 1.5V 1.5V Output Load See Figures 1 and 2 4083 tbl 08 +3.3 V +3.3 V 298 Ω 298 Ω DATA OUT DATA OUT 216 Ω 216 Ω 30 pF , 5 pF* 4083 drw 03 Figure 1. Output Load Figure 2. Output Load (for tOLZ, tOHZ, tCHZ, tCLZ, tWHZ, tOW ) * Includes scope and jig. 6.42 3 IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges AC Electrical Characteristics (2) (VCC = 3.3V ±10%) -10(3) Symbol Parameter -12 -15 Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 10 ____ 12 ____ 15 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ns tACS Chip Select Access Time ____ 10 ____ 12 ____ 15 ns tCLZ(1) Chip Select to Output in Low-Z 3 ____ 3 ____ 3 ____ ns ____ 4 ____ 6 ____ 7 ns tOE Output Enable to Output Valid tOLZ(1) Output Enable to Output in Low-Z 0 ____ 0 ____ 0 ____ ns tCHZ(1) Chip Deselect to Output in High-Z ____ 5 ____ 6 ____ 7 ns tOHZ(1) Output Disable to Output in High-Z ____ 5 ____ 6 ____ 7 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tPU(1) Chip Select to Power-Up Time 0 ____ 0 ____ 0 ____ ns tPD(1) Chip Deselect to Power-Down Time ____ 10 ____ 12 ____ 15 ns Write Cycle Time 10 ____ 12 ____ 15 ____ ns 10 ____ 12 ____ ns Write Cycle tWC tCW Chip Select to End-of-Write 8 ____ tAW Address Valid to End-of-Write 8 ____ 10 ____ 12 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns 8 ____ 10 ____ 12 ____ ns 0 ____ 0 ____ 0 ____ ns ____ 5 ____ 5 ____ 5 ns tWP tWR tWHZ(1) Write Pulse Width Write Recovery Time Write Enable to Output in High-Z tDW Data to Write Time Overlap 6 ____ 6 ____ 7 ____ ns tDH Data Hold from Write Time 0 ____ 0 ____ 0 ____ ns 3 ____ 3 ____ 3 ____ ns (1) tOW Output Active from End-of-Write 4083 tbl 09 NOTES: 1. This parameter is guaranteed by design but not tested. 2. These specifications are for the individual 71V124 Static RAMs. 3. Commercial temperature only, VCC = -5% to +10%. 4 IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE CS tOLZ (5) , tACS(3) tCLZ tOHZ (5) (5) tCHZ (5) HIGH IMPEDANCE DATAOUT . DATAOUT VALID 4083 drw 04 Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATAOUT VALID DATAOUT VALID 4083 drw 05 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.42 5 . IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,4,5) tWC ADDRESS tAW CS tWP tAS (3) tWR WE tWHZ tOW (5) (5) tCHZ (5) HIGH IMPEDANCE (4) DATAOUT (4) tDW DATAIN tDH DATAIN VALID 4083 drw 06 . Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4) tWC ADDRESS tAW CS tAS (3) tCW tWR WE tDW DATAIN tDH DATAIN VALID 4083 drw 07 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured ±200mV from steady state. 6 . IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges Package Dimensions 20.32 Ref 22.0 + 0.1 Q P O N M L K J I H G F E D C B A 7 6 5 14.00 + 0.1 4 3 7.62 Ref , 2 1 3.19 REF 1.27 Typ 0.84 REF TOP VIEW BOTTOM VIEW 2.15 Nom. 2.36 Max 4083 drw 08 NOTES: 1. All dimensions are in mm. Ordering Information IDT XXXXX X X X X Device Type Power Speed Package Process/ Temperature Range I Blank Industrial (-40°C to +85°C) Commercial (0°C to +70°C) BG 119 lead BGA (Ball Grid Array) 10 12 15 Speed in Nanoseconds Commercial Temp Only Commercial and Industrial Temp Commercial and Industrial Temp S , Standard Power 7MMV4101 3 Megabit Static RAM 4083 drw 09 6.42 7 IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges Datasheet History 09/18/00 Pg. 2 01/07/03 Add datasheet history Reduce ICC, ISB, and ISB1 to reflect K step die shrink Changed datasheet from Prelininary to final release CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax:408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 8 for Tech Support: [email protected] 800 544-7726, x4033