ETC IMST400

IMS T400
)
Low cost 32-bit transputer
FEATURES
H 32 bit architecture
H 50 ns internal cycle time
H 20 MHz only
H 20 MIPS peak instruction rate
H 10 MIPS sustained instruction rate
H Pin compatible with IMS T805, IMS T800, IMS T425
and IMS T414
H 2 Kbytes on-chip static RAM
H 80 Mbytes/sec sustained data rate to internal
memory
System
Services
H 4 Gbytes directly addressable external memory
H 26 Mbytes/sec sustained data rate to external
memory
32
32 bit
Processor
H 950 ns response to interrupts
H Whetstones/sec 704K
Timers
H Dhrystones/sec 8193
H Two INMOS serial links 5/10/20 Mbits/sec
H High performance graphics support with block move
instructions
2 Kbytes
of
On-chip
RAM
Link
Services
32
H Boot from ROM or communication links
32
Link
Interface
32
Link
Interface
H Single 5 MHz clock input
H Single +5V
10% power supply
H Packaging 84 pin PGA / 84 pin PLCC100 / pin PQFP
/ 100 pin TQFP
APPLICATIONS
The IMS T400 is a low-cost product designed for single
or multiprocessor applications in:
External
Memory
Interface
32
Event
H Telecoms
H Office systems
H Industrial control
H Robotics
H Instrumentation
H Computing
July 1995
42 1452 05
1/74
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
2 Pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
3 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
3.1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
3.2
CapPlus, CapMinus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
3.3
ClockIn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
3.4
ProcSpeedSelect0–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
3.5
Bootstrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
3.6
Peek and poke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
3.7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.8
Analyse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3.9
Error, ErrorIn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
5 External memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
5.1
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
5.2
Read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
5.3
Write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
5.4
Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
5.5
Memory refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
5.6
Direct memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
5.7
Memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
6 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
7 Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
8 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
8.1
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
8.2
Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
8.3
AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
8.4
Power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
9 Package details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
9.1
84 pin grid array package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
9.2
84 pin PLCC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
9.3
100 pin plastic quad flat pack (PQFP) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
9.4
100 pin thin plastic quad flat pack (TQFP) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
9.5
Thermal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
10 Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
11 Transputer instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
2 / 74
1 Introduction
1
Introduction
The IMS T400 transputer is a 32 bit CMOS microcomputer with graphics support. It has 2 Kbytes on-chip
RAM for high speed processing, a configurable memory interface and two standard INMOS communication links. The instruction set achieves efficient implementation of high level languages such as ANSI C
and provides direct support foR concurrency when using either a single transputer or a network. Procedure
calls, process switching and typical interrupt latency are sub-microsecond.
For convenience of description, the IMS T400 operation is split into the basic blocks shown in figure 1.1.
VDD
GND
CapPlus
CapMinus
Reset
Analyse
ErrorIn
Error
BootFromROM
ClockIn
ProcSpeedSelect0–2
System
Services
32
32 bit
Processor
Timers
DisableIntRAM
ProcClockOut
notMemS0–4
notMemWrB0–3
notMemRd
notMemRf
RefreshPending
MemWait
MemConfig
MemReq
MemGranted
2 Kbytes
of
On-chip
RAM
External
Memory
Interface
Link
Services
LinkSpecial
Link0Special
Link1Special
32
Link
Interface
LinkIn0
LinkOut0
32
Link
Interface
LinkIn1
LinkOut1
32
Event
32
32
EventReq
EventAck
EventWaiting
MemnotWrD0
MemnotRfD1
MemAD2–31
Figure 1.1 IMS T400 block diagram
The processor speed of the device is fixed at 20 MHz and achieves an instruction throughput of 20 MIPS
peak and 10 MIPS sustained.
High performance graphics support is provided by microcoded block move instructions which operate at
the speed of memory. The two-dimensional block move instructions provide for contiguous block moves
as well as block copying of either non-zero bytes of data only or zero bytes only. Block move instructions
can be used to provide graphics operations such as text manipulation, windowing, panning, scrolling and
screen updating.
Cyclic redundancy checking (CRC) instructions are available for use on arbitrary length serial data
streams, to provide error detection where data integrity is critical. Another feature of the IMS T400, useful
for pattern recognition, is the facility to count bits set in a word.
3 / 74
IMS T400
The IMS T400 can directly access a linear address space of 4 Gbytes. The 32 bit wide memory interface
uses multiplexed data and address lines and provides a data rate of up to 4 bytes every 150 nanoseconds
(26.6 Mbytes/sec) for a 20 MHz device. A configurable memory controller provides all timing, control and
DRAM refresh signals for a wide variety of mixed memory systems.
System Services include processor reset and bootstrap control, together with facilities for error analysis.
Error signals may be daisy-chained in multi-transputer systems.
The standard INMOS communication links allow networks of transputer family products to be constructed
by direct point to point connections with no external logic. The IMS T400links support the standard operating speed of 10 Mbits/sec, but also operate at 5 or 20 Mbits/sec. Each link can transfer data bi-directionally
at up to 2.35 Mbytes/sec.
The IMS T400-20 is pin compatible with the IMS T805-20 and IMS T425-20 and can be plugged directly
into a circuit designed for those devices.
The transputer is designed to efficiently implement high level languages such as ANSI C and occam.
Access to the transputer at machine level is seldom required, but if necessary refer to the Transputer Instruction Set – A Compiler Writer’s Guide.
4 / 74
2 Pin designations
2
Pin designations
Signal names are preceded by not if they are active low, otherwise they are active high.
Pinout details for various packages are given in section 9.
Pin
VDD, GND
CapPlus, CapMinus
ClockIn
ProcSpeedSelect0-2
Reset
Error
ErrorIn
Analyse
BootFromROM
DisableIntRAM
HoldToGND
DoNotWire
N/C
In/Out
in
in
in
out
in
in
in
in
Function
Power supply and return
External capacitor for internal clock power supply
Input clock
Processor speed selectors
System reset
Error indicator
Error daisychain input
Error analysis
Boot from external ROM or from link
Disable internal RAM
Must be connected to GND
Must not be wired
There is no internal connection to this pin
Table 2.1
Pin
ProcClockOut
MemnotWrD0
MemnotRfD1
MemAD2-31
notMemRd
notMemWrB0-3
notMemS0-4
notMemRf
RefreshPending
MemWait
MemReq
MemGranted
MemConfig
In/Out
out
in/out
in/out
in/out
out
out
out
out
out
in
in
out
in
IMS T400 system services
Function
Processor clock
Multiplexed data bit 0 and write cycle warning
Multiplexed data bit 1 and refresh warning
Multiplexed data and address bus
Read strobe
Four byte-addressing write strobes
Five general purpose strobes
Dynamic memory refresh indicator
Dynamic refresh is pending
Memory cycle extender
Direct memory access request
Direct memory access granted
Memory configuration data input
Table 2.2 IMS T400 external memory interface
Pin
EventReq
EventAck
EventWaiting
In/Out
in
out
out
Function
Event request
Event request acknowledge
Event input requested by software
Table 2.3
Pin
LinkIn0-1
LinkOut0-1
LinkSpecial
Link0Special
Link1Special
In/Out
in
out
in
in
in
IMS T400 event
Function
Two serial data input channels
Two serial data output channels
Select non-standard speed as 5 or 20 Mbits/sec
Select special speed for Link 0
Select special speed for Link 1
Table 2.4
IMS T400 link
5 / 74
IMS T400
3
System services
System services include all the necessary logic to initialise and sustain operation of the device. They also
include error handling and analysis facilities.
3.1
Power
Power is supplied to the device via the VDD and GND pins. Several of each are provided to minimise inductance within the package. All supply pins must be connected. The supply must be decoupled close to the
chip by at least one 100 nF low inductance (e.g. ceramic) capacitor between VDD and GND. Four layer
boards are recommended; if two layer boards are used, extra care should be taken in decoupling.
Input voltages must not exceed specification with respect to VDD and GND, even during power-up and
power-down ramping, otherwise latchup can occur. CMOS devices can be permanently damaged by excessive periods of latchup.
3.2
CapPlus, CapMinus
The internally derived power supply for internal clocks requires an external low leakage, low inductance
1mF capacitor to be connected between CapPlus and CapMinus. A ceramic capacitor is preferred, with
an impedance less than 3 Ohms between 100 KHz and 10 MHz. If a polarised capacitor is used the negative terminal should be connected to CapMinus. Total PCB track length should be less than 50 mm. The
connections must not touch power supplies or other noise sources.
VDD
CapPlus
P.C.B track
Phase–locked
loops
Decoupling
capacitor 1 mF
CapMinus
P.C.B track
GND
Figure 3.1 Recommended PLL decoupling
3.3
ClockIn
Transputer family components use a standard clock frequency, supplied by the user on the ClockIn input.
The nominal frequency of this clock for all transputer family components is 5 MHz, regardless of device
type, transputer word length or processor cycle time. High frequency internal clocks are derived from
ClockIn, simplifying system design and avoiding problems of distributing high speed clocks externally.
A number of transputer devices may be connected to a common clock, or may have individual clocks providing each one meets the specified stability criteria. In a multi-clock system the relative phasing of ClockIn clocks is not important, due to the asynchronous nature of the links. Mark/space ratio is unimportant
provided the specified limits of ClockIn pulse widths are met.
Oscillator stability is important. ClockIn must be derived from a crystal oscillator; RC oscillators are not
sufficiently stable. ClockIn must not be distributed through a long chain of buffers. Clock edges must be
monotonic and remain within the specified voltage and time limits.
6 / 74
3 System services
T400-20
Symbol
Parameter
Min
Nom
Max
Units
TDCLDCH
ClockIn pulse width low
40
ns
TDCHDCL
ClockIn pulse width high
40
ns
TDCLDCL
ClockIn period
TDCerror
ClockIn timing error
TDC1DC2
Difference in ClockIn for 2 linked devices
TDCr
TDCf
200
Notes
ns
1,3
ns
2
400
ppm
3
ClockIn rise time
10
ns
4
ClockIn fall time
8
ns
4
0.5
Notes
1 Measured between corresponding points on consecutive falling edges.
2 Variation of individual falling edges from their nominal times.
3 This value allows the use of 200ppm crystal oscillators for two devices connected together by
a link.
4 Clock transitions must be monotonic within the range VIH to VIL (table 8.3).
Table 3.1
TDCerror
Input clock
TDCerror
TDCerror
TDCerror
2.0V
1.5V
0.8V
TDCLDCH
TDCHDCL
TDCLDCL
90%
90%
10%
10%
TDCf
TDCr
Figure 3.2 ClockIn timing
3.4
ProcSpeedSelect0–2
Processor speed of the IMS T400 is variable in discrete steps. The desired speed can be selected, up to
the maximum rated for a particular component, by the three speed select lines ProcSpeedSelect0-2. The
pins are tied high or low, according to table 3.2, for the various speeds.
Currently only the 20 MHz speed select combination is available on the IMS T400; the others are not valid
speed selectors. The frequency of ClockIn for the speeds given in the table is 5 MHz.
7 / 74
IMS T400
ProcSpeedSelect2
ProcSpeedSelect1
ProcSpeedSelect0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 3.2
3.5
Processor
Clock
Speed MHz
20.0
22.5
25.0
30.0
35.0
Processor
Cycle
Time ns
50.0
44.4
40.0
33.3
28.6
17.5
57.1
Notes
Not supported
Not supported
Not supported
Not supported
Invalid
Not supported
Invalid
Processor speed selection
Bootstrap
The transputer can be bootstrapped either from a link or from external ROM. Tofacilitate debugging, BootFromROM may be dynamically changed but must obey the specified timing restrictions. It is sampled once
only by the transputer, before the first instruction is executed after Reset is taken low.
If BootFromROM is connected high (e.g. to VDD) the transputer starts to execute code from the top two
bytes in external memory, at address #7FFFFFFE. This location should contain a backward jump to a program in ROM. Following this access, BootFromROM may be taken low if required. The processor is in
the low priority state, and the W register points to MemStart (page 4).
If BootFromROM is connected low (e.g. to GND) the transputer will wait for the first bootstrap message
to arrive on any one of its links. The transputer is ready to receive the first byte on a link within two processor
cycles TPCLPCL after Reset goes low.
If the first byte received (the control byte) is greater than 1 it is taken as the quantity of bytes to be input.
The following bytes, to that quantity, are then placed in internal memory starting at location MemStart. Following reception of the last byte the transputer will start executing code at MemStart as a low priority process. BootFromROM may be taken high after reception of the last byte, if required. The memory space
immediately above the loaded code is used as work space. A byte arriving on the other link after the control
byte has been received and on the bootstrapping link after the last bootstrap byte, will be retained and no
acknowledge will be sent until a process inputs from them.
3.6
Peek and poke
Any location in internal or external memory can be interrogated and altered when the transputer is waiting
for a bootstrap from link. If the control byte is 0 then eight more bytes are expected on the same link. The
first four byte word is taken as an internal or external memory address at which to poke (write) the second
four byte word. If the control byte is 1 the next four bytes are used as the address from which to peek (read)
a word of data; the word is sent down the output channel of the same link.
Following such a peek or poke, the transputer returns to its previously held state. Any number of accesses
may be made in this way until the control byte is greater than 1, when the transputer will commence reading its bootstrap program. Either link can be used, but addresses and data must be transmitted via the
same link as the control byte.
8 / 74
3 System services
3.7
Reset
Reset can go high with VDD, but must at no time exceed the maximum specified voltage for VIH. After
VDD is valid ClockIn should be running for a minimum period TDCVRL before the end of Reset. The falling
edge of Reset initialises the transputer, triggers the memory configuration sequence and starts the bootstrap routine. Link outputs are forced low during reset; link inputs and EventReq should be held low.
Memory request (DMA) must not occur whilst Reset is high but can occur before bootstrap (page 29).
After the end of Reset there will be a delay of 144 periods of ClockIn (figure 3.3). Following this, the MemnotWrD0, MemnotRfD1 and MemAD2-31 pins will be scanned to check for the existence of a pre-programmed memory interface configuration (page 31). This lasts for a further 144 periods of ClockIn. Regardless of whether a configuration was found, 36 configuration read cycles will then be performed on
external memory using the default memory configuration (page 33), in an attempt to access the external
configuration ROM. A delay will then occur, its period depending on the actual configuration. Finally eight
complete and consecutive refresh cycles will initialise any dynamic RAM, using the new memory configuration. If the memory configuration does not enable refresh of dynamic RAM the refresh cycles will be replaced by an equivalent delay with no external memory activity.
If BootFromROM is high bootstrapping will then take place immediately, using data from external
memory; otherwise the transputer will await an input from any link. The processor will be in the low priority
state.
Reset
Action
Delay
Internal
External
configuration configuration
Delay
Refresh
Boot
Figure 3.3 IMS T400 post–reset sequence
3.8
Analyse
If Analyse is taken high when the transputer is running, the transputer will halt at the next descheduling
point (page 64). From Analyse being asserted, the processor will halt within three time slice periods plus
the time taken for any high priority process to complete. As much of the transputer status is maintained
as is necessary to permit analysis of the halted machine.
Processor flags Error, HaltOnError and EnableJ0Break are normally cleared at reset on the IMS T400;
however, if Analyse is asserted the flags are not altered. Memory refresh continues.
Input links will continue with outstanding transfers. Output links will not make another access to memory
for data but will transmit only those bytes already in the link buffer. Providing there is no delay in link acknowledgement, the links should be inactive within a few microseconds of the transputer halting.
Reset should not be asserted before the transputer has halted and link transfers have ceased. When Reset is taken low whilst Analyse is high, neither the memory configuration sequence nor the block of eight
refresh cycles will occur; the previous memory configuration will be used for any external memory accesses. If BootFromROM is high the transputer will bootstrap as soon as Analyse is taken low, otherwise
it will await a control byte on any link. If Analyse is taken low without Reset going high the transputer state
and operation are undefined. After the end of a valid Analyse sequence the registers have the values given in table 3.3.
I
W
A
B
C
MemStart if bootstrapping from a link, or the external memory bootstrap address if bootstrapping
from ROM.
MemStart if bootstrapping from ROM, or the address of the first free word after the bootstrap
program if bootstrapping from link.
The value of I when the processor halted.
The value of W when the processor halted, together with the priority of the process when the
transputer was halted (i.e. the W descriptor).
The ID of the bootstrapping link if bootstrapping from link.
Table 3.3
Register values after Analyse
9 / 74
IMS T400
Symbol
Parameter
TPVRH
TRHRL
TDCVRL
TAHRH
TRLAL
TBRVRL
TRLBRX
TALBRX
Power valid before Reset
Reset pulse width high
ClockIn running before Reset end
Analyse setup before Reset
Analyse hold after Reset end
BootFromROM setup
BootFromROM hold after Reset
BootFromROM hold after Analyse
Min
10
8
10
3
1
0
50
50
T400-20
Nom
Max
Units
ms
ClockIn
ms
ms
ClockIn
ms
ms
ms
Notes
1 Full periods of ClockIn TDCLDCL required.
2 At power-on reset.
3 Must be stable until after end of bootstrap period. See Bootstrap section 3.5.
Table 3.4
Reset , Analyse and BootFromROM timing
ClockIn
TDCVRL
VDD
TPVRH
TRHRL
Reset
TBRVRL
TRLBRX
BootFromROM
Figure 3.4 Transputer Reset timing with Analyse low
TRHRL
Reset
TRLAL
TAHRH
Analyse
TBRVRL
TALBRX
BootFromROM
Figure 3.5 Transputer Reset, Analyse and BootFromROM timing
10 / 74
Notes
1
2
1
3
3
3 System services
3.9
Error, ErrorIn
The Error pin carries the OR’ed output of the internal Error flag and the ErrorIn input. If Error is high it
indicates either that ErrorIn is high or that an error was detected in one of the processes. An internal error
can be caused, for example, by arithmetic overflow, divide by zero, array bounds violation or software setting the flag directly. Once set, the Error flag is only cleared by executing the instruction testerr. The error
is not cleared by processor reset, in order that analysis can identify any errant transputer (page 9).
A process can be programmed to stop if the Error flag is set; it cannot then transmit erroneous data to other
processes, but processes which do not require that data can still be scheduled. Eventually all processes
which rely, directly or indirectly, on data from the process in error will stop through lack of data. ErrorIn
does not directly affect the status of a processor in any way.
By setting the HaltOnError flag the transputer itself can be programmed to halt if Error becomes set. If Error
becomes set after HaltOnError has been set, all processes on that transputer will cease but will not necessarily cause other transputers in a network to halt. Setting HaltOnError after Error will not cause the transputer to halt; this allows the processor reset and analyse facilities to function with the flags in indeterminate
states.
An alternative method of error handling is to have the errant process or transputer cause all transputers
to halt. This can be done by ‘daisy-chaining’ the ErrorIn and Error pins of a number of processors and
applying the final Error output signal to the EventReq pin of a suitably programmed master transputer.
Since the process state is preserved when stopped by an error, the master transputer can then use the
analyse function to debug the fault. When using such a circuit, note that the Error flag is in an indeterminate
state on power up; the circuit and software should be designed with this in mind.
Error checks can be removed completely to optimise the performance of a proven program; any unexpected error then occurring will have an arbitrary undefined effect.
If a high priority process pre-empts a low priority one, status of the Error and HaltOnError flags is saved
for the duration of the high priority process and restored at the conclusion of it. Status of both flags is transmitted to the high priority process. Either flag can be altered in the process without upsetting the error status of any complex operation being carried out by the pre-empted low priority process.
In the event of a transputer halting because of HaltOnError, the links will finish outstanding transfers before
shutting down. If Analyse is asserted then all inputs continue but outputs will not make another access
to memory for data. Memory refresh will continue to take place.
After halting due to the Error flag changing from 0 to 1 whilst HaltOnError is set, register I points two bytes
past the instruction which set Error. After halting due to the Analyse pin being taken high, register I points
one byte past the instruction being executed. In both cases I will be copied to register A.
Master
Transputer
Analyse
Latch
Reset
EventReq
T805
slave 0
GND
ErrorIn
Error
T400
slave 1
ErrorIn
Error
T805
slave n
ErrorIn
Error
(transputer links not shown)
Figure 3.6 Error handling in a multi-transputer system
11 / 74
IMS T400
4
Memory
The IMS T400 has 2 Kbytes of fast internal static memory for high rates of data throughput. Each internal
memory access takes one processor cycle ProcClockOut (page 16). The transputer can also access
4 Gbytes of external memory space. Internal and external memory are part of the same linear address
space. Internal RAM can be disabled by holding DisableIntRAM high. All internal addresses are then
mapped to external RAM. This pin should not be altered after Reset has been taken low.
IMS T400 memory is byte addressed, with words aligned on four-byte boundaries. The least significant
byte of a word is the lowest addressed byte.
The bits in a byte are numbered 0 to 7, with bit 0 the least significant. The bytes are numbered from 0, with
byte 0 the least significant. In general, wherever a value is treated as a number of component values, the
components are numbered in order of increasing numerical significance, with the least significant component numbered 0. Where values are stored in memory, the least significant component value is stored at
the lowest (most negative) address.
Internal memory starts at the most negative address #80000000 and extends to #800007FF. User memory
begins at #80000070; this location is given the name MemStart. An instruction ldmemstartval is provided
to obtain the value of MemStart.
The context of a process in the transputer model involves a workspace descriptor (WPtr) and an instruction pointer (IPtr). WPtr is a word address pointer to a workspace in memory. IPtr points to the next instruction to be executed for the process which is the currently executing process. The context switch performed
by the breakpoint instruction swaps the WPtr and IPtr of the currently executing process with the WPtr
and IPtr held above MemStart. Two contexts are held above MemStart, one for high priority and one for
low priority; this allows processes at both levels to have breakpoints. Note that on bootstrapping from a
link, these contexts are overwritten by the loaded code. If this is not acceptable, the values should be
peeked from memory before bootstrapping from a link.
The reserved area of internal memory below MemStart is used to implement link and event channels.
Two words of memory are reserved for timer use, TPtrLoc0 for high priority processes and TPtrLoc1 for
low priority processes. They either indicate the relevant priority timer is not in use or point to the first process on the timer queue at that priority level.
Values of certain processor registers for the current low priority process are saved in the reserved IntSaveLoc locations when a high priority process pre-empts a low priority one. Other locations are reserved for
extended features such as block moves.
External memory space starts at #80000800 and extends up through #00000000 to #7FFFFFFF. Memory
configuration data and ROM bootstrapping code must be in the most positive address space, starting at
#7FFFFF6C and #7FFFFFFE respectively. Address space immediately below this is conventionally used
for ROM based code.
12 / 74
4 Memory
hi
Machine map
lo Byte address
Reset inst
Word offsets
occam map
#7FFFFFFE
#7FFFFFF8
Memory configuration
#7FFFFF6C
#0
#80000800 — Start of external memory — #0200
Reserved for
extended functions
#80000070 MemStart
#8000006C
MemStart #1C
#80000048
ERegIntSaveLoc
#80000044
STATUSIntSaveLoc
#80000040
CRegIntSaveLoc
#8000003C
BRegIntSaveLoc
#80000038
ARegIntSaveLoc
#80000034
IptrIntSaveLoc
#80000030
WdescIntSaveLoc
#8000002C
TPtrLoc1
#80000028
TPtrLoc0
#80000024
Event
#80000020
#08
Event
Reserved
#8000001C
#07
Reserved
Reserved
#80000018
#06
Reserved
Link 1 Input
#80000014
#05
Link 1 Input
Link 0 Input
#80000010
#04
Link 0 Input
Reserved
#8000000C
#03
Reserved
Reserved
#80000008
#02
Reserved
Link 1 Output
#80000004
#01
Link 1 Output
Link 0 Output
#80000000
#00
Link 0 Output
Note 1
(Base of memory)
Notes
1 These locations are used as auxiliary processor registers and should not be manipulated by the
user. Like processor registers, their contents may be useful for implementing debugging tools
(Analyse, page 9 ). For details see Transputer Instruction Set – A Compiler Writers’ Guide.
Figure 4.1 IMS T400 memory map
13 / 74
IMS T400
5
External memory interface
The External Memory Interface (EMI) allows access to a 32 bit address space, supporting dynamic and
static RAM as well as ROM and EPROM. EMI timing can be configured at Reset to cater for most memory
types and speeds, and a program is supplied with the TransputerDevelopment System to aid in this configuration.
There are 17 internal configurations which can be selected by a single pin connection (page 31). If none
are suitable the user can configure the interface to specific requirements, as shown in page 33.
The external memory cycle is divided into six Tstates with the following functions:
T1
Address setup time before address valid strobe.
T2
Address hold time after address valid strobe.
T3
Read cycle tristate or write cycle data setup.
T4
Extendable data setup time.
T5
Read or write data.
T6
Data hold.
Under normal conditions each Tstate may be from one to four periods Tm long, the duration being set
during memory configuration. The default condition on Reset is that all Tstates are the maximum four periods Tm long to allow external initialisation cycles to read slow ROM.
Period T4 can be extended indefinitely by adding externally generated wait states.
An external memory cycle is always an even number of periods Tm in length and the start of T1 always
coincides with a rising edge of ProcClockOut. If the total configured quantity of periods Tm is an odd number, one extra period Tm will be added at the end of T6 to force the start of the next T1 to coincide with
a rising edge of ProcClockOut. This period is designated E in configuration diagrams (figure 5.19).
During an internal memory access cycle the external memory interface bus MemAD2-31 reflects the word
address used to access internal RAM, MemnotWrD0 reflects the read/write operation and MemnotRfD1
is high; all control strobes are inactive. This is true unless and until a memory refresh cycle or DMA
(memory request) activity takes place, when the bus will carry the appropriate external address or data.
The bus activity is not adequate to trace the internal operation of the transputer in full, but may be used
for hardware debugging in conjunction with peek and poke (page 8).
ProcClockOut
MemnotWrD0
Write
Read
Read
MemnotRfD1
MemAD2–31
Address
Address
Address
Figure 5.1 IMS T400 bus activity for internal memory cycle
14 / 74
5 External memory interface
5.1
Pin functions
5.1.1
MemAD2–31
External memory addresses and data are multiplexed on one bus. Only the top 30 bits of address are output on the external memory interface, using pins MemAD2-31. They are normally output only during
Tstates T1 and T2, and should be latched during this time. The data bus is 32 bits wide. It uses MemAD2-31 for the top 30 bits and MemnotRfD1 and MemnotWrD0 for the lower two bits.
5.1.2
notMemRd
For a read cycle the read strobe notMemRd is low during T4 and T5. Data is read by the transputer on
the rising edge of this strobe, and may be removed immediately afterward. If the strobe duration is insufficient it may be extended by adding extra periods Tm to either or both of the Tstates T4 and T5. Further
extension may be obtained by inserting wait states at the end of T4.
5.1.3
MemnotWrD0
During T1 and T2 this pin will be low if the cycle is a write cycle, otherwise it will be high. During Tstates
T3 to T6 it becomes bit 0 of the data bus. In both cases it follows the general timing of MemAD2-31.
5.1.4
notMemWrB0–3
Because the transputer uses word addressing, four write strobes are provided; one to write each byte of
the word. notMemWrB0 addresses the least significant byte.
5.1.5
notMemS0–4
To facilitate control of different types of memory and devices, the EMI is provided with five strobe outputs,
four of which can be configured by the user. The strobes are conventionally assigned the functions shown
in the read and write cycle diagrams, although there is no compulsion to retain these designations.
5.1.6
MemWait
Wait states can be selected by taking MemWait high. Externally generated wait states can be added to
extend the duration of T4 indefinitely.
5.1.7
MemnotRfD1
During T1 and T2, this pin is low if the address on MemAD2-31 is a refresh address, otherwise it is high.
During Tstates T3 to T6 it becomes bit 1 of the data bus. In both cases it follows the general timing of MemAD2-31.
5.1.8
notMemRf
The IMS T400 can be operated with memory refresh enabled or disabled. The selection is made during
memory configuration, when the refresh interval is also determined.
5.1.9
RefreshPending
When high, this pin signals that a refresh cycle is pending.
15 / 74
IMS T400
CapPlus
CapMinus
ClockIn
(5MHz)
VDD
GND
Link0In
MemAD24–31
Row/
column
address
multiplexor
MemAD16–23
Column
address
latch
MemAD8–15
MemnotWrD0
MemnotRfD1
MemAD2–31
MemAD5
MemConfig
256K 4
Dynamic
256K 4
RAM
Dynamic
256K 4 RAM
Dynamic
notOE
256K 4 RAM
notCAS Dynamic
RAM
notRAS
MemAD2–10
IMS
56R
T400
Link1In
As Link0
Link1Out
notMemWrB3
notMemWrB2
notMemWrB1
notMemWrB0
notMemRd
notMemS3
notMemS2
notMemS1
notMemS0
MemAD11–19
Link0Out
MemnotWrD0
MemnotRfD1
MemAD2–7
100K
GND
Figure 5.2 IMS T400 dynamic RAM application
5.1.10
MemReq, MemGranted
Direct memory access (DMA) can be requested at any time by driving the asynchronous MemReq input
high. MemGranted follows the timing of the bus being tristated and can be used to signal to the device
requesting the DMA that it has control of the bus. Note that MemGranted changes on the falling edge of
ProcClockOut and can therefore be sampled to establish control of the bus on the rising edge of
ProcClockOut.
5.1.11
MemConfig
MemConfig is an input pin used to read configuration data when setting external memory interface (EMI)
characteristics.
5.1.12
ProcClockOut
This clock is derived from the internal processor clock, which is in turn derived from ClockIn. Its period
is equal to one internal microcode cycle time, and can be derived from the formula
TPCLPCL = TDCLDCL / PLLx
where TPCLPCL is the ProcClockOut Period, TDCLDCL is the ClockIn Period and PLLx is the phase
lock loop factor for the relevant speed part, obtained from the ordering details (Ordering section).
16 / 74
5 External memory interface
The time value Tm is used to define the duration of Tstates and, hence, the length of external memory
cycles; its value is exactly half the period of one ProcClockOut cycle (0.5*TPCLPCL), regardless of mark/
space ratio of ProcClockOut.
Edges of the various external memory strobes coincide with rising or falling edges of ProcClockOut. It
should be noted, however, that there is a skew associated with each coincidence. The value of skew depends on whether coincidence occurs when the ProcClockOut edge and strobe edge are both rising,
when both are falling or if either is rising when the other is falling. Timing values given in the strobe tables
show the best and worst cases. If a more accurate timing relationship is required, the exact Tstate timing
and strobe edge to ProcClockOut relationships should be calculated and the correct skew factors applied
from the edge skew timing table 5.4.
T400-20
Symbol
Parameter
TPCLPCL
ProcClockOut period
TPCHPCL
ProcClockOut pulse width high
TPCLPCH
ProcClockOut pulse width low
Tm
ProcClockOut half cycle
TPCstab
ProcClockOut stability
Min
Max
Units
48
52
ns
13.5
28.5
ns
a
24
ns
26
ns
8
%
Notes
2,3
1
Notes
1 Stability is the variation of cycle periods between two consecutive cycles, measured at corresponding points on the cycles.
2 a is TPCLPCL – TPCHPCL.
3 This is a nominal value.
Table 5.1
ProcClockOut
1.5V
TPCLPCH
TPCHPCL
TPCLPCL
Figure 5.3 IMS T400 ProcClockOut timing
17 / 74
IMS T400
5.2
Read cycle
Byte addressing is carried out internally by the transputer for read cycles. For a read cycle the read strobe
notMemRd is low during T4 and T5. Read cycle data may be set up on the data bus at any time after the
start of T3, but must be valid when the transputer reads it at the end of T5. Data may be removed any time
during T6, but must be off the bus no later than the end of that period.
notMemS0 is a fixed format strobe. Its leading edge is always coincident with the start of T2 and its trailing
edge always coincident with the end of T5.
The leading edge of notMemS1 is always coincident with the start of T2, but its duration may be configured
to be from zero to 31 periods Tm. Regardless of the configured duration, the strobe will terminate no later
than the end of T6. The strobe is sometimes programmed to extend beyond the normal end of Tmx. When
wait states are inserted into an EMI cycle the end of Tmx is delayed, but the potential active duration of
the strobe is not altered. Thus the strobe can be configured to terminate relatively early under certain conditions (page 24). If notMemS1 is configured to be zero it will never go low.
notMemS2, notMemS3 and notMemS4 are identical in operation. They all terminate at the end of T5,
but the start of each can be delayed from one to 31 periods Tm beyond the start of T2. If the duration of
one of these strobes would take it past the end of T5 it will stay high. This can be used to cause a strobe
to become active only when wait states are inserted. If one of these strobes is configured to zero it will
remain low during T1–T5 and only go high during the first Tm of T6. Figure 5.6 shows the effect of Wait
on strobes in more detail; each division on the scale is one period Tm.
In the read cycle timing diagrams ProcClockOut is included as a guide only; it is shown with each Tstate
configured to one period Tm.
T400-20
Symbol
Parameter
Min
Max
Units
TaZdV
Address tristate to data valid
0
ns
TdVRdH
Data setup before read
25
ns
TRdHdX
Data hold after read
0
ns
TS0LRdL
notMemS0 before start of read
a–4
a+4
ns
TS0HRdH
End of read from end of notMemS0
–4
4
ns
TRdLRdH
Read period
b–3
b+5
ns
Notes
1
2
Notes
1 a is total of T2+T3 where T2, T3 can be from one to four periods Tm each in length.
2 b is total of T4+Twait+T5 where T4, T5 can be from one to four periods Tm each in length and
Twait may be any number of periods Tm in length.
Table 5.2
18 / 74
Read
5 External memory interface
Tstate
T1
T2
T3
T4
T5
T6
T1
ProcClockOut
Tmx
MemnotWrD0
Data
MemnotRfD1
Data
MemAD2–31
Address
TaVS0L TS0LaX
Data
TRdHdX
TaZdV
TdVRdH
TS0LRdL
TRdLRdH
notMemRd
TS0HRdH
notMemS0
(CE)
TS0LS0H
TS0LS1L 1
TS0LS1H 5
TS0HS1H 9
notMemS1
(ALE)
Figure 5.4 IMS T400 external read cycle: static memory
19 / 74
IMS T400
Symbol
TaVS0L
TS0LaX
TS0LS0H
TS0LS1L
TS0LS1H
TS0HS1H
TS0LS2L
TS0LS2H
TS0HS2H
TS0LS3L
TS0LS3H
TS0HS3H
TS0LS4L
TS0LS4H
TS0HS4H
Tmx
n
Parameter
Address setup before notMemS0
Address hold after notMemS0
notMemS0 pulse width low
1 notMemS1 from notMemS0
5 notMemS1 end from notMemS0
9 notMemS1 end from notMemS0 end
2 notMemS2 delayed after notMemS0
6 notMemS2 end from notMemS0
10 notMemS2 end from notMemS0 end
3 notMemS3 delayed after notMemS0
7 notMemS3 end from notMemS0
11 notMemS3 end from notMemS0 end
4 notMemS4 delayed after notMemS0
8 notMemS4 end from notMemS0
12 notMemS4 end from notMemS0 end
Complete external memory cycle
T400-20
Min
Max
a–8
b–8
b+8
c–5
c+6
–4
4
d–3
d+7
e–8
e+4
f–6
f+5
c–5
c+7
–4
7
f–6
f+5
c–5
c+7
–4
7
f–6
f+5
c–5
c+7
–4
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
2
3
4,6
5,6
7
3
7
3
7
3
8
Notes
1 a is T1 where T1 can be from one to four periods Tm in length.
2 b is T2 where T2 can be from one to four periods Tm in length.
3 c is total of T2+T3+T4+Twait+T5 where T2, T3, T4, T5 can be from one to four periods Tm each
in length and Twait may be any number of periods Tm in length.
4 d can be from zero to 31 periods Tm in length.
5 e can be from –27 to +4 periods Tm in length.
6 If the configuration would cause the strobe to remain active past the end of T6 it will go high at
the end of T6. If the strobe is configured to zero periods Tm it will remain high throughout the
complete cycle Tmx.
7 f can be from zero to 31 periods Tm in length. If this length would cause the strobe to remain
active past the end of T5 it will go high at the end of T5. If the strobe value is zero periods Tm
it will remain low throughout T1 to T5 and only go high during the first Tm of T6.
8 Tmx is one
complete external memory cycle comprising the total of
T1+T2+T3+T4+Twait+T5+T6 where T1, T2, T3, T4, T5 can be from one to four periods Tm each
in length, T6 can be from one to five periods Tm in length and Twait may be zero or any number
of periods Tm in length.
Table 5.3
20 / 74
IMS T400 strobe timing
5 External memory interface
Tstate
T1
T2
T3
T4
T5
T6
T1
ProcClockOut
Tmx
MemnotWrD0
Data
MemnotRfD1
Data
MemAD2–31
Data
Address
TaVS0L TS0LaX
TaZdV
TRdHdX
TdVRdH
TS0HRdH
TS0LRdL
TRdLRdH
notMemRd
TS0LS0H
notMemS0
(RAS)
TS0LS1L 1
TS0HS1H 9
TS0LS1H 5
notMemS1
(ALE)
notMemS2
(AMUX)
notMemS3
(CAS)
TS0LS2H 6
TS0LS2L 2
TS0HS2H 10
TS0LS3H 7
TS0LS3L 3
TS0HS3H 11
TS0LS4H 8
TS0LS4L 4
TS0HS4H 12
notMemS4
(Wait state)
Figure 5.5 IMS T400 external read cycle: dynamic memory
21 / 74
IMS T400
Tstate T1 T2 T3 T4 T5 T6 T1
Tstate T1 T2 T3 T4 W W T5 T6 T1
notMemS1
notMemS1
notMemS2
notMemS2
No wait states
Wait states inserted
Figure 5.6 IMS T400 effect of wait states on strobes
T400-20
Symbol
Parameter
TPCHS0H
Min
Max
Units
notMemS0 rising from ProcClockOut rising
–6
4
ns
TPCLS0H
notMemS0 rising from ProcClockOut falling
–5
10
ns
TPCHS0L
notMemS0 falling from ProcClockOut rising
–8
3
ns
TPCLS0L
notMemS0 falling from ProcClockOut falling
–5
7
ns
Table 5.4
Strobe S0 to ProcClockOut skew
ProcClockOut
TPCHS0H
TPCHS0L
TPCLS0H
notMemS0
Figure 5.7 IMS T400 skew of notMemS0 to ProcClockOut
22 / 74
TPCLS0L
5 External memory interface
5.3
Write cycle
For write cycles the relevant bytes in memory are addressed by the write strobes notMemWrB0-3. If a
particular byte is not to be written, then the corresponding data outputs are tristated.
For a write cycle pin MemnotWrD0 will be low during T1 and T2. Write data is placed on the bus at the
start of T3 and removed at the end of T6. If T6 is extended to force the next cycle Tmx (page 15) to start
on a rising edge of ProcClockOut, data will be valid during this time also.
The transputer has both early and late write cycle modes. For a late write cycle the relevant write strobes
notMemWrB0-3 are low during T4 and T5; for an early write they are also low during T3. Data should be
latched into memory on the rising edge of the strobes in both cases, although it is valid until the end of T6.
If the strobe duration is insufficient, it may be extended at configuration time by adding extra periods Tm
to either or both of Tstates T4 and T5 for both early and late modes. For an early cycle they may also be
added to T3. Further extension may be obtained by inserting wait states at the end of T4. If the data hold
time is insufficient, extra periods Tm may be added to T6 to extend it.
In the write cycle timing diagram ProcClockOut is included as a guide only; it is shown with each Tstate
configured to one period Tm. The strobe is inactive during internal memory cycles.
T400-20
Symbol
Parameter
Min
Max
Units
Notes
TdVWrH
TWrHdX
TS0LWrL
Data setup before write
Data hold after write
notMemS0 before start of early write
notMemS0 before start of late write
End of write from end of notMemS0
Early write pulse width
Late write pulse width
d–7
a–10
b–5
c–5
–5
d–4
e–4
d+10
a+5
b+5
c+5
4
d+7
e+7
ns
ns
ns
ns
ns
ns
ns
1,5
1,2
1,3
1,4
1
1,5
1,6
TS0HWrH
TWrLWrH
Notes
1 Timing is for all write strobes notMemWrB0-3.
2 a is T6 where T6 can be from one to five periods Tm in length.
3 b is T2 where T2 can be from one to four periods Tm in length.
4 c is total of T2+T3 where T2, T3 can be from one to four periods Tm each in length.
5 d is total of T3+T4+Twait+T5 where T3, T4, T5 can be from one to four periods Tm each in length
and Twait may be zero or any number of periods Tm in length.
6 e is total of T4+Twait+T5 where T4, T5 can be from one to four periods Tm each in length and
Twait may be zero or any number of periods Tm in length.
Table 5.5
Write
23 / 74
IMS T400
Tstate
T1
T2
T3
T4
T5
T6
T1
ProcClockOut
Tmx
MemnotWrD0
Data
MemnotRfD1
Data
MemAD2–31
Address
Data
TdVWrH
TWrHDX
TaVS0L TS0LaX
TWrLWrH
TS0LWrL
notMemWrB0–3
(Early write)
TS0LWrL
TWrLWrH
notMemWrB0–3
(Late write)
TS0LS0H
notMemS0
(CE)
notMemS1
(ALE)
TS0HWrH
TS0LS1L 1
TS0LS1H 5
TS0HS1H 9
Figure 5.8 IMS T400 external write cycle
5.4
Wait
Taking MemWait high with the timing shown (figure 5.9) will extend the duration of T4. MemWait is
sampled close to the falling edge of ProcClockOut during a T3 or T4 period, prior to, but not at the end
of T4. By convention, notMemS4 is used to synchronize wait state insertion. If this or another strobe is
used, its delay should be such as to take the strobe low an even number of periods Tm after the start of
T1, to coincide with a rising edge of ProcClockOut.
MemWait may be kept high indefinitely, although if dynamic memory refresh is used it should not be kept
high long enough to interfere with refresh timing. MemWait operates normally during all cycles, including
refresh and configuration cycles. It does not affect internal memory access in any way.
If the start of T5 would coincide with a falling edge of ProcClockOut an extra wait period Tm (EW) is generated by the EMI to force coincidence with a rising edge. Rising edge coincidence is only forced if wait states
are added, otherwise coincidence with a falling edge is permitted.
24 / 74
5 External memory interface
IMS T400-20
Symbol
Parameter
Min
TPCLWtH
Wait setup
TPCLWtL
TWtLWtH
Max
Units
Notes
10
ns
1,2
Wait hold
8
ns
1,2
Delay before re-assertion of Wait
50
ns
Notes
1 ProcClockOut load should not exceed 50pf.
2 If wait period exceeds refresh interval, refresh cycles will be lost.
Table 5.6
Tstate
T2
T3
IMS T400 memory wait
T4
W
T5
T6
T1
ProcClockOut
TPCLWtL
TPCLWtH
MemWait
TWtLWtH
MemAD0–31
Address
Data
Address
notMemRd
Tstate
T3
T4
T4
W
W
EW
T5
T6
Tstate
T3
T4
T4
W
EW
W
EW
T5
Tstate
T2
T3
T4
W
EW
T5
T6
T1
ProcClockOut
MemWait
ProcClockOut
MemWait
ProcClockOut
MemWait
Figure 5.9 IMS T400 memory wait timing
25 / 74
IMS T400
5.5
Memory refresh
The RefreshPending pin is asserted high when the external memory interface is about to perform a refresh cycle. It remains high until the refresh cycle is started by the transputer. The mimimum time for the
RefreshPending pin to be high is for one cycle of ProcClockOut (two periods Tm), when the EMI was
not about to perform a memory read or write. If the EMI was held in the tristate condition with MemGranted
asserted, then RefreshPending will be asserted when the refresh controller in the EMI is ready to perform
a refresh. MemReq may be re-asserted any time after the commencement of the refresh cycle. RefreshPending changes state near the rising edge of ProcClockOut and can therefore be sampled by the falling
edge of ProcClockOut.
If no DMA is active then refresh will be performed following the end of the current internal or external
memory cycle. If DMA is active the transputer will wait for DMA to terminate before commencing the refresh cycle. Unlike MemnotRfD1, RefreshPending is never tristated and can thus be interrogated by the
DMA device; the DMA cycle can then be suspended, at the discretion of the DMA device, to allow refresh
to take place.
The simple circuit of Figure 5.10 will suspend DMA requests from the external logic when RefreshPending is asserted, so that a memory refresh cycle can be performed. DMA is restored on completion of the
refresh cycle. The transputer will not perform an external memory cycle other than a refresh cycle, using
this method, until the requesting device removes its DMA request.
DMA Request
MemReq
Logic
IMS T400
RefreshPending
Figure 5.10
IMS T400 refresh with DMA
When refresh is disabled no refresh cycles occur. During the post-Reset period eight dummy refresh
cycles will occur with the appropriate timing but with no bus or strobe activity.
A refresh cycle uses the same basic external memory timing as a normal external memory cycle, except
that it starts two periods Tm before the start of T1. If a refresh cycle is due during an external memory
access, it will be delayed until the end of that external cycle. Two extra periods Tm (periods R in the diagram) will then be inserted between the end of T6 of the external memory cycle and the start of T1 of the
refresh cycle itself. The refresh address and various external strobes become active approximately one
period Tm before T1. Bus signals are active until the end of T2, whilst notMemRf remains active until the
end of T6.
For a refresh cycle, MemnotRfD1 goes low when notMemRf goes low and MemnotWrD0 goes high with
the same timing as MemnotRfD1. All the address lines share the same timing, but only MemAD2-11 give
the refresh address. MemAD12-30 stay high during the address period, whilst MemAD31 remains low.
Refresh cycles generate strobes notMemS0-4 with timing as for a normal external cycle, but notMemRd
and notMemWrB0-3 remain high. MemWait operates normally during refresh cycles.
Refresh cycles do not interrupt internal memory accesses, although the internal addresses cannot be reflected on the external bus during refresh.
26 / 74
5 External memory interface
T400-20
Symbol
Parameter
Min
Max
Units
Notes
TRfLRfH
TRaVS0L
TRfLS0L
Refresh pulse width low
Refresh address setup before notMemS0
Refresh indicator setup before notMemS0
a–2
b–12
b–4
a+9
ns
ns
ns
1
b+6
2
Notes
1 a is total Tmx+Tm.
2 b is total T1+Tm where T1 can be from one to four periods Tm in length.
Table 5.7
Tstate
T4
T5
T6
normal cycle
MemAD2–31
Tstate
MemAD2–11
notMemS0
Memory refresh
T1
T2
T3
T4
Address
T6
R
R
T1
T2
T5
T6
T1
T6
T1
Data
T3
T4
T5
Refresh address
TRaVSOL
TRfLSOL
TRfLRfH
notMemRf
MemnotWrD0
MemnotRfD1
MemAD12–30
MemAD31
Figure 5.11 IMS T400 refresh cycle timing
27 / 74
IMS T400
R
R
T1
ProcClockOut
notMemS0
MemReq
MemGranted
RefreshPending
notMemRf
MemAD2–11
Refresh Address
Figure 5.12 IMS T400 Refresh Pending timing
28 / 74
5 External memory interface
5.6
Direct memory access
Direct memory access (DMA) can be requested at any time by taking the asynchronous MemReq input
high. The transputer samples MemReq just before falling edges of ProcClockOut. To guarantee taking
over the bus immediately following either a refresh or external memory cycle, MemReq must be sampled
at least four periods Tm before the end of T6. In the absence of an external memory cycle, the address
bus is tristated two periods Tm after the ProcClockOut rising edge which follows the sample.
Removal of MemReq is sampled just before falling edges of ProcClockOut and MemGranted is removed
synchronously with the second falling edge of ProcClockOut which follows the sample. If accurate timing
of DMA is required, the setup time relative to ProcClockOut must be met. Further external bus activity,
either refresh, external cycles or reflection of internal cycles, will commence at the next but one rising edge
of ProcClockOut.
The strobes (notMemS0–4 and notMemWrB0–3) are left in their inactive states during DMA. DMA cannot
interrupt a refresh or external memory cycle, and outstanding refresh cycles will occur before the bus is
released to DMA. DMA does not interfere with internal memory cycles in any way, although a program
running in internal memory would have to wait for the end of DMA before accessing external memory. DMA
cannot access internal memory. If DMA extends longer than one refresh interval (Memory Refresh Configuration Coding, table 5.11), the DMA user becomes responsible for refresh (see section 5.5). DMA may
also inhibit an internally running program from accessing external memory.
DMA allows a bootstrap program to be loaded into external RAM ready for execution after reset. If MemReq is held high throughout reset, MemGranted will be asserted before the bootstrap sequence begins.
MemReq must be high at least one period TDCLDCL of ClockIn before Reset. The circuit should be designed to ensure correct operation if Reset could interrupt a normal DMA cycle.
Symbol
Parameter
TMRHPCL
TPCLMGH
TMRLPCL
TPCLMGL
TADZMGH
TMGLADV
Notes
MemReq setup before ProcClockOut falling
MemReq response time
Memreq removal before ProcClockOut falling
MemReq end response time
Bus tristate before MemGranted
Bus active after end of MemGranted
T400-20
Min Max
3
14
96
110
4
16
50
66
0
27
0
32
Units
ns
ns
Note
1
2
ns
ns
ns
1 Setup time need only be met to guarantee sampling on this edge.
2 If an external cycle is active, maximum time could be
(1 EMI cycle Tmx)+(1 refresh cycle TRfLRfH)+(6 periods Tm).
Table 5.8 Memory request
T6
ProcClockOut
TMRHPCL
TMRLPCL
MemReq
TPCLMGH
TPCLMGL
MemGranted
TADZMGH
MemnotWrD0
MemnotRfD1
MemAD2–31
Figure 5.13
TMGLADV
IMS T400 memory request timing
29 / 74
IMS T400
MemReq
MemGranted
Reset
Configuration
sequence
D
I
E
R
B
D
I E D R
B
Pre– and post–configuration delays (figure 3.3)
Internal configuration sequence
External configuration sequence
Initial refresh sequence
Bootstrap sequence
Figure 5.14 IMS T400 DMA sequence at reset
MemReq
External memory
interface cycles
Read or write
Refresh
Read or write
MemGranted
MemnotRfD1
MemnotWrD0
MemAD2–31
Figure 5.15 IMS T400 operation of MemReq, MemGranted with external, refresh memory cycles
MemReq
Internal memory cycles
External memory
interface activity
T1 T2 T3 T4 T5 T6
EMI cycle
T1 T2 T3 T4 T5 T6
EMI cycle
MemGranted
MemnotWrD0
MemnotRfD1
MemAD2–31
Figure 5.16 IMS T400 operation of MemReq, MemGranted with external, internal memory cycles
30 / 74
5 External memory interface
5.7
Memory configuration
MemConfig is an input pin used to read configuration data when setting external memory interface (EMI)
characteristics. It is read by the processor on two occasions after Reset goes low; first to check if one of
the preset internal configurations is required, then to determine a possible external configuration.
5.7.1
Internal configuration
The internal configuration scan comprises 64 periods TDCLDCL of ClockIn during the internal scan period of 144 ClockIn periods. MemnotWrD0, MemnotRfD1 and MemAD2-32 are all high at the beginning
of the scan. Starting with MemnotWrD0, each of these lines goes low successively at intervals of two
ClockIn periods and stays low until the end of the scan. If one of these lines is connected to MemConfig
the preset internal configuration mode associated with that line will be used as the EMI configuration. The
default configuration is that defined in the table for MemAD31; connecting MemConfig to VDD will also
produce this default configuration. Note that only 17 of the possible configurations are valid, all others remain at the default configuration.
Duration of each Tstate
periods Tm
Pin
Strobe
coefficient
Write
cycle
Refresh
interval
Cycle
time
T1
T2
T3
T4
T5
T6
s1
s2
s3
s4
type
ClockIn
cycles
Proc
cycles
MemnotWrD0
1
1
1
1
1
1
30
1
3
5
late
72
3
MemnotRfD1
1
2
1
1
1
2
30
1
2
7
late
72
4
MemAD2
1
2
1
1
2
3
30
1
2
7
late
72
5
MemAD3
2
3
1
1
2
3
30
1
3
8
late
72
6
MemAD4
1
1
1
1
1
1
3
1
2
3
early
72
3
MemAD5
1
1
2
1
2
1
5
1
2
3
early
72
4
MemAD6
2
1
2
1
3
1
6
1
2
3
early
72
5
MemAD7
2
2
2
1
3
2
7
1
3
4
early
72
6
MemAD8
1
1
1
1
1
1
30
1
2
3
early
{
3
MemAD9
1
1
2
1
2
1
30
2
5
9
early
{
4
MemAD10
2
2
2
2
4
2
30
2
3
8
late
72
7
MemAD11
3
3
3
3
3
3
30
2
4
13
late
72
9
MemAD12
1
1
2
1
2
1
4
1
2
3
early
72
4
MemAD13
2
1
2
1
2
2
5
1
2
3
early
72
5
MemAD14
2
2
2
1
3
2
6
1
3
4
early
72
6
MemAD15
2
1
2
3
3
3
8
1
2
3
early
72
7
MemAD31
4
4
4
4
4
4
31
30
30
18
late
72
12
{ Provided for static RAM only.
Table 5.9
IMS T400 internal configuration coding
31 / 74
IMS T400
Tstate 1 2 3 4 5 6 1 2 3 4 5 6 1 2
notMemS0
1 2 2 3 4 5 6 6 1 2 2 3 4 5
notMemS0
30
notMemS1
notMemS2
1
notMemS2
notMemS3
3
notMemS3
notMemS4
30
notMemS1
1
2
notMemS4
5
notMemRd
notMemRd
notMemWr late
notMemWr
MemConfig=MemnotWrD0
late
MemConfig=MemnotRfD1
Tstate 1 1 2 2 2 3 4 5 5 6 6 6 1 2
notMemS0
7
1 1 2 2 3 3 4 5 5 5 6 6 1 1
notMemS0
30
notMemS1
1
notMemS2
notMemS2
3
notMemS3
notMemS4
8
7
notMemS1
1
notMemS3
3
notMemS4
4
notMemRd
notMemRd
notMemWr late
notMemWr early
MemConfig=MemAD3
MemConfig=MemAD7
Figure 5.17 IMS T400 internal configuration
32 / 74
5 External memory interface
Delay
Internal configuration
64
periods
of
ClockIn
Periods of ClockIn
0 0 0 0 11
2 4 6 8 02
MemnotWrD0
External configuration
16
periods
Read at Read at
of
7FFFFF6C 7FFFFF70
ClockIn
566 6
802 4
MemnotRfD1
MemAD2
MemAD3
MemAD31
MemConfig 1
MemConfig 2
1 Internal configuration: MemConfig connected to MemAD2
2 External configuration: MemConfig connected to inverse of MemAD3
Figure 5.18
5.7.2
IMS T400 internal configuration scan
External configuration
If MemConfig is held low until MemnotWrD0 goes low the internal configuration is ignored and an external
configuration will be loaded instead. An external configuration scan always follows an internal one, but if
an internal configuration occurs any external configuration is ignored.
The external configuration scan comprises 36 successive external read cycles, using the default EMI configuration preset by MemAD31. However, instead of data being read on the data bus as for a normal read
cycle, only a single bit of data is read on MemConfig at each cycle. Addresses put out on the bus for each
read cycle are shown in table 5.10, and are designed to address ROM at the top of the memory map. The
table shows the data to be held in ROM; data required at the MemConfig pin is the inverse of this.
MemConfig is typically connected via an inverter to MemnotWrD0. Data bit zero of the least significant
byte of each ROM word then provides the configuration data stream. By switching MemConfig between
various data bus lines up to 32 configurations can be stored in ROM, one per bit of the data bus. MemConfig can be permanently connected to a data line or to GND. Connecting MemConfig to GND gives all
Tstates configured to four periods; notMemS1 pulse of maximum duration; notMemS2-4 delayed by
maximum; refresh interval 72 periods of ClockIn; refresh enabled; late write.
The external memory configuration table 5.10 shows the contribution of each memory address to the
13 configuration fields. The lowest 12 words (#7FFFFF6C to #7FFFFF98, fields 1 to 6) define the number
of extra periods Tm to be added to each Tstate. If field 2 is 3 then three extra periods will be added to T2
to extend it to the maximum of four periods.
The next five addresses (field 7) define the duration of notMemS1 and the following fifteen (fields 8 to 10)
define the delays before strobes notMemS2-4 become active. The five bits allocated to each strobe allow
durations of from 0 to 31 periods Tm, as described in strobes page 15.
33 / 74
IMS T400
Addresses #7FFFFFEC to #7FFFFFF4 (fields 11 and 12) define the refresh interval and whether refresh
is to be used, whilst the final address (field 13) supplies a high bit to MemConfig if a late write cycle is
required.
The columns to the right of the coding table show the values of each configuration bit for the four sample
external configuration diagrams. Note the inclusion of period E at the end of T6 in some diagrams. This
is inserted to bring the start of the next Tstate T1 to coincide with a rising edge of ProcClockOut (page 16).
Wait states W have been added to show the effect of them on strobe timing; they are not part of a configuration. In each case which includes wait states, two wait periods are defined. This shows that if a wait state
would cause the start of T5 to coincide with a falling edge of ProcClockOut, another period Tm is generated by the EMI to force it to coincide with a rising edge of ProcClockOut. This coincidence is only necessary if wait states are added, otherwise coincidence with a falling edge is permitted. Any configuration
memory access is only permitted to be extended using wait, up to a total of 14 ClockIn periods.
34 / 74
5 External memory interface
Tstate 1 2 2 3 3 4 5 6 6 E 1 2 2 3
notMemS0
notMemS0
8
notMemS1
2
notMemS2
1
7
notMemS3
4
notMemS4
0
notMemS1
3
notMemS2
notMemS3
Tstate 1 2 3 3 4 W W W 5 6 1 2 3 3
notMemS4
notMemRd
notMemRd
notMemWr early
notMemWr
MemWait 0
MemWait 2
MemWait 0
MemWait 3
late
Example 1
Example 2
Tstate 1 2 3 3 4 W W W 5 6 6 E 1 2
Tstate 1 2 2 3 3 4 W W 5 6 6 E 1 2
notMemS0
notMemS0
notMemS1
1
notMemS1
notMemS2
0
notMemS2
notMemS3
9
notMemS3
notMemS4
notMemS4
2
7
5
3
notMemRd
notMemRd
notMemWr
1
late
notMemWr
MemWait 2
MemWait 1
MemWait 3
MemWait 3
Example 3
early
Example 4
0
No wait states inserted
One wait state inserted
2 Two wait states inserted
3 Three wait states inserted
1
Figure 5.19 IMS T400 external configuration
35 / 74
IMS T400
Internal
configuration
7FFFFFF8
7FFFFFF4
Delay
7FFFFFF0
7FFFFFEC
7FFFFF7C
7FFFFF78
7FFFFF74
7FFFFF70
7FFFFF6C
Address
External configuration
MemnotWrD0
MemnotRfD1
MemAD2
MemAD3
MemAD31
MemConfig 1
notMemRd
2
1
2
3
4
5
3
4
5
6
MemConfig connected to inverse of MemnotWrD0
Configuration field 1; T1 configured for 2 periods Tm
Configuration field 2; T2 configured for 2 periods Tm
Configuration field 10; most significant bit of notMemS4 configured high
6
Configuration field 11; refresh interval configured for 36 periods ClockIn
Configuration field 12; refresh enabled
7
Configuration field 13; early write cycle
Figure 5.20 IMS T400 external configuration scan
36 / 74
7
5 External memory interface
Scan
cycle
Mem AD
address
Field Function
Example diagram
1
2
3
4
1
7FFFFF6C
1
T1 least significant bit
0
0
0
0
2
7FFFFF70
1
T1 most significant bit
0
0
0
0
3
7FFFFF74
2
T2 least significant bit
1
0
0
1
4
7FFFFF78
2
T2 most significant bit
0
0
0
0
5
7FFFFF7C
3
T3 least significant bit
1
1
1
1
6
7FFFFF80
3
T3 most significant bit
0
0
0
0
7
7FFFFF84
4
T4 least significant bit
0
0
0
0
8
7FFFFF88
4
T4 most significant bit
0
0
0
0
9
7FFFFF8C
5
T5 least significant bit
0
0
0
0
10
7FFFFF90
5
T5 most significant bit
0
0
0
0
11
7FFFFF94
6
T6 least significant bit
1
0
1
1
12
7FFFFF98
6
T6 most significant bit
0
0
0
0
13
7FFFFF9C
7
notMemS1 least significant bit
0
0
1
1
14
7FFFFFA0
7
0
0
0
0
15
7FFFFFA4
7
0
0
0
0
16
7FFFFFA8
7
1
0
0
0
17
7FFFFFAC
7
notMemS1 most significant bit
0
0
0
0
18
7FFFFFB0
8
notMemS2 least significant bit
1
0
0
1
19
7FFFFFB4
8
1
1
0
1
20
7FFFFFB8
8
0
0
0
1
21
7FFFFFBC
8
0
0
0
0
22
7FFFFFC0
8
notMemS2 most significant bit
0
0
0
0
23
7FFFFFC4
9
notMemS3 least significant bit
1
1
1
1
24
7FFFFFC8
9
0
1
0
0
25
7FFFFFCC
9
0
1
0
1
26
7FFFFFD0
9
0
0
1
0
27
7FFFFFD4
9
notMemS3 most significant bit
0
0
0
0
28
7FFFFFD8
10
notMemS4 least significant bit
0
0
0
1
29
7FFFFFDC
10
0
1
1
1
30
7FFFFFE0
10
1
1
0
0
31
7FFFFFE4
10
0
0
0
0
32
7FFFFFE8
10
notMemS4 most significant bit
0
0
0
0
33
7FFFFFEC
11
Refresh Interval least significant bit
-
-
-
-
34
7FFFFFF0
11
Refresh Interval most significant bit
-
-
-
-
35
7FFFFFF4
12
Refresh Enable
-
-
-
-
36
7FFFFFF8
13
Late Write
0
1
1
0
ª
ª
ª
ª
ª
ª
ª
ª
Table 5.10 IMS T400 external configuration coding
37 / 74
IMS T400
Refresh
interval
Interval
in ms
Field 11
encoding
Complete
cycle (ms)
18
3.6
00
0.922
36
7.2
01
1.843
54
10.8
10
2.765
72
14.4
11
3.686
Table 5.11
IMS T400 memory refresh configuration coding
Refresh intervals are in periods of ClockIn and ClockIn frequency is 5 MHz:
Interval = 18 * 200 = 3600 ns
Refresh interval is between successive incremental refresh addresses.
Complete cycles are shown for 256 row DRAMS.
T400-20
Symbol
Parameter
TMCVRdH
Memory configuration data setup
Min
25
TRdHMCX
Memory configuration data hold
0
TS0LRdH
notMemS0 to configuration data read
Tstate
Tm
Memory configuration
T1
T3
T4
T5
MemnotWrD0
Data
MemnotRfD1
Data
MemAD2–31
Address
T6
412
T1
Data
notMemS0
TS0LRdH
notMemRd
TMCVRdH
MemConfig
TRdHMCX
Data
Figure 5.21 IMS T400 external configuration read cycle timing
38 / 74
Units
ns
ns
388
Table 5.12
T2
Max
ns
6 Events
6
Events
EventReq and EventAck provide an asynchronous handshake interface between an external event and
an internal process. When an external event takes EventReq high the external event channel (additional
to the external link channels) is made ready to communicate with a process. When both the event channel
and the process are ready the processor takes EventAck high and the process, if waiting, is scheduled.
EventAck is removed after EventReq goes low.
EventWaiting is asserted high by the transputer when a process executes an input on the event channel;
typically with the occam EVENT ? ANY instruction. It remains high whilst the transputer is waiting for or
servicing EventReq and is returned low when EventAck goes high. The EventWaiting pin changes near
the falling edge of ProcClockOut and can therefore be sampled by the rising edge of ProcClockOut.
The EventWaiting pin can only be asserted by executing an in instruction on the event channel. The
EventWaiting pin is not asserted high when an enable channel (enbc) instruction is executed on the Event
channel (during an ALT construct in occam, for example). The EventWaiting pin can be asserted by executing the occam input on the event channel (such as Event ? ANY), provided that this does not occur
as a guard in an alternative process. The EventWaiting pin can not be used to signify that an alternative
process (ALT) is waiting on an input from the event channel.
EventWaiting allows a process to control external logic; for example, to clock a number of inputs into a
memory mapped data latch so that the event request type can be determined. This function is not available
on the IMS T414 and IMS T800.
Only one process may use the event channel at any given time. If no process requires an event to occur
EventAck will never be taken high. Although EventReq triggers the channel on a transition from low to
high, it must not be removed before EventAck is high. EventReq should be low during Reset; if not it will
be ignored until it has gone low and returned high. EventAck is taken low when Reset occurs.
If the process is a high priority one and no other high priority process is running, typical latency is 19 full
processor cycles TCPLCPL (38 Tm), and maximum latency (assuming all memory accesses are internal)
is 58 full processor cycles (116 Tm). Setting a high priority task to wait for an event input allows the user
to interrupt a transputer program running at low priority. The time taken from asserting EventReq to the
execution of the microcode interrupt handler in the CPU is four cycles. The following functions take place
during the four cycles:
Cycle 1
Sample EventReq at pad on the rising edge of ProcClockOut and synchronise.
Cycle 2
Edge detect the synchronised EventReq and form the interrupt request.
Cycle 3
Sample interrupt vector for microcode ROM in the CPU.
Cycle 4
Execute the interrupt routine for Event rather than the next instruction.
39 / 74
IMS T400
T400–20
Symbol
Parameter
TVHKH
EventReq response
0
ns
TKHVL
EventReq hold
0
ns
TVLKL
Delay before removal of EventAck
0
TKLVH
Delay before re-assertion of EventReq
0
ns
TKHEWL
EventAck to end of EventWaiting
0
ns
Min
Table 6.1
Event
EventReq
TVHKH
TKHVL
TVLKL
TKLVH
EventAck
TKHEWL
EventWaiting
Process waiting for Event
Event waiting for Process
Figure 6.1 IMS T400 event timing
40 / 74
Max
157
Units
ns
7 Links
7
Links
Two identical INMOS bi-directional serial links provide synchronized communication between processors
and with the outside world. Each link comprises an input channel and output channel. A link between two
transputers is implemented by connecting a link interface on one transputer to a link interface on the other
transputer. Every byte of data sent on a link is acknowledged on the input of the same link, thus each signal
line carries both data and control information.
The quiescent state of a link output is low. Each data byte is transmitted as a high start bit followed by a
one bit followed by eight data bits followed by a low stop bit. The least significant bit of data is transmitted
first. After transmitting a data byte the sender waits for the acknowledge, which consists of a high start bit
followed by a zero bit. The acknowledge signifies both that a process was able to receive the acknowledged data byte and that the receiving link is able to receive another byte. The sending link reschedules
the sending process only after the acknowledge for the final byte of the message has been received.
The IMS T400 links allow an acknowledge packet to be sent before the data packet has been fully received.
This overlapped acknowledge technique is fully compatible with all other INMOS transputer links.
The IMS T400 links support the standard INMOS communication speed of 10 Mbits/sec. In addition they
can be used at 5 or 20 Mbits/sec. Links are not synchronised with ClockIn or ProcClockOut and are insensitive to their phases. Thus links from independently clocked systems may communicate, providing
only that the clocks are nominally identical and within specification.
Links are TTL compatible and intended to be used in electrically quiet environments, between devices on
a single printed circuit board or between two boards via a backplane. Direct connection may be made between devices separated by a distance of less than 300 millimetres. For longer distances a matched
100 ohm transmission line should be used with series matching resistors RM. When this is done the line
delay should be less than 0.4 bit time to ensure that the reflection returns before the next data bit is sent.
Buffers may be used for very long transmissions. If so, their overall propagation delay should be stable
within the skew tolerance of the link, although the absolute value of the delay is immaterial.
Link speeds can be set by LinkSpecial, Link0Special and Link1Special. Table 7.1 shows uni-directional
and bi-directional data rates in Kbytes/sec for each link speed; LinknSpecial is to be read as Link0Special when selecting link 0 speed and as Link1Special for link 1. Data rates are quoted for a transputer
using internal memory, and will be affected by a factor depending on the number of external memory accesses and the length of the external memory cycle.
Link
Linkn
Special
Special
Mbits/sec
Uni
Bi
0
0
10
910
1250
0
1
5
450
670
1
0
10
910
1250
1
1
20
1740
2350
Table 7.1
H
H
0
1
2
3
Kbytes/sec
Speed Settings for Transputer Links
4
5
6
7
L
Data
H
L
Ack
Figure 7.1 IMS T400 link data and acknowledge packets
41 / 74
IMS T400
Symbol
Parameter
TJQr
Min
Nom
Max
Units
LinkOut rise time
20
ns
TJQf
LinkOut fall time
10
ns
TJDr
LinkIn rise time
20
ns
TJDf
LinkIn fall time
20
ns
TJQJD
Buffered edge delay
TJBskew
Variation in TJQJD
0
Notes
ns
20 Mbits/s
3
ns
1
10 Mbits/s
10
ns
1
5 Mbits/s
30
ns
1
@ f=1MHz
7
pF
50
pF
CLIZ
LinkIn capacitance
CLL
LinkOut load capacitance
RM
Series resistor for 100W transmission line
56
ohms
Notes
1 This is the variation in the total delay through buffers, transmission lines, differential receivers
etc., caused by such things as short term variation in supply voltages and differences in delays
for rising and falling edges.
Table 7.2 Link
90%
LinkOut
10%
TJQr
TJQf
90%
LinkIn
10%
TJDr
Figure 7.2 IMS T400 link timing
LinkOut
1.5 V
Latest TJQJD
Earliest TJQJD
LinkIn
1.5 V
TJBskew
Figure 7.3 IMS T400 buffered link timing
42 / 74
TJDf
7 Links
Transputer family device A
LinkOut
LinkIn
LinkIn
LinkOut
Transputer family device B
Figure 7.4 Links directly connected
Transputer family device A
Zo = 100 ohms
RM
LinkOut
LinkIn
LinkIn
LinkOut
RM
Zo = 100 ohms
Transputer family device B
Figure 7.5 Links connected by transmission line
Transputer family device A
LinkOut
LinkIn
buffers
LinkIn
LinkOut
Transputer family device B
Figure 7.6 Links connected by buffers
43 / 74
IMS T400
8
Electrical specifications
8.1
DC electrical characteristics
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
0
7.0
V
1,2,3
–0.5
VDD+0.5
V
1,2,3
mA
4
VDD
DC supply voltage
VI, VO
Voltage on input and output pins
II
Input current
25
tOSC
Output short circuit time (one pin)
1
s
2
150
oC
2
125
oC
2
2
W
Storage temperature
TS
–65
TA
Ambient temperature under bias
PDmax
Maximum allowable dissipation
–55
Notes
1 All voltages are with respect to GND.
2 This is a stress rating only and functional operation of the device at these or any other conditions
beyond those indicated in the operating sections of this specification is not implied. Stresses
greater than those listed may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
3 This device contains circuitry to protect the inputs against damage caused by high static voltages
or electrical fields. However, it is advised that normal precautions be taken to avoid application
of any voltage higher than the absolute maximum rated voltages to this high impedance circuit.
Unused inputs should be tied to an appropriate logic level such as VDD or GND.
4 The input current applies to any input or output pin and applies when the voltage on the pin is
between GND and VDD.
Table 8.1
SYMBOL
Absolute maximum ratings
PARAMETER
VDD
DC supply voltage
VI, VO
Input or output voltage
CL
Load capacitance on any pin
TA
Operating temperature range IMS T400-S
TA
Operating temperature range IMS T400-I
MIN
MAX
UNITS
NOTES
4.5
5.5
V
1
0
VDD
V
1,2
60
pF
3
70
oC
4
+85
oC
4,5
0
–40
Notes
1 All voltages are with respect to GND.
2 Excursions beyond the supplies are permitted but not recommended; see DC characteristics.
3 Excluding LinkOut load capacitance.
4 Air flow rate 400 linear ft/min transverse air flow.
5 Industrial temperature range part.
Table 8.2
44 / 74
Operating conditions
8 Electrical specifications
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
VIH
High level input voltage
2.0
VDD+0.5
V
1, 2
VIL
Low level input voltage
–0.5
0.8
V
1, 2
II
Input current
@ GND<VI<VDD
mA
1, 2
VOH
Output high voltage
@ IOH=2mA
V
1, 2
VOL
Output low voltage
@ IOL=4mA
V
1, 2
IOZ
Tristate output current
@ GND<V0<VDD
mA
1, 2
PD
Power dissipation
1.0
W
2, 3
CIN
Input capacitance
@ f=1MHz
7
pF
COZ
Output capacitance
@ f=1MHz
10
pF
10
VDD–1
0.4
10
Notes
1 All voltages are with respect to GND.
2 Parameters for IMS T400 measured at 4.75V<VDD<5.25V and 0oC<TA<70oC.
Input clock frequency = 5 MHz.
3 Power dissipation varies with output loading and program execution.
Power dissipation for processor operating at 20 MHz.
Table 8.3
8.2
DC characteristics
Equivalent circuits
IOL
1.5V
D.U.T.
1MW
50pF
IOH
GND
Note: This circuit represents the device sinking IOL and sourcing IOH with a 50pF capacitive load.
Figure 8.1 Load circuit for AC measurements
45 / 74
IMS T400
VDD–1
Inputs
VIH
0V
VDD–1
Inputs
0V
VIL
tp HL
VDD
1.5V
Outputs
0V
tp LH
VDD
1.5V
Outputs
0V
Figure 8.2 AC measurements timing waveforms
8.3
AC timing characteristics
Symbol
Parameter
Min
Max
Units Notes
TDr
Input rising edges
2
20
ns
1,2
TDf
Input falling edges
2
20
ns
1,2
TQr
Output rising edges
25
ns
1,2
TQf
Output falling edges
15
ns
1,2
TS0LaX
Address hold after notMemS0
a+8
ns
3
a–8
Notes
1 Non-link pins; see section on links.
2 All inputs except ClockIn; see section on ClockIn.
3 a is T2 where T2 can be from one to four periods Tm in length.
Address lines include MemnotWrD0, MemnotRfD1, MemAD2-31.
Table 8.4 Input and output edges
46 / 74
8 Electrical specifications
90%
90%
10%
10%
TDf
TDr
90%
90%
10%
10%
TQf
TQr
Figure 8.3 IMS T400 input and output edge timing
1.5 V
TS0LaX
90%
10%
Figure 8.4 IMS T400 tristate timing relative to notMemS0
30
30
Rise time
Rise time
Time
ns
20
10
Fall time
20
Time
ns
10
40
60
80 100
Load capacitance pF
Link
Fall time
Skew
1
40
60
80 100
Load capacitance pF
EMI
Notes
1 Skew is measured between ProcClockOut with a load of 2 Schottky TTL inputs and 30pF
and notMemS0 with a load of 2 Schottky TTL inputs and varying capacitance.
Figure 8.5 Typical rise/fall times
47 / 74
IMS T400
8.4
Power rating
Internal power dissipation (PINT) of transputer and peripheral chips depends on VDD, as shown in
figure 8.6. PINT is substantially independent of temperature.
600
T400–20
500
Power
PINT
(mW)
400
300
4.4
4.6
4.8
5.0
5.2
5.4
5.6
VDD (Volts)
Figure 8.6 IMS T400 internal power dissipation vs VDD
Total power dissipation (PD) of the chip is
PD = PINT + PIO
where PIO is the power dissipation in the input and output pins; this is application dependent.
Internal working temperature TJ of the chip is
TJ = TA + qJA * PD
where TA is the external ambient temperature in oC and qJA is the junction-to-ambient thermal resistance
in oC/W.
Further information about device thermal characteristics can be found in section 9.5.
48 / 74
9 Package details
9
Package details
9.1
84 pin grid array package
Figure 9.1 IMS T400 84-pin PGA package pinout
49 / 74
IMS T400
Figure 9.2 IMS T400 84-pin PGA package dimensions
50 / 74
9 Package details
DIMENSIONS
REF.
CONTROL DIM. INCHES
ALTERNATIVE DIM. mm
Min
Nom
Max
Min
Nom
Max
A
0.135
0.147
0.160
3.429
3.734
4.064
A1
–
0.050
–
–
1.270
–
A2
0.085
0.097
0.110
2.159
2.464
2.794
B
0.016
0.018
0.020
0.406
0.457
0.508
B1
–
0.050
–
–
1.270
–
D
1.050
1.060
1.070
26.670
26.924
27.178
D1
–
0.900
–
–
22.860
–
E
1.050
1.060
1.070
26.670
26.924
27.178
E1
–
0.900
–
–
22.860
–
e
–
0.100
–
–
2.540
–
L
0.120
0.130
0.140
3.048
3.302
3.556
Notes
REF
REF
REF
BSC
Notes:
1 Lead finish to be 60 µinch min. Au on 80 µinch Ni plate, for commercial, and 100 µich min. Au
on 80 µinch Ni plate, for military applications.
2 Maximum lead displacement from the notional centre line will be no greater than + 0.005 inch.
51 / 74
IMS T400
9.2
84 pin PLCC package
Figure 9.3 IMS T400 84-pin PLCC package pinout
52 / 74
9 Package details
Figure 9.4 IMS T400 84-pin PLCC package dimensions
53 / 74
IMS T400
DIMENSIONS
REF.
CONTROL DIM. INCHES
ALTERNATIVE DIM. mm
Notes
Min
Nom
Max
Min
Nom
Max
A
0.165
0.170
0.200
4.191
4.318
5.080
A1
0.020
–
–
0.508
–
–
A3
0.090
–
0.130
2.290
–
3.302
B
0.013
–
0.023
0.330
–
0.584
B1
0.025
–
0.035
0.635
–
0.889
C
0.0075
0.008
0.0085
0.191
0.203
0.216
D
1.185
1.190
1.195
30.099
30.266
30.353
D1
1.150
1.155
1.160
29.210
29.337
29.464
D2
1.090
1.120
1.130
27.686
28.488
28.702
D3
–
1.000
–
–
24.400
–
E
1.185
1.190
1.195
30.099
30.266
30.353
E1
1.150
1.155
1.160
29.210
29.337
29.464
E2
1.090
1.120
1.130
27.686
28.488
28.702
E3
–
1.000
–
–
25.400
–
REF
e
–
0.050
–
–
1.270
–
BSC
G
–
–
0.004
–
–
0.102
M
0.042
–
0.048
1.067
–
1.219
M1
0.042
–
0.056
1.067
–
1.422
REF
Notes:
1 Lead finish to be 60 Sn/40 Pb solder plate.
2 Maximum lead displacement from the notional centre line will be no greater than + 0.007 inches
54 / 74
9 Package details
9.3
100 pin plastic quad flat pack (PQFP) package
Figure 9.5 IMS T400 100-pin PQFP package pinout
55 / 74
IMS T400
Figure 9.6 IMS T400 100-pin PQFP package dimensions
56 / 74
9 Package details
DIMENSIONS
REF.
CONTROL DIM. mm
ALTERNATIVE DIM. INCHES
Notes
Min
Nom
Max
Min
Nom
Max
A
–
–
3.400
–
–
0.134
A1
0.100
–
–
0.004
–
–
A2
2.540
2.800
3.050
0.096
0.110
0.120
B
0.220
–
0.380
0.009
–
0.015
C
0.130
–
0.230
0.005
–
0.009
D
22.950
–
24.150
0.904
–
0.951
D1
19.900
20.000
20.100
0.783
0.787
0.791
D3
–
18.850
–
–
0.742
–
E
16.950
–
18.150
0.667
–
0.715
E1
13.900
14.000
14.100
0.547
0.551
0.555
E3
–
12.350
–
–
0.486
–
REF
e
–
0.650
–
–
0.026
–
BSC
G
–
–
0.100
–
–
0.004
K
05
–
75
05
–
75
L
0.650
0.800
0.950
0.026
0.031
0.037
Zd
–
0.580
–
–
0.23
–
REF
Ze
–
0.830
–
–
0.033
–
REF
REF
Notes:
1 Lead finish to be 60 Sn/40 Pb solder plate.
2 Maximum lead displacement from the notional centre line will be no greater than + 0.125 mm.
57 / 74
IMS T400
9.4
100 pin thin plastic quad flat pack (TQFP) package
Figure 9.7 IMS T400 100-pin thin plastic quad flatpack (TQFP) package pinout
58 / 74
9 Package details
Figure 9.8 IMS T400 100-pin TQFP package dimensions
59 / 74
IMS T400
DIMENSIONS
REF.
CONTROL DIM. mm
ALTERNATIVE DIM. INCHES
Min
Nom
Max
Min
Nom
Max
A
–
–
1.60
–
–
0.063
A1
0.05
–
0.15
0.002
–
0.006
A2
1.35
1.4
1.45
0.053
0.055
0.057
B
0.17
–
0.27
0.007
–
0.011
C
–
–
0.17
–
–
0.007
D
15.75
16.00
16.25
0.620
0.630
0.640
D1
13.95
14.00
14.05
0.549
0.551
0.553
D3
–
12.00
–
–
0.472
–
E
15.75
16.00
16.25
0.620
0.630
0.640
E1
13.95
14.00
14.05
0.549
0.551
0.553
E3
–
12.00
–
–
0.472
–
e
–
0.500
–
–
0.020
–
G
–
–
0.08
–
–
0.0032
K
05
–
75
05
–
75
L
0.50
0.60
0.75
0.020
0.024
0.030
Notes
REF
BSC
Notes:
1 Lead finish to be 60Sn/40Pb solder plate.
2 Maximum lead displacement from the notional centre line will be no greater than + 0.08mm.
9.5
Thermal specification
The IMS T400 is tested to a maximum silicon temperature of 100_C. For operation within the given specifications, the case temperature should not exceed 85_C.
For temperatures above 85_C the operation of the device cannot be guaranteed and reliability may be
impaired.
For further information on reliability refer to the SGS–THOMSON Microelectronics Quality and Reliability
Program.
60 / 74
10 Ordering
10
Ordering
This section indicates the designation of speed and package selections for the various devices. Speed
of ClockIn is 5 MHz for all parts. Transputer processor cycle time is nominal; it can be calculated more
exactly using the phase lock loop factor PLLx, as detailed in the external memory section.
For availability contact your local SGS–THOMSON sales office or authorized distributor.
SGS-THOMSON
designation
Processor
clock speed
Processor
cycle time
PLLx
IMS T400-G20S
20.0 MHz
50 ns
4.0
84 pin ceramic pin grid array
IMS T400-J20S
20.0 MHz
50 ns
4.0
84 pin plastic PLCC J-Bend
IMS T400-X20I
20.0 MHz
50 ns
4.0
100 pin plastic quad flat pack
IMS T400-T20S
20.0 MHz
50 ns
4.0
100 pin thin plastic quad flat pack
Table 10.1
Package
IMS T400 ordering details
61 / 74
IMS T400
11
Transputer instruction set summary
11.1
Introduction
The Function Codes table 11.9 (page 66) gives the basic function code set. Where the operand value is
less than 16, a single byte encodes the complete instruction. If the operand value is greater than 15, one
prefix instruction (pfix) is required for each additional four bits of the operand. If the operand is negative
the first prefix instruction will be nfix. Examples of prefix coding are given in table 11.1.
Mnemonic
ldc
#3
ldc
#35
Function code
Memory code
#4
#43
is coded as
pfix
#3
#2
#23
ldc
#5
#4
#45
ldc
#987
is coded as
pfix
#9
#2
#29
pfix
#8
#2
#28
ldc
#7
#4
#47
ldc
–31
( ldc #FFFFFFE1)
( ldc #FFE1) {
is coded as
{
nfix
#1
#6
#61
ldc
#1
#4
#41
IMS T222, IMS T225
Table 11.1 prefix coding
Tables 11.10 to 11.30 (pages 66–73) give details of the operation codes. Where an operation code is less
than 16 (e.g. add: operation code 05), the operation can be stored as a single byte comprising the operate
function code F and the operand (5 in the example). Where an operation code is greater than 15 (e.g. ladd:
operation code 16), the prefix function code 2 is used to extend the instruction.
Mnemonic
add
Function code
( op. code #5)
Memory code
#F5
is coded as
opr
ladd
add
#F
( op. code #16)
#F5
#21F6
is coded as
pfix
#1
#2
#21
opr
#6
#F
#F6
Table 11.2 operate coding
62 / 74
11 Transputer instruction set summary
11.1.1
Product identity numbers
The load device identity (lddevid) instruction (table 11.10) pushes the device type identity into the A register. Each product is allocated a unique group of numbers for use with the lddevid instruction. Product identity numbers are given in table 11.3.
Product
IMS T425
IMS T805
IMS T225
IMS T400
Identity numbers
0 to 9 inclusive
10 to 19 inclusive
40 to 49 inclusive
50 to 59 inclusive
Table 11.3 Product identity numbers
11.1.2
Floating point unit
In the floating point unit (FPU) basic addition, subtraction, multiplication and division operations are performed by single instructions. However, certain less frequently used floating point instructions are selected
by a value in register A (when allocating registers, this should be taken into account). A load constant instruction ldc is used to load register A; the floating point entry instruction fpentry then uses this value to
select the floating point operation. This pair of instructions is termed a selector sequence.
In the Floating Point Operation Codes tables 11.23 to 11.29, a selector sequence code is indicated in the
Memory Code column by s. The code given in the Operation Code column is the indirection code, the operand for the ldc instruction.
The FPU and processor operate concurrently, so the actual throughput of floating point instructions is better than that implied by simply adding up the instruction times. For full details see Transputer Instruction
Set – A Compiler Writer’s Guide.
11.1.3
Notation
The Processor Cycles column refers to the number of periods TPCLPCL (refer to ProcClockOut) taken
by an instruction executing in internal memory. The number of cycles is given for the basic operation only;
where the memory code for an instruction is two bytes, the time for the prefix function (one cycle) should
be added. Some instruction times vary.Where a letter is included in the cycles column it is interpreted from
table 11.4.
Ident
b
m{
Interpretation
Bit number of the highest bit set in register A. Bit 0 is the least significant bit.
Bit number of the highest bit set in the absolute value of register A. Bit 0 is the least significant bit.
n
Number of places shifted.
w
Number of words in the message. Part words are counted as full words. If the message is not
word aligned the number of words is increased to include the part words at either end of the
message.
p{
Number of words per row.
r{
Number of rows.
{ does not apply to IMS T225
Table 11.4 Instruction set interpretation
63 / 74
IMS T400
The DEF column of the tables indicates the descheduling/error features of an instruction as described in
table .
Ident
Feature
See section:
D
The instruction is a descheduling point
11.2
E
The instruction will affect the Error flag
11.3
The instruction will affect the FP_Error flag
11.6
F{
{ applies to IMS T805 only
Table 11.5 Instruction features
11.2
Descheduling points
The instructions in table 11.6 are the only ones at which a process may be descheduled. They are also
the ones at which the processor will halt if the Analyse pin is asserted (refer to Analyse section).
input message
output message
output byte
output word
timer alt wait
timer input
stop on error
alt wait
jump
loop end
end process
start process
Table 11.6 Descheduling point instructions
11.3
Error instructions
The instructions in table 11.7 are the only ones which can affect the Error flag directly. Note, however, that
the floating point unit error flag FP_Error is set by certain floating point instructions (section 11.6), and that
Error can be set from this flag by fpcheckerror.
add
add constant
subtract
multiply
fractional multiply {
divide
long add
long subtract
long divide
set error
testerr
fpcheckerror }
check word
check subscript from 0
check single
remainder
check count from 1
{ does not apply to IMS T225
} applies to IMS T805 only
Table 11.7 Error setting instructions
11.4
Debugging support
Table 11.20 (page 70) contains a number of instructions to facilitate the implementation of breakpoints.
These instructions overload the operation of j0. Normally j0 is a no-op which might cause descheduling.
Setj0break enables the breakpointing facilities and causes j0 to act as a breakpointing instruction. When
breakpointing is enabled, j0 swaps the current Iptr and Wptr with an Iptr and Wptr stored above MemStart. The break instruction does not cause descheduling, and preserves the state of the registers. It is possible to single step the processor at machine level using these instructions. Refer to Support for debugging/breakpointing in transputers (technical note 61) for more detailed information regarding debugger
support.
11.5
Block move
The block move instructions (Table 11.21) move any number of bytes from any byte boundary in memory,
to any other byte boundary, using the smallest possible number of word read, and word or part-word writes.
64 / 74
11 Transputer instruction set summary
A block move instruction can be interrupted by a high priority process. On interrupt, block move is completed to a word boundary, independent of start position. When restarting after interrupt, the last word written is written again. This appears as an unnecessary read and write in the simplest case of word aligned
block moves, and may cause problems with FIFOs. This problem can be overcome by incrementing the
saved destination (BregIntSaveLoc) and source pointer (CregIntSaveLoc) values by BytesPerWord
during the high priority process.
11.6
Floating point errors (IMS T805 only)
The FPU has its own error flag FP_Error. This reflects the state of evaluation within the FPU and is set
in circumstances where invalid operations, division by zero or overflow exceptions to the ANSI-IEEE
754-1985 standard would be flagged. FP_Error is also set if an input to a floating point operation is infinite
or is not a number (NaN). The FP_Error flag can be set, tested and cleared without affecting the main Error
flag, but can also set Error when required. Depending on how a program is compiled, it is possible for both
unchecked and fully checked floating point arithmetic to be performed.
The instructions in table 11.8 are the only ones which can affect the floating point error flag FP_Error.
Error is set from this flag by fpcheckerror if FP_Error is set.
fpadd
fpsub
fpmul
fpdiv
fpldnladdsn
fpldnladddb
fpldnlmulsn
fpldnlmuldb
fpremfirst
fpusqrtfirst
fpgt
fpeq
fpuseterror
fpuclearerror
fptesterror
fpuexpincby32
fpuexpdecby32
fpumulby2
fpudivby2
fpur32tor64
fpur64tor32
fpucki32
fpucki64
fprtoi32
fpuabs
fpint
Table 11.8 Floating point error setting instructions
11.7
General instructions
The following tables list the complete instruction set which is common to all variants of the transputer. Exceptions are noted at the bottom of each table by { or }.
65 / 74
IMS T400
Function
Code
Memory
Code
Mnemonic
0
1
2
3
4
5
6
7
8
9
A
0X
1X
2X
3X
4X
5X
6X
7X
8X
9X
AX
j
ldlp
pfix
ldnl
ldc
ldnlp
nfix
ldl
adc
call
cj
B
C
D
E
F
BX
CX
DX
EX
FX
ajw
eqc
stl
stnl
opr
Processor
Cycles
3
1
1
2
1
1
1
2
1
7
2
4
1
2
1
2
–
Name
jump
load local pointer
prefix
load non–local
load constant
load non–local pointer
negative prefix
load local
add constant
call
conditional jump (not taken)
conditional jump (taken)
adjust workspace
equals constant
store local
store non-local
operate
DEF
D
E
Table 11.9 Function codes
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
2A
3E
3D
18
50
1C
17
54
17C
7E
22FA
23FE
23FD
21F8
25F0
21FC
21F7
25F4
2127FC
27FE
testpranal
saveh
savel
sthf
sthb
stlf
stlb
sttimer
lddevid
ldmemstartval
2
4
4
1
1
1
1
1
1
1
Table 11.10
66 / 74
Name
test processor analyzing
save high priority queue registers
save low priority queue registers
store high priority front pointer
store high priority back pointer
store low priority front pointer
store low priority back pointer
store timer
load device identity
load value of memstart address
Processor initialisation operation codes
DEF
11 Transputer instruction set summary
Operation
Memory
Mnemonic
Processor Cycles
Code
Code
24F6
24FB
23F3
23F2
24F1
24F0
and
or
xor
not
shl
shr
16-bit
devices
1
1
1
1
n+2
n+2
32-bit
devices
1
1
1
1
n+2
n+2
46
4B
33
32
41
40
05
0C
53
72 {
F5
FC
25F3
27F2
add
sub
mul
fmul
1
1
23
1
1
38
35
40
39
37
2
1
1
b+4
m+5
2C
22FC
div
1F
21FF
rem
09
F9
gt
04
F4
diff
52
25F2
sum
08
F8
prod
08
F8
prod
{ does not apply to IMS T225
24
21
2
1
1
b+4
m+5
Table 11.11
Operation
Memory Mnemonic
Code
Code
16
38
37
4F
31
1A
36
21F6
23F8
23F7
24FF
23F1
21FA
23F6
ladd
lsub
lsum
ldiff
lmul
ldiv
lshl
35
23F5
lshr
19
21F9
norm
Name
DEF
and
or
exclusive or
bitwise not
shift left
shift right
add
subtract
multiply
fractional multiply (no rounding)
fractional multiply (rounding)
divide
remainder
greater than
difference
sum
product for positive register A
product for negative register A
E
E
E
E
E
E
E
Arithmetic/logical operation codes
Processor Cycles
16-bit
devices
2
2
3
3
17
19
n+3
n–12
n+3
n–12
n+5
n–10
3
32-bit
devices
2
2
3
3
33
35
n+3
n–28
n+3
n–28
n+5
n–26
3
Name
long add
long subtract
long sum
long diff
long multiply
long divide
long shift left (n<32)
long shift left(n 32)
long shift right (n<32)
long shift right (n 32)
normalise (n<32)
normalise (n 32)
normalise (n=64)
DEF
E
E
E
{ (n<16)
{ (n 16)
{ (n<16)
{ (n 16)
{ (n<16)
{ (n 16)
{ (n=32)
{ for IMS T225
Table 11.12
Long arithmetic operation codes
67 / 74
IMS T400
Operation
Code
Memory
Code
00
F0
3A
Mnemonic
Processor
Cycles
Name
rev
1
reverse
23FA
xword
4
extend to word
56
25F6
cword
5
check word
1D
21FD
xdble
2
extend to double
4C
24FC
csngl
3
check single
42
24F2
mint
1
minimum integer
5A
25FA
dup
1
duplicate top of stack
79
27F9
pop
1
pop processor stack
Table 11.13
Operation Memory Mnemonic
DEF
E
E
General operation codes
Processor Cycles
Name
Code
Code
02
F2
bsub
16-bit
devices
1
0A
FA
wsub
2
2
word subscript
81 {
28F1
wsubdb
3
3
form double word subscript
34
23F4
bcnt
2
2
byte count
3F
23FF
wcnt
4
5
word count
01
F1
lb
5
5
load byte
3B
23FB
sb
4
4
store byte
4A
24FA
move
2w+8
2w+8
DEF
32-bit
devices
1
byte subscript
move message
{ does not apply to IMS T225
Table 11.14
Mnemonic
Indexing/array operation codes
Operation
Code
Memory
Code
Processor
Cycles
Name
DEF
22
22F2
ldtimer
2
load timer
2B
22FB
tin
30
timer input (time future)
D
4
timer input (time past)
D
4E
24FE
talt
4
timer alt start
51
25F1
taltwt
15
timer alt wait (time past)
D
48
timer alt wait (time future)
D
47
24F7
enbt
8
enable timer
2E
22FE
dist
23
disable timer
Table 11.15 Timer handling operation codes
68 / 74
11 Transputer instruction set summary
Operation
Code
Memory
Code
Mnemonic
07
0B
0F
0E
F7
FB
FF
FE
43
44
24F3
24F4
alt
altwt
45
24F5
49
30
in
out
outword
outbyte
Processor
Cycles
2w+19
2w+19
23
23
Name
DEF
input message
output message
output word
output byte
D
D
D
D
alt
alt
alt
alt
D
D
altend
2
5
17
4
24F9
23F0
enbs
diss
3
4
enable skip
disable skip
12
48
21F2
24F8
resetch
enbc
2F
22FF
disc
3
7
5
8
reset channel
enable channel (ready)
enable channel (not ready)
disable channel
start
wait (channel ready)
wait (channel not ready)
end
Table 11.16 Input/output operation codes
Operation
Code
Memory
Code
20
1B
3C
06
21
22F0
21FB
23FC
F6
22F1
Mnemonic
ret
ldpi
gajw
gcall
lend
5
2
2
4
10
5
Table 11.17
Operation
Code
Memory
Code
0D
03
39
15
1E
FD
F3
23F9
21F5
21FE
Processor
Cycles
Mnemonic
startp
endp
runp
stopp
ldpri
Table 11.18
Name
return
load pointer to instruction
general adjust workspace
general call
loop end (loop)
loop end (exit)
DEF
D
D
Control operation codes
Processor
Cycles
12
13
10
11
1
Name
start process
end process
run process
stop process
load current priority
DEF
D
Scheduling operation codes
69 / 74
IMS T400
Operation
Code
Memory
Code
Mnemonic
13
4D
29
21F3
24FD
22F9
csub0
ccnt1
testerr
10
55
57
58
59
21F0
25F5
25F7
25F8
25F9
seterr
stoperr
clrhalterr
sethalterr
testhalterr
Table 11.19
Operation
Code
Memory
Code
0
00
jump 0
B1
2BF1
break
B2
B3
B4
7A
7B
7C
7D
2BF2
2BF3
2BF4
27FA
27FB
27FC
27FD
clrj0break
setj0break
testj0break
timerdisableh
timerdisablel
timerenableh
timerenablel
Processor
Cycles
2
3
2
3
1
2
1
1
2
Name
check subscript from 0
check count from 1
test error false and clear (no error)
test error false and clear (error)
set error
stop on error (no error)
clear halt–on–error
set halt–on–error
test halt–on–error
E
E
E
D
Error handling operation codes
Mnemonic
Table 11.20
Mnemonic
Processor
Cycles
Name
DEF
3
11
13
9
11
1
1
2
1
1
6
6
jump 0 (break not enabled)
jump 0 (break enabled, high priority)
jump 0 (break enabled, low priority)
break (high priority)
break (low priority)
clear jump 0 break enable flag
set jump 0 break enable flag
test jump 0 break enable flag set
disable high priority timer interrupt
disable low priority timer interrupt
enable high priority timer interrupt
enable low priority timer interrupt
D
Debugger support codes
Operation
Code
Memory
Code
5B {
25FB
move2dinit
8
5C {
25FC
move2dall
(2p+23)*r
2D block copy
5D {
25FD
move2dnonzero
(2p+23)*r
2D block copy non-zero bytes
5E {
25FE
(2p+23)*r
2D block copy zero bytes
Processor
Cycles
Name
initialise data for 2D block move
{ does not apply to IMS T225
Table 11.21 2D block move operation codes
70 / 74
DEF
DEF
11 Transputer instruction set summary
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
Name
74
27F4
crcword
35
calculate crc on word
75
27F5
crcbyte
11
calculate crc on byte
76
27F6
bitcnt
b+2
count bits set in word
77
27F7
bitrevword
36
78
27F8
bitrevnbits
n+4
DEF
reverse bits in word
reverse bottom n bits in word
Table 11.22 CRC and bit operation codes
11.8
Floating point instructions
11.9
Floating point instructions for IMS T805 only
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
Name
DEF
8E
28FE
fpldnlsn
2
fp load non-local single
8A
28FA
fpldnldb
3
fp load non-local double
86
28F6
fpldnlsni
4
fp load non-local indexed single
82
28F2
fpldnldbi
6
fp load non-local indexed double
9F
29FF
fpldzerosn
2
load zero single
A0
2AF0
fpldzerodb
2
load zero double
AA
2AFA
fpldnladdsn
8/11
fp load non local & add single
F
A6
2AF6
fpldnladddb
9/12
fp load non local & add double
F
AC
2AFC
fpldnlmulsn
13/20
fp load non local & multiply single
F
A8
2AF8
fpldnlmuldb
21/30
fp load non local & multiply double
F
88
28F8
fpstnlsn
2
fp store non-local single
84
28F4
fpstnldb
3
fp store non-local double
9E
29FE
fpstnli32
4
store non-local int32
Processor cycles are shown as Typical/Maximum cycles.
Table 11.23
Floating point load/store operation codes
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
Name
AB
2AFB
fpentry
1
floating point unit entry
A4
2AF4
fprev
1
fp reverse
A3
2AF3
fpdup
1
fp duplicate
DEF
Table 11.24 Floating point general operation codes
71 / 74
IMS T400
Operation
Code
Memory
Code
22
s
06
Mnemonic
Processor
Cycles
Name
fpurn
1
set rounding mode to round nearest
s
fpurz
1
set rounding mode to round zero
04
s
fpurp
1
set rounding mode to round positive
05
s
fpurm
1
set rounding mode to round minus
Table 11.25
DEF
Floating point rounding operation codes
Operation
Code
Memory
Code
Mnemonic
83
28F3
fpchkerror
1
check fp error
E
9C
29FC
fptesterror
2
test fp error false and clear
F
23
s
fpuseterror
1
set fp error
F
9C
s
fpuclearerror
1
clear fp error
F
Table 11.26
Mnemonic
Processor
Cycles
Name
DEF
Floating point error operation codes
Operation
Code
Memory
Code
Processor
Cycles
Name
DEF
94
29F4
fpgt
4/6
fp greater than
F
95
29F5
fpeq
3/5
fp equality
F
92
29F2
fpordered
3/4
fp orderability
91
29F1
fpnan
2/3
fp NaN
93
29F3
fpnotfinite
2/2
fp not finite
0E
s
fpuchki32
3/4
check in range of type int32
F
0F
s
fpuchki64
3/4
check in range of type int64
F
Processor cycles are shown as Typical/Maximum cycles.
Table 11.27
Floating point comparison operation codes
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
Name
07
s
fpur32tor64
3/4
real32 to real64
F
08
s
fpur64tor32
6/9
real64 to real32
F
9D
29FD
fprtoi32
7/9
real to int32
F
96
29F6
fpi32tor32
8/10
int32 to real32
98
29F8
fpi32tor64
8/10
int32 to real64
9A
29FA
fpb32tor64
8/8
bit32 to real64
0D
s
fpunoround
2/2
real64 to real32, no round
A1
2AF1
fpint
5/6
round to floating integer
Processor cycles are shown as Typical/Maximum cycles.
Table 11.28 Floating point conversion operation codes
72 / 74
DEF
F
11 Transputer instruction set summary
Operation
Memory
Code
Code
87
28F7
89
Processor Cycles
Mnemonic
Single
Double
fpadd
6/9
6/9
fp add
F
28F9
fpsub
6/9
6/9
fp subtract
F
8B
28FB
fpmul
11/18
18/27
fp multiply
F
8C
28FC
fpdiv
16/28
31/43
fp divide
F
0B
s
2/2
2/2
fp absolute
F
8F
28FF
fpremfirst
36/46
36/46
fp remainder first step
F
90
29F0
fpremstep
32/36
32/36
fp remainder iteration
01
s
fpusqrtfirst
27/29
27/29
fp square root first step
02
s
fpusqrtstep
42/42
42/42
fp square root step
03
s
fpusqrtlast
8/9
8/9
fp square root end
0A
s
fpuexpinc32
6/9
6/9
multiply by 232
fpuabs
Name
DEF
F
F
232
F
09
s
fpuexpdec32
6/9
6/9
divide by
12
s
fpumulby2
6/9
6/9
multiply by 2.0
F
11
s
fpudivby2
6/9
6/9
divide by 2.0
F
Processor cycles are shown as Typical/Maximum cycles.
Table 11.29 Floating point arithmetic operation codes
11.10 Floating point instructions for IMS T400 and IMS T425 only
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
73
27F3
cflerr
3
check floating point error
9C
29FC
fptesterr
1
load value true (FPU not present)
63
26F3
unpacksn
15
unpack single length fp number
6D
26FD
roundsn
12/15
round single length fp number
6C
26FC
postnormsn
5/30
post–normalise correction of single
length fp number
71
27F1
ldinf
1
Name
DEF
E
load single length infinity
Processor cycles are shown as Typical/Maximum cycles.
Table 11.30 Floating point support operation codes
73 / 74
IMS T400
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This
publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of
SGS-THOMSON Microelectronics.
E
,
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74 / 74