INTERSIL ISL33001IBZ

ISL33001, ISL33002, ISL33003
Features
The ISL33001, ISL33002, ISL33003 2-Channel Bus
Buffers provide the necessary buffering for extending the
bus capacitance beyond the 400pF maximum specified
by the I2C specification. In addition, the ISL33001,
ISL33002, ISL33003 feature rise time accelerator
circuitry to reduce power consumption from passive bus
pull-up resistors and improve data-rate performance. All
devices also include hot swap circuitry to prevent
corruption of the data and clock lines when I2C devices
are plugged into a live backplane and level translation for
mixed supply voltage applications.
• 2 Channel I2C Compatible Bi-Directional Buffer
The ISL33001, ISL33002, ISL33003 operates at supply
voltages from +2.3V to +5.5V at a temperature range of
-40°C to +85°C.
• Logic Level Translation (ISL33002 and ISL33003)
Summary of Features
• Pb-Free (RoHS Compliant) 8 Ld SOIC (ISL33001
only), 8 Ld TDFN (3mmx3mm) and 8 Ld MSOP
packages
PART
LEVEL
ENABLE READY ACCELERATOR
NUMBER TRANSLATION
PIN
PIN
DISABLE
ISL33001
No
Yes
Yes
No
ISL33002
Yes
No
No
Yes
ISL33003
Yes
Yes
No
No
Related Literature* (see page 15)
• AN1543, “ISL33001EVAL1Z, ISL33002EVAL1Z,
ISL33003EVAL1Z Evaluation Board Manual”
• +2.3VDC to +5.5VDC Supply Range
• >400kHz Operation
• Bus Capacitance Buffering
• Rise Time Accelerators
• Hot-Swapping Capability
• ±6kV Class 3 HBM ESD Protection On All Pins
• ±12kV HBM ESD Protection on SDA/SCL Pins
• Enable Pin (ISL33001 and ISL33003)
• READY Logic Pin (ISL33001)
• Accelerator Disable Pin (ISL33002)
• Low Quiescent Current . . . . . . . . . . . . . 2.2mA typ
• Low Shutdown Current . . . . . . . . . . . . . . 0.5µA typ
Applications*(see page 15)
• I2C Bus Extender and Capacitance Buffering
• Server Racks for Telecom, Datacom, and Computer
Servers
• Desktop Computers
• Hot-Swap Board Insertion and Bus Isolation
Typical Operating Circuit
VCC1
+3.3V
+5.0V
Bus Accelerator Performance
100kHz I2C BUS WITH 2.7kΩ PULL-UP RESISTOR
AND 400pF BUS CAPACITANCE
VCC2
WITHOUT BUFFER
µC
SDA
SCL
SDA
ISL33003
SCL
I2C
DEVICE
A
EN
I2C
DEVICE
B
GND
VOLTAGE (1V/DIV)
BACK
PLANE
WITH BUFFER
TIME (2µs/DIV)
September 30, 2010
FN7560.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL33001, ISL33002, ISL33003
I2C Bus Buffer with Rise Time Accelerators and
Hot Swap Capability
ISL33001, ISL33002, ISL33003
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL33001IRTZ
3001
-40 to +85
8 Ld TDFN (0.65mm Pitch)
L8.3x3A
ISL33001IRT2Z
01R2
-40 to +85
8 Ld TDFN (0.5mm Pitch)
L8.3x3H
ISL33001IBZ
33001 IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL33001IUZ
33001
-40 to +85
8 Ld MSOP
M8.118
ISL33002IRTZ
3002
-40 to +85
8 Ld TDFN (0.65mm Pitch)
L8.3x3A
ISL33002IRT2Z
02R2
-40 to +85
8 Ld TDFN (0.5mm Pitch)
L8.3x3H
ISL33002IUZ
33002
-40 to +85
8 Ld MSOP
M8.118
ISL33003IRTZ
3003
-40 to +85
8 Ld TDFN (0.65mm Pitch)
L8.3x3A
ISL33003IRT2Z
03R2
-40 to +85
8 Ld TDFN (0.5mm Pitch)
L8.3x3H
ISL33003IUZ
33003
-40 to +85
8 Ld MSOP
M8.118
ISL33001MSOPEVAL1Z
ISL33001 Evaluation Board
ISL33002MSOPEVAL1Z
ISL33002 Evaluation Board
ISL33003MSOPEVAL1Z
ISL33003 Evaluation Board
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL33001, ISL33002, ISL33003. For more
information on MSL please see techbrief TB363.
Pin Configurations
ISL33001
(8 LD TDFN)
(8 LD SOIC, MSOP)
ISL33001
TOP VIEW
TOP VIEW
8
VCC1
7
SDA_OUT
SCL_IN 3
6
SDA_IN
GND 4
5
READY
EN 1
SCL_OUT 2
PAD
2
EN 1
8
VCC1
SCL_OUT 2
7
SDA_OUT
3
6
SDA_IN
SCL_IN
GND 4
5 READY
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Pin Configurations
(Continued)
ISL33002
ISL33002
(8 LD TDFN)
(8 LD MSOP)
TOP VIEW
TOP VIEW
VCC2 1
VCC2 1
8
VCC1
7
SDA_OUT
SCL_IN 3
6
SDA_IN
GND 4
5
ACC
SCL_OUT 2
PAD
8
7 SDA_OUT
SCL_OUT 2
6 SDA_IN
SCL_IN 3
GND 4
5 ACC
ISL33003
ISL33003
(8 LD TDFN)
(8 LD MSOP)
TOP VIEW
TOP VIEW
VCC2 1
8 VCC1
SCL_OUT 2
7 SDA_OUT
VCC1
VCC2 1
8
VCC1
SCL_OUT 2
7
SDA_OUT
SCL_IN 3
6
SDA_IN
GND 4
5
EN
PAD
SCL_IN 3
6 SDA_IN
GND 4
5 EN
Pin Descriptions
NAME
NOTES
PIN NUMBER
FUNCTION
8
VCC1 power supply, +2.3V to +5.5V. Decouple VCC1 to ground with a high
frequency 0.01µF to 0.1µF capacitor.
1
VCC2 power supply, +2.3V to +5.5V. Decouple VCC2 to ground with a high
frequency 0.01µF to 0.1µF capacitor. In level shifting applications, SDA_OUT
and SCL_OUT logic thresholds are referenced to VCC2 supply levels. Connect
pull-up resistors on these pins to VCC2.
4
Device Ground Pin
ISL33001
1
ISL33003
5
Buffer Enable Pin. Logic “0” disables the device. Logic “1” enables the
device. Logic threshold referenced to VCC1.
READY
ISL33001 only
5
Buffer Active ‘Ready’ Logic Output. When buffer is active, READY is high
impedance. When buffer is inactive, READY is low impedance to ground.
ACC
ISL33002 only
5
Rise Time Accelerator Enable Pin. Logic “0” disables the accelerator. Logic
“1” enables the accelerator. Logic threshold referenced to VCC1.
SDA_IN
6
Data I/O Pins
SDA_OUT
7
SCL_IN
3
SCL_OUT
2
VCC1
VCC2
ISL33002, ISL33003
GND
EN
PAD
Thermal Pad; TDFN only
3
Clock I/O Pins
Thermal pad should be connected to ground or float.
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Absolute Maximum Ratings
Thermal Information
(All voltages referenced to GND)
VCC1, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V
SDA_IN, SCL_IN . . . . . . . . . . . . . -0.3V to +(VCC1 + 0.3)V
SDA_OUT, SCL_OUT . . . . . . . . . . . -0.3V to +(VCC2 + 0.3)V
ENABLE, READY, ACC . . . . . . . . . . -0.3V to +(VCC1 + 0.3)V
Maximum Sink Current (SDA and SCL Pins). . . . . . . . . 20mA
Maximum Sink Current (READY pin) . . . . . . . . . . . . . . . 7mA
Latch-Up Tested per JESD78, Level 2, Class A . . . . . . . 85°C
ESD Ratings. . . . . . . . . . See “ESD PROTECTION” on page 5
Thermal Resistance
θJA (°C/W)
θJC (°C/W)
8 Ld TDFN Package (Notes 5, 6) . . .
47
4
(0.50mm Pitch)
8 Ld TDFN Package (Notes 5, 6) . . .
48
6
(0.65mm Pitch)
8 Ld MSOP Package (Notes 4, 7) . . .
151
50
8 Ld SOIC Package (Notes 4, 7). . . .
120
56
Maximum Storage Temperature Range . . . -65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersi.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . -40°C to +85°C
VCC1 and VCC2 Supply Voltage Range . . . . . +2.3V to +5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB7379 for details.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications
PARAMETER
SYMBOL
VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8).
Boldface limits apply over the operating temperature range,
-40°C to +85°C.
CONDITIONS
TEMP
MIN
(°C) (Note 9)
TYP
MAX
(Note 9) UNITS
POWER SUPPLIES
VCC1 Supply Range
VCC1
VCC2 Supply Range
VCC2
Supply Current from
VCC1
ICC1
Supply Current from
VCC2
ICC2
VCC1 Shut-down
Supply Current
ISHDN1
VCC2 Shut-down
Supply Current
ISHDN2
Full
2.3
-
5.5
V
ISL33002 and ISL33003
Full
2.3
-
5.5
V
VCC1 = 5.5V; ISL33001 only (Note 11)
Full
-
2.1
4.0
mA
VCC1 = VCC2 = 5.5V; ISL33002 and
ISL33003 (Note 11)
Full
-
2.0
3.0
mA
VCC2 = VCC = 5.5V; ISL33002 and
ISL33003 (Note 11)
Full
-
0.22
0.6
mA
VCC1 = 5.5V, VEN = GND; ISL33001 only
Full
-
0.5
-
µA
VCC1 = VCC2 = 5.5V, VEN = GND;
ISL33003 only
Full
-
0.05
-
µA
VCC1 = VCC2 = 5.5V, VEN = GND,
ISL33003 only
Full
-
0.06
-
µA
SDA and SCL pins floating
Full
0.8
1
1.2
V
START-UP CIRCUITRY
Precharge Circuitry
Voltage
VPRE
Enable High Threshold
Voltage
VEN_H
+25
-
0.5*VCC
0.7*VCC
V
Enable Low Threshold
Voltage
VEN_L
+25
0.3*VCC
0.5*VCC
-
V
Full
-1
0.1
1
µA
Enable Pin Input
Current
IEN
4
Enable from 0V to VCC1; ISL33001 and
ISL33003
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Electrical Specifications
PARAMETER
VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8).
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
SYMBOL
CONDITIONS
TEMP
MIN
(°C) (Note 9)
TYP
MAX
(Note 9) UNITS
Enable Delay, On-Off
tEN-HL
ISL33001 and ISL33003 (Note 10)
+25
-
10
-
ns
Enable Delay, Off-On
tEN-LH
ISL33001 and ISL33003 (Figure 1)
+25
-
86
-
µs
Bus Idle Time
tIDLE
(Figure 2, Note 12)
Full
50
83
150
µs
Ready Pin OFF State
Leakage Current
IOFF
ISL33001 only
+25
-1
0.1
1
µA
Ready Delay, On-Off
tREADY-HL
ISL33001 only (Note 10)
+25
-
10
-
ns
Ready Delay, Off-On
tREADY-LH
ISL33001 only (Note 10)
+25
-
10
-
ns
Ready Output Low
Voltage
VOL_READY VCC1 = +2.5V, IPULLUP = 3mA;
ISL33001 only
Full
-
-
0.4
V
VCC1 = 2.7V, VCC2 = 2.7V;
(ACC = 0.7*VCC1 for ISL33002 only)
(Figure 6)
+25
-
5
-
mA
-
RISE-TIME ACCELERATORS
Transient Accelerator
Current
ITRAN_ACC
Accelerator Enable
Threshold
VACC_EN
ISL33002 only
+25
Accelerator Disable
Threshold
VACC_DIS
ISL33002 only
+25
IACC
ISL33002 only
+25
-1
ISL33002 only (Note 10)
+25
SDA, SCL I/O Pins
Human Body Model, SDA and SCL pins to
ground only (JESD22-A114)
All Pins
Accelerator Pin Input
Current
Accelerator Delay,
On-Off
tPDOFF
0.5*VCC1 0.7*VCC1
0.3*VCC1 0.5*VCC1
V
-
V
0.1
1
µA
-
10
-
ns
+25
-
±12
-
kV
Machine Model (JESD22-A115)
+25
-
±400
-
V
Class 3 HBM ESD (JESD22-A114)
+25
±6
-
kV
ESD PROTECTION
INPUT-OUTPUT CONNECTIONS
Input Low Threshold
VIL
VCC1 = VCC2, 10kΩ to VCC1 on SDA and
SCL pins
+25
-
0.3*VCC1
-
V
Input-Output Offset
Voltage
VOS
VCC1 = 3.3V, 10kΩ to VCC1 on SDA and
SCL pins, VINPUT = 0.2V; VCC2 = 3.3V,
ISL33002 and ISL33003 (Figure 3)
Full
0
50
150
mV
Output Low Voltage
VOL
VCC1 = 2.7V, VINPUT = 0V, ISINK = 3mA
on SDA/SCL pins; VCC2 = 2.7V,
ISL33002 and ISL33003 (Figure 4)
Full
-
-
0.4
V
Buffer SDA and SCL
Pins Input
Capacitance
CIN
(Figure 23)
+25
-
10
-
pF
SDA and SCL pins = VCC1 = 5.5V;
VCC2 = 5.5V, ISL33002 and ISL33003
Full
-5
0.1
5
µA
Input Leakage
Current
ILEAK
5
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Electrical Specifications
PARAMETER
VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8).
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
SYMBOL
CONDITIONS
TEMP
MIN
(°C) (Note 9)
TYP
MAX
(Note 9) UNITS
TIMING CHARACTERISTICS
SCL/SDA Propagation
Delay High to Low
tPHL
CLOAD = 100pF, 2.7kΩ to VCC1 on SDA
and SCL pins, VCC1 = 3.3V; VCC2 = 3.3V,
ISL33002 and ISL33003 (Figure 5)
+25
0
27
100
ns
SCL/SDA Propagation
Delay Low to High
tPLH
CLOAD = 100pF, 2.7kΩ to VCC1 on SDA
and SCL pins, VCC1 = 3.3V; VCC2 = 3.3V,
ISL33002 and ISL33003 (Figure 5)
+25
0
2
26
ns
NOTES:
8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
10. Typical value determined by design simulations. Parameter not tested.
11. Buffer is in the connected state.
12. ISL33002 and ISL33003 limits established by characterization. Not production tested.
6
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Test Circuits and Waveforms
- VSDA_IN = VSDA_OUT = VSCL_OUT = VEN = VCC
- SDA and SCL pins connected to VCC
- Enable Delay Time Measured on ISL33001 only
- ISL33003 performance inferred from ISL33001
- EN Logic High for t > Enable Delay, tEN_LH
prior to SCL_IN transition
- Bus Idle Time Measured on ISL33001 only
- ISL33002 and ISL33003 performance
inferred from ISL33001
VCC
VCC
0.5 * VCC
VEN
0V
0.5VCC
VSCL_IN
0V
VCC
VCC
0.5VCC
0.5 * VCC
VREADY
VREADY
0V
0V
tEN-LH
tIDLE
FIGURE 1. ENABLE DELAY TIME
FIGURE 2. BUS IDLE TIME
+3.3V
10kΩ
VCC1
SCL_OUT
10kΩ
10kΩ
SDA_OUT
SCL_IN OR
SDA_IN
0.2V
10kΩ
SDA_IN
SCL_IN
GND
VIN
0.2V
SCL_OUT OR
SDA_OUT
VIN
0.2V
VO
VOS = VO - 0.2V
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. INPUT TO OUTPUT OFFSET VOLTAGE
+2.7V
900Ω
VCC1
SCL_OUT
900Ω
900Ω
VCC1
SDA_OUT
900Ω
SDA_IN
SCL_IN
SCL_OUT
VOL
VCC1
GND
0V
0V
SDA_OUT
FIGURE 4A. TEST CIRCUIT
VOL
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. OUTPUT LOW VOLTAGE
7
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Test Circuits and Waveforms (Continued)
+3.3V
SCL_IN OR
SDA_IN
2.7kΩ
2.7kΩ
VCC1
SCL_OUT
2.7kΩ
SDA_OUT
2.7kΩ
SCL_OUT OR
SDA_OUT
SDA_IN
SCL_IN
GND
VIN
100pF
100pF
100pF
VIN
100pF
*tPLH
*tPHL
*Propagation delay measured between 50% of VCC1
FIGURE 5A. TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. PROPAGATION DELAY
IACC = CΔV/Δt
*V
X
VCC1
2.7kΩ
*V
X
VCC1
2.7kΩ 2.7kΩ
100kΩ
VCC1
SCL_OUT
10kΩ
SDA_OUT
SDA_IN
SCL_IN
GND
2nF
10kΩ
SCL_OUT
10kΩ
VCC1
10kΩ
SDA_OUT
SDA_IN
SCL_IN
GND
*V < V
X
CC1
(See Figure 20)
FIGURE 6. ACCELERATOR CURRENT TEST CIRCUIT
8
FIGURE 7. ACCELERATOR PULSE WIDTH TEST CIRCUIT
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
SDA_IN
SDA_OUT
U1
M2
M1
U2
RISE TIME
ACCELERATOR
READY
ISL33001 only
M5
LOGIC CONTROL
START-UP CIRCUITRY
VCC1
VCC2
ISL33002 and ISL33003
EN
ISL33001 and ISL33003
PRECHARGE
CIRCUIT
SCL_IN
ACC
ISL33002 only
SCL_OUT
U3
M4
M3
U4
FIGURE 8. CIRCUIT BLOCK DIAGRAM
Application Information
The ISL33001, ISL33002, ISL33003 ICs are 2-Wire
Bidirectional Bus Buffers designed to drive heavy
capacitive loads in open-drain/open-collector systems.
The ISL33001, ISL33002, ISL33003 incorporate rise time
accelerator circuitry that improves the rise time for
systems that use a passive pull-up resistor for logic
HIGH. These devices also feature hot swapping circuitry
for applications that require hot insertion of boards into a
host system (i.e., servers racks and I/O card modules).
The ISL33001 features a logic output flag (READY) that
signals the status of the buffer and an EN pin to enable or
disable the buffer. The ISL33002 features two separate
supply pins for voltage level shifting on the I/O pins and
a logic input to disable the rise time accelerator circuitry.
The ISL33003 features an EN pin and the level shifting
functionality.
I2C and SMBUS Compatibility
The ISL33001, ISL33002, ISL33003 ICs are I2C and
SMBUS compatible devices, designed to work in
open-drain/open-collector bus environments. The ICs
support both clock stretching and bus arbitration on the
SDA and SCL pins. They are designed to operate from DC
to more than 400kHz, supporting Fast Mode data rates of
the I2C specification.
In addition, the buffer rise time accelerators are designed
to increase the capacitive drive capability of the bus.
9
With careful choosing of components, driving a bus with
the I2C specified maximum bus capacitance of 400pF at
400kHz data rate is possible.
Start-Up Sequencing and Hot Swap Circuitry
The ISL33001, ISL33002, ISL33003 buffers contain
undervoltage lock out (UVLO) circuitry that prevents
operation of the buffer until the IC receives the proper
supply voltage. For VCC1 and VCC2, this voltage is
approximately 1.8V on the rising edge of the supply
voltage. Externally driven signals at the SDA/SCL pins
are ignored until the device supply voltage is above 1.8V.
This prevents communication errors on the bus until the
device is properly powered up. The UVLO circuitry is also
triggered on the falling edge when the supply voltage
drops below 1.7V.
Once the IC comes out of the UVLO state, the buffer will
remain disconnected until it detects a valid connection
state. A valid connection state is either a BUS IDLE
condition (see Figure 2) or a STOP BIT condition (a rising
edge on SDA_IN when SCL_IN is high) along with the
SCL_OUT and SDA_OUT pins being logic high.
Note - For the ISL33001 and ISL33003 with EN pins,
after coming out of UVLO, there will be an additional
delay from the enable circuitry if the EN pin voltage is not
rising at the same time as the supply pins (see Figure 1)
before a valid connection state can be established.
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Coming out of UVLO but prior to a valid connection state,
the SDA and SCL pins are pre-charged to 1V to allow hot
insertion. Because the bus at any time can be between
0V and VCC, pre-charging the I/O pins to 1V reduces the
maximum differential voltage from the buffer I/O pin and
the active bus. The pre-charge circuitry reduces system
disturbance when the IC is hot plugged into a live back
plane that may have the bus communicating with other
devices.
Note - For ISL33001 and ISL33003 with EN pins, the
pre-charge circuitry is active only after coming out of
UVLO and having the device enabled.
Connection Circuitry
Once a valid connection condition is met, the buffer is
active and the input stage of the SDA/SCL pins is
controlled by external drivers. The output of the buffer
will follow the input of the buffer. The directionality of the
IN/OUT pins are not exclusive (bi-directional operation)
and functionally behave identical to each other. Being a
two channel buffer, the SDA and SCL pins also behave
identically. In addition, the SDA and SCL portions of the
buffer are independent from each other. The SDA pins
can be driven in one direction while the SCL pins can be
driven opposite.
Refer to Figure 8 for the operation of the bi-directional
buffer. When the input stage of the buffer on one side is
driven low by an external device, the output of the buffer
drives an open-drain transistor to pull the ‘output’ pin
low. The ‘output’ pin will continue to be held low by the
transistor until the external driver on the ‘input’ releases
the bus.
To prevent the buffer from entering a latched condition
where both internal transistors are actively pulling the
I/O pins low, the buffer is designed to be active in only
one direction. The buffer logic circuitry senses which
input stage is being externally driven low and sets that
buffer to be the active one. For example, referring to
Figure 8, if SDA_OUT is externally driven low, buffer U2
will be active and buffer U1 is inactive. M1 is turned on to
drive SDA_IN low, effectively buffering the signal from
SDA_OUT to SDA_IN. The low signal at the input of U1
will not turn M2 on because U1 remains inactive,
preventing a latch condition.
Buffer Output Low and Offset Voltage
By design, when a logic input low voltage is forced on the
input of the buffer, the output of the buffer will have an
input to output offset voltage. The output voltage of the
buffer is determined by Equation 1:
V OUT = V IN + V OS + [ V CC ⁄ R PULL-UP × R ON ]
(EQ. 1)
Where VOS is the buffer internal offset voltage, RPull-Up is
the pull up resistance on the SDA/SCL pin to VCC and
RON is the ON resistance of the buffer’s internal NMOS
pull-down device. The last term of the equation is the
additional voltage drop developed by sink current and
the internal resistance of the transistor. The VOS of the
buffer can be determined by Figures 17, 18 and is
10
typically 40mV. Reducing the pull-up resistor values
increases the sink current and increases the output
voltage of the buffer for a given input low voltage
(Figures 15, 16, 17, 18).
Rise Time Accelerators
The ISL33001, ISL33002, ISL33003 buffer rise time
accelerators on the SDA/SCL pins improve the transient
performance of the system. Heavy load capacitance or
weak pull-up resistors on an Open-Drain bus cause the
rise time to be excessively long, which leads to data
errors or reduced data rate performance. The rise time
accelerators are only active on the low to high transitions
and provide an active constant current source to slew the
voltage on the pin quickly (Figure 19).
The rise time accelerators are triggered immediately
after the buffer release threshold (approximately 30% of
VCC) on both sides of the buffer is crossed. Once
triggered, the accelerators are active for a defined pulse
width (Figure 20) with the current source turning off as it
approaches the supply voltage.
Enable Pin (ISL33001 and ISL33003)
When driven high, the enable pin puts the buffer into its
normal operating state. After power-up, EN high will
activate the bus pre-charge circuitry and wait for a valid
connection state to enable the buffer and the accelerator
circuitry.
Driving the EN pin low disables the accelerators, disables
the buffer so that signals on one side of the buffer will be
isolated from the other side, disables the pre-charge
circuit and places the device in a low power shutdown
state.
READY Logic Pin (ISL33001 Only)
The READY pin is a digital output flag for signaling the
status of the buffer. The pin is the drain of an Open-Drain
NMOS. Connect a resistor from the READY pin to VCC1 to
provide the high pull-up. The recommended value is
10kΩ.
When the buffer is disabled by having the EN pin low or if
the start-up sequencing is not complete, the READY pin
will be pulled low by the NMOS. When the buffer has the
EN pin high and a valid connection state is made at the
SDA/SCL pins, the READY pin will be pulled high by the
pull-up resistor. The READY pin is capable of sinking 3mA
when pulled low while maintaining a voltage of less than
0.4V.
ACC Accelerator Pin (ISL33002 Only)
The ACC logic pin controls the rise time accelerator
circuitry of the buffer. When ACC is driven high, the
accelerators are enabled and will be triggered when
crossing the buffer release threshold. When ACC is driven
low, the accelerators are disabled.
For lightly loaded buses, having the accelerators active
may cause ringing or noise on the rising edge transition.
Disabling the accelerators will have the buffers continue
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
to perform level shifting with the VCC1 and VCC2 supplies
and provide capacitance buffering.
Propagation Delays
On a low to high transition, the rising edge signal is
determined by the bus pull-up resistor, load capacitance,
and the accelerator current from the ISL33001,
ISL33002, ISL33003 buffer. Prior to the accelerators
becoming active, the buffer is connected and the output
voltage will track the input of the buffer. When the
accelerators activate the buffer connection is released
and the signal on each side of the buffer rises
independently. The accelerator current on both sides of
the buffer will be equal. If the pull-up resistance on both
sides of the buffer are also equal, then differences in the
rise time will be proportional to the difference in
capacitive loading on the two sides.
Because the signals on each side of the buffer rise
independently, the propagation delay can be positive or
negative. If the input side rises slowly relative to the
output (i.e., heavy capacitive loading on the input and
light load on the output) then the propagation delay tPLH
is negative. If the output side rises slowly relative to the
input, tPLH is positive.
For high to low transitions, there is a finite propagation
delay through the buffer from the time an external low
on the input drives the NMOS output low. This
propagation delay will always be positive because the
buffer connect threshold on the falling edge is below the
measurement points of the delay. In addition to the
Typical Performance Curves
propagation delay of the buffer, there will be additional
delay from the different capacitive loading of the buffer.
Figures 21 and 22 show how the propagation delay from
high to low, tPHL, is affected by VCC and capacitive
loading.
The buffer’s propagation delay times for rising and falling
edge signals must be taken into consideration for the
timing requirements of the system. SETUP and HOLD
times may need to be adjusted to take into account
excessively long propagation delay times caused by
heavy bus capacitances.
Pull-Up Resistor Selection
While the ISL33001, ISL33002, ISL33003 2-Channel
buffers are designed to improve the rise time of the bus
in passive pull-up systems, proper selection of the
pull-up resistor is critical for system operation when a
buffer is used. For a bus that is operating normally
without active rise time circuitry, using the ISL33001,
ISL33002, ISL33003 buffer will allow larger pull-up
resistor values to reduce sink currents when the bus is
driving low. However, choose a pull-up resistor value of
no larger than 20kΩ regardless of the bus capacitance
seen on the SDA/SCL lines. The Bus Idle or Stop Bit
condition requires valid logic high voltages to give a valid
connection state. Pull-up resistor values 20kΩ or smaller
are recommended to overcome the typical 150kΩ
impedance of the pre-charge circuitry, delivering valid
high levels.
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25°C; Unless Otherwise
Specified.
2.4
600
2.3
T = -40°C
550
2.2
1.9
1.8
1.7
1.6
T = +85°C
400
350
300
250
1.5
200
1.4
150
1.3
1.2
2.0
T = +25°C
450
T = +85°C
ICC1 (nA)
ICC1 (mA)
2.0
500
T = +25°C
2.1
2.5
3.0
3.5
4.0
4.5
VCC1 (V)
5.0
FIGURE 9. ICC1 ENABLED CURRENT vs VCC1
(ISL33001)
11
5.5
6.0
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC1 (V)
FIGURE 10. ICC1 DISABLED CURRENT vs VCC1
(ISL33001)
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Typical Performance Curves
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25°C; Unless Otherwise
Specified. (Continued)
2.4
60
VCC2 = 5.5V
2.3
VCC2 = 5.5V
2.2
2.1
T = +25°C
1.9
ICC1 (nA)
ICC1 (mA)
2.0
50
T = -40°C
T = +85°C
1.8
1.7
1.6
40
T = +25°C
30
T = +85°C
20
1.5
1.4
10
1.3
1.2
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
2.0
6.0
2.5
3.0
3.5
VCC1 (V)
FIGURE 11. ICC1 ENABLED CURRENT vs VCC1
(ISL33002 AND ISL33003)
0.24
5.0
5.5
6.0
60
VCC1 = 5.5V
VCC1 = 5.5V
50
T = -40°C
0.20
T = +85°C
ICC2 (nA)
ICC2 (mA)
4.5
FIGURE 12. ICC1 DISABLED CURRENT vs VCC1
(ISL33003)
T = +25°C
0.22
4.0
VCC1 (V)
0.18
0.16
40
30
T = +25°C
T = +85°C
20
0.14
10
0.12
0.10
2.0
2.5
3.0
3.5
4.0
4.5
VCC2 (V)
5.0
5.5
0
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC2 (V)
FIGURE 14. ICC2 DISABLED CURRENT vs VCC2
(ISL33003)
FIGURE 13. ICC2 ENABLED CURRENT vs VCC2
(ISL33002 AND ISL33003)
120
120
T = -40°C
VCC = 2.3V
100
100
80
80
T = +25°C
60
VOL (mV)
VOL (mV)
T = +85°C
VCC = 2.7V
60
40
40
VCC = 4.5V
20
VCC = 3.3V
VIN = 0V
20
VIN = 0V
0
0
1
2
3
4
5
6
7
8
9
10
11
IOL (mA)
FIGURE 15. SDA/SCL OUTPUT LOW VOLTAGE vs SINK
CURRENT vs VCC
12
0
0
1
2
3
4
5
7
6
IOL (mA)
8
9
10
11
FIGURE 16. SDA/SCL OUTPUT LOW VOLTAGE vs SINK
CURRENT vs TEMPERATURE
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Typical Performance Curves
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25°C; Unless Otherwise
Specified. (Continued)
100
100
VOS (mV)
90
90
VCC = 5.5V
80
80
70
70
50
VCC = 3.3V
VCC = 2.3V
40
VOS (mV)
60
60
50
40
30
20
20
VCC = 3.3V
10
10
VIN = 0.2V
0
0
1
2
3
4
5
6
7
IOL (mA)
8
9
10
9
T = +85°C
7
6
5
T = +25°C
4
3
2.0
2.5
3.0
3.5
4.0
4.5
1
2
3
4
5.0
5.5
6.0
800
FIGURE 19. ACCELERATOR PULL-UP CURRENT vs VCC
T = +25°C
30
20
T = -40°C
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC (V)
FIGURE 21. PROPAGATION DELAY H-L vs VCC
13
8
9
10
11
700
T = +25°C
600
T = -40°C
T = +85°C
500
400
300
200
2.0
2.5
3.0
3.5
6.0
4.0
4.5
VCC (V)
5.0
5.5
6.0
50
T = +85°C
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
40
7
FIGURE 20. ACCELERATOR PULSE WIDTH vs VCC
RPULL-UP = 2.7kΩ
CIN = 10pF
COUT = 100pF
T = +85°C
6
(See Figure 7)
VCC (V)
50
5
FIGURE 18. INPUT TO OUTPUT OFFSET VOLTAGE vs
SINK CURRENT vs TEMPERATURE
ACCELERATOR PULSE WIDTH (ns)
T = -40°C
10
8
0
IOL (mA)
12
11
0
11
FIGURE 17. INPUT TO OUTPUT OFFSET VOLTAGE vs
SINK CURRENT vs VCC
ACCELERATOR CURRENT (mA)
T = +85°C
30
VIN = 0.2V
T = -40°C
T = +25°C
40
30
T = +25°C
20
T = -40°C
VCC = 3.3V
RPULL-UP = 10kΩ
CIN = 50pF
10
0
0
100 200 300 400 500 600 700 800 900
COUT (pF)
FIGURE 22. PROPAGATION DELAY H-L vs COUT
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Typical Performance Curves
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25°C; Unless Otherwise
Specified. (Continued)
12
CAPACITANCE (pF)
11
VCC = 2.3V
VCC = 3.3V
VCC = 5.5V
10
50
10
9
8
7
6
-30
-10
30
70
90
TEMPERATURE (°C)
FIGURE 23. SDA/SCL PIN CAPACITANCE vs TEMPERATURE vs VCC
Die Characteristics
SUBSTRATE AND TDFN THERMAL PAD
POTENTIAL (POWERED UP):
GND
PROCESS:
0.25µm CMOS
14
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
9/13/10
FN7560.2
Added SOIC package information to datasheet for ISL33001.
4/30/10
FN7560.1
Changed typical value of “Supply Current from VCC1” on page 4 for ISL33001 only from 2.2mA
to 2.1mA.
Changed typical value of “Input-Output Offset Voltage” on page 5 from 100mV to 50mV.
3/18/10
FN7560.0
Initial Release.
Products
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handheld products, and notebooks. Intersil's product families address power management and analog signal
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL33001, ISL33002, ISL33003
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
15
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Package Outline Drawing
L8.3x3H
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN)
Rev 0, 2/08
2.38
1.50 REF
3.00
A
PIN #1 INDEX AREA
6 X 0.50
6
PIN 1
INDEX AREA
6
B
1
8 X 0.40
4
2.20
3.00
(4X)
1.64
0.15
5
8
0.10 M C A B
TOP VIEW
8 X 0.25
BOTTOM VIEW
( 2.38 )
SEE DETAIL "X"
0 .80 MAX
0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
2 . 80
( 2 .20 )
SIDE VIEW
( 1.64 )
C
0.2 REF
8X 0.60
0 . 00 MIN.
0 . 05 MAX.
( 8X 0.25 )
DETAIL “X”
( 6X 0 . 5 )
NOTES:
TYPICAL RECOMMENDED LAND PATTERN
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width dimension applies to the metallized terminal and is
measured between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
16
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
3.00
( 1.95)
A
B
3.00
( 8X 0.50)
6
PIN 1
INDEX AREA
(4X)
(1.50)
( 2.90 )
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
2X 1.950
PIN #1
INDEX AREA
0.10 C
0.75 ±0.05
6X 0.65
C
0.08 C
1
SIDE VIEW
6
1.50 ±0.10
8
C
8X 0.30 ±0.05
8X 0.30 ± 0.10
0 . 2 REF
5
4
0.10 M C A B
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
either a mold or mark feature.
17
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.036
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
18
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN7560.2
September 30, 2010
ISL33001, ISL33002, ISL33003
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
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19
FN7560.2
September 30, 2010