High Speed, Dual Channel, 6A, 4.5 to 16VOUT, Power MOSFET Driver ISL89160, ISL89161, ISL89162 Features The ISL89160, ISL89162, and ISL89162 are high-speed, 6A, dual channel MOSFET drivers. These parts are identical to the ISL89163, ISL89164, ISL89165 drivers but without the enable inputs for each channel. • Dual output, 6A peak current (sink and source) Two input logic thresholds are available: 3.3V (CMOS and TTL compatible) and 5.0V (CMOS). • Typical ON-resistance <1Ω • Specified Miller plateau drive currents • Very low thermal impedance (θJC = 3°C/W) • 3.3V and 5V logic inputs with hysteresis are VDD tolerant Precision thresholds on all logic inputs allow the use of external RC circuits to generate accurate and stable time delays on both inputs, INA and INB. This capability is very useful for dead time control. • Precision threshold inputs for time delays with external RC components At high switching frequencies, these MOSFET drivers use very little bias current. Separate, non-overlapping drive circuits are used to drive each CMOS output FET to prevent shoot-thru currents in the output stage. • Pb-Free (RoHs Compliant) The undervoltage lock-out (UV) insures that driver outputs remain off (low) until VDD is sufficiently high for correct logic control. This prevents unexpected behavior when VDD is being turned on or turned off. • ~ 20ns rise and fall time driving a 10nF load. • Low operating bias currents Applications • Synchronous Rectifier (SR) Driver • Switch mode power supplies • Motor Drives, Class D amplifiers, UPS, Inverters • Pulse Transformer Driver • Clock/Line Driver 3.5 VDD INA GND INB 8 1 7 2 3 EPAD OUTA 6 5 4 NC OUTB 4.7µF OPTION B THRESHOLDS (5V) NC 3.0 POSITIVE THRESHOLD 2.5 2.0 1.5 NEGATIVE THRESHOLD 1.0 0.5 0.0 -40 -25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) FIGURE 1. TYPICAL APPLICATION January 20, 2011 FN7719.1 1 FIGURE 2. TEMPERATURE STABLE LOGIC THRESHOLDS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL89160, ISL89161, ISL89162 Block Diagram VDD For clarity, only one channel is shown Separate FET drives, with non-overlapping outputs, prevent shoot-thru currents in the output CMOS FETs resulting with very low high frequency operating currents. For options A and B, the UV comparator holds off the outputs until VDD ~> 3.3VDC. ISL89160 INx OUTx 10k EPAD ISL89161, ISL89162 GND For proper thermal and electrical performance, the EPAD must be connected to the PCB ground plane. Pin Configurations ISL89161FR, ISL89161FB (8 LD TDFN, EPSOIC) TOP VIEW ISL89160FR, ISL89160FB (8 LD TDFN, EPSOIC) TOP VIEW Pin Descriptions PIN NUMBER SYMBOL 1, 8 NC NC 1 8 NC INA 2 7 OUTA /INA 2 7 OUTA 2 6 VDD GND 3 6 VDD 3 5 OUTB /INB 4 5 OUTB 4 GND 3 INB 4 8 NC NC 1 ISL89162FR, ISL89162FB (8 LD TDFN, EPSOIC) TOP VIEW No Connect. This pin may be left open or connected to 0V or VDD INA or /INA Channel A input, 0V to VDD GND Power Ground, 0V INB or /INB Channel B enable, 0V to VDD 5 OUTB Channel B output 6 VDD Power input, 4.5V to 16V 7 OUTA Channel A output, 0V to VDD EPAD Power Ground, 0V 8 NC NC 1 /INA 2 7 OUTA GND 3 6 VDD INB DESCRIPTION 5 OUTB 4 2 FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP RANGE (°C) INPUT CONFIGURATION INPUT LOGIC PACKAGE (Pb-Free) PKG. DWG. # ISL89160FRTAZ 160A -40 to +125 non-inverting 8 Ld 3x3 TDFN L8.3x3I ISL89161FRTAZ 161A -40 to +125 inverting 8 Ld 3x3 TDFN L8.3x3I ISL89162FRTAZ 162A -40 to +125 inverting + non-inverting 8 Ld 3x3 TDFN L8.3x3I ISL89160FBEAZ 89160 FBEAZ -40 to +125 non-inverting 8 Ld EPSOIC M8.15D ISL89161FBEAZ 89161 FBEAZ -40 to +125 inverting 8 Ld EPSOIC M8.15D ISL89162FBEAZ 89162 FBEAZ -40 to +125 inverting + non-inverting 8 Ld EPSOIC M8.15D ISL89160FRTBZ 160B -40 to +125 non-inverting 8 Ld 3x3 TDFN L8.3x3I 3.3VDC ISL89161FRTBZ 161B -40 to +125 inverting 8 Ld 3x3 TDFN L8.3x3I ISL89162FRTBZ 162B -40 to +125 inverting + non-inverting 8 Ld 3x3 TDFN L8.3x3I ISL89160FBEBZ 89160 FBEBZ -40 to +125 non-inverting 8 Ld EPSOIC M8.15D ISL89161FBEBZ 89161 FBEBZ -40 to +125 inverting 8 Ld EPSOIC M8.15D ISL89162FBEBZ 89162 FBEBZ -40 to +125 inverting + non-inverting 8 Ld EPSOIC M8.15D 5.0VDC NOTES: 1. Add “-T*”, suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL89160, ISL89161, ISL89162. For more information on MSL, please see Technical Brief TB363. 3 FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD Relative to GND . . . . . . . . . . . . . . . . . . . . -0.3V to 18V Logic Inputs (INA, INB) . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD + 0.3V Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD + 0.3V Average Output Current (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA ESD Ratings Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . . . 2000V Machine Model Class B (Tested per JESD22-A115-A) . . . . . . . . . . . . 200V Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld TDFN Package (Notes 4, 5). . . . . . . . . 44 3 8 Ld EPSOIC Package (Notes 4, 5) . . . . . . . 42 3 Max Power Dissipation at +25°C in Free Air . . . . . . . . . . . . . . . . . . . . . 2.27W Max Power Dissipation at +25°C with Copper Plane . . . . . . . . . . . . . 33.3W Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Latch-Up (Tested per JESD-78B; Class 2, Level A) Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500 mA Maximum Recommended Operating Conditions Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Supply Voltage, VDD Relative to GND. . . . . . . . . . . . . . . . . . . . . .4.5V to 16V Logic Inputs (INA, INB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output currents of this driver are self limiting by transconductance or rDS(ON) and do not required any external components to minimize the peaks. If the output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified absolute maximum. DC Electrical Specifications VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. TJ = +25°C PARAMETERS SYMBOL TJ = -40°C to +125°C MIN TYP MAX MIN (Note 7) MAX (Note 7) UNITS - - - 4.5 16 V INx = GND - 5 - - - mA INA = INB = 1MHz, square wave - 25 - - mA - 3.3 - - - - ~25 - - - mV - - - GND VDD V Option A, nominally 37% x 3.3V - 1.22 - 1.12 1.32 V Option B, nominally 37% x 5.0V - 1.85 - 1.70 2.00 V Option A, nominally 63% x 3.3V - 2.08 - 1.98 2.18 V Option B, nominally 63% x 5.0V - 3.15 - 3.00 3.30 V - 2 - - - pF TEST CONDITIONS POWER SUPPLY Voltage Range VDD VDD Quiescent Current IDD UNDERVOLTAGE VDD Undervoltage Lock-out (Note 9) VUV INA = INB = True (Note 10) Hysteresis V INPUTs (Note 11) Input Range for INA, INB VIN Logic 0 Threshold for INA, INB (Note 9) VIL Logic 1 Threshold for INA, INB (Note 9) VIH Input Capacitance of INA, INB (Note 8) CIN 4 FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 DC Electrical Specifications VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued) TJ = +25°C PARAMETERS SYMBOL Input Bias Current for INA, INB IIN TEST CONDITIONS GND<VIN<VDD TJ = -40°C to +125°C MIN TYP MAX MIN (Note 7) MAX (Note 7) UNITS - - - -10 +10 µA OUTPUTS High Level Output Voltage VOHA VOHB - - - VDD - 0.1 VDD V Low Level Output Voltage VOLA VOLB - - - GND GND + 0.1 V Peak Output Source Current IO VO (initial) = 0V, CLOAD = 10nF - -6 - - - A Peak Output Sink Current IO VO (initial) =12V, CLOAD = 10nF - +6 - - - A NOTES: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic capacitance. 9. A 200µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. 10. The true state of a specific part number is defined by the input logic symbol. 11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted inputs is less than the logic 0 threshold voltage. AC Electrical Specifications VDD = 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. PARAMETERS SYMBOL TEST CONDITIONS /NOTES TJ = -40°C to +125°C TJ = +25°C MIN TYP MAX MIN MAX UNITS Output Rise Time (see Figure 4) tR CLOAD = 10nF, 10% to 90% - 20 - - 40 ns Output Fall Time (see Figure 4) tF CLOAD = 10nF, 90% to 10% - 20 - - 40 ns Output Rising Edge Propagation Delay for Non-Inverting Inputs (see Figure 3) tRDLYn No load - 25 - - 50 ns Output Rising Edge Propagation Delay with Inverting Inputs (see Figure 3) tRDLYi No load - 25 - - 50 ns Output Falling Edge Propagation Delay with Non-Inverting Inputs (see Figure 3) tFDLYn No load - 25 - - 50 ns Output Falling Edge Propagation Delay with Inverting Inputs (see Figure 3) tFDLYi No load - 25 - - 50 ns Rising Propagation Matching (see Figure 3) tRM - <1ns - - - ns Falling Propagation Matching (see Figure 3) tFM - <1ns - - - ns Miller Plateau Sink Current (See Test Circuit Figure 5) -IMP VDD = 10V, VMILLER = 5V - 6 - - - A -IMP VDD = 10V, VMILLER = 3V - 4.7 - - - A -IMP VDD = 10V, VMILLER= 2V - 3.7 - - - A 5 FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 AC Electrical Specifications VDD = 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued) PARAMETERS SYMBOL Miller Plateau Source Current (See Test Circuit Figure 6) TEST CONDITIONS /NOTES TJ = -40°C to +125°C TJ = +25°C MIN TYP MAX MIN MAX UNITS IMP VDD = 10V, VMILLER = 5V - 5.2 - - - A IMP VDD = 10V, VMILLER = 3V - 5.8 - - - A IMP VDD = 10V, VMILLER = 2V - 6.9 - - - A Test Waveforms and Circuits 3.3V* INA, INB 50% 50% tRDLY tFDLY 0V 90% /OUTA OUTA tRDLY tFDLY OUTA OR OUTB /OUTB 10% tR OUTB tRM tF tFM * logic levels: A option = 3.3V, B option = 5.0V FIGURE 3. PROP DELAYS AND MATCHING ISL8916x FIGURE 4. RISE/FALL TIMES 10V 10V ISL8916x 0.1µF 10k 0.1µF 10k VMILLER VMILLER 10µF 200ns 10µF 200ns 10nF +ISENSE 10nF 0.1 0.1 -ISENSE FIGURE 5. MILLER PLATEAU SINK CURRENT TEST CIRCUIT 6 +ISENSE -ISENSE FIGURE 6. MILLER PLATEAU SOURCE CURRENT TEST CIRCUIT FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 Test Waveforms and Circuits (Continued) 10V Current through 0.1Ω Resistor IM P 0A V M IL LER V O UT V OUT V M ILLER Current through 0.1 Ω Resistor -I M P 0V 0 200 ns 20 0n s FIGURE 7. MILLER PLATEAU SINK CURRENT FIGURE 8. MILLER PLATEAU SOURCE CURRENT Typical Performance Curves 3.5 35 +125°C 30 1MHz BIAS CURRENT (mA) STATIC BIAS CURRENT (mA) +125°C 3.0 +25°C -40°C 2.5 +25°C 25 -40°C 20 15 10 2.0 4 8 12 5 4 16 8 12 VDD 16 VDD FIGURE 10. IDD vs VDD (1 MHz) FIGURE 9. IDD vs VDD (STATIC) 50 1.1 16V VOUT LOW 1.0 40 NO LOAD 0.9 rDS(ON) (Ω) IDD (mA) 10V 30 12V 20 5V 0.7 10 0 VOUT HIGH 0.8 0.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 FREQUENCY (MHz) FIGURE 11. IDD vs FREQUENCY (+25°C) 7 1.8 2.0 0.5 -45 -20 5 30 55 80 105 130 TEMPERATURE (°C) FIGURE 12. rDS(ON) vs TEMPERATURE FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 Typical Performance Curves (Continued) 25 30 PROPAGATION DELAY (ns) RISE/FALL TIME (ns) FALL TIME, CLOAD = 10nF 20 RISE TIME, CLOAD = 10nF 15 -45 -20 5 30 55 80 TEMPERATURE (°C) 105 OUTPUT FALLING PROP DELAY 25 OUTPUT RISING PROP DELAY 20 15 5 130 7 9 11 VDD 13 15 FIGURE 14. PROPAGATION DELAY vs VDD FIGURE 13. OUTPUT RISE/FALL TIME Functional Description D Overview INx The ISL89160, ISL89161, ISL89162 drivers incorporate several features including precision input logic thresholds, undervoltage lock-out, and fast rising high output drive currents. The precision input thresholds facilitate the use of an external RC network to delay the rising or falling propagation of the driver output. This is a useful feature to create dead times for bridge applications to prevent shoot through. To prevent unexpected glitches on the output of the ISL89160, ISL89161, ISL89162 during power-on or power-off when VDD is very low, the Undervoltage (UV) lock-out prevents the outputs of the ISL89160, ISL89161, ISL89162 driver from turning on. The UV lock-out forces the driver outputs to be low when VDD < ~3.2 VDC regardless of the input logic level. The fast rising (or falling) output drive currents of the ISL89160, ISL89161, ISL89162 minimize the turn-on (off) delays due to the input capacitance of the driven FET. The switching transition period at the Miller plateau is also minimized by high drive currents even at these lower output voltages. (See the specified Miller plateau currents in the AC Electrical Specifications on page 5). Application Information Precision Thresholds for Time Delays For input logic voltage option A, the nominal input negative transition threshold is 1.22V and the positive transition threshold is 2.08V (37% and 63% of 3.3V) Likewise, for input logic option B, the nominal input negative transition threshold is 1.85V and the positive transition threshold is 3.15V (37% and 63% of 4.0V). In Figure 15, Rdel and Cdel delay the rising edge of the input signal. For the falling edge of the input signal, the diode shorts out the resistor resulting in a minimal falling edge delay. If the diode polarity is reversed, the falling edge is delayed and the rising delay is minimal. 8 Rdel OUTx cdel FIGURE 15. DELAY USING RCD NETWORK The 37% and 63% thresholds were chosen to simplify the calculations for the desired time delays. When using an RC circuit to generate a time delay, the delay is simply T (secs) = R (ohms) x C (farads). Please note that this equation only applies if the input logic voltage amplitude is 3.3V. If the logic high amplitude is higher than 3.3V, the equations in Equation 1 can be used for more precise delay calculations. V H High level of the logic signal into the RC = 5V V THRESH = 63% × 3.3V Positive going threshold V Low level of the logic signal into the RC L = 0.1V R del = 100Ω C t del del Timing values = 1nF = –R ⎛ V L – V THRESH ⎞ C × LN ⎜ --------------------------------------- + 1⎟ del del VH – VL ⎝ ⎠ t del = 51.731ns Nominal delay time (EQ. 1) In this example, the high input logic voltage is 5V, the positive threshold is 63% of 3.3V and the low level input logic is 0.1V. Note the rising edge propagation delay of the driver must be added to this value. The minimum recommended value of C is 100pF. The parasitic capacitance of the PCB and any attached scope probes will introduce significant delay errors if smaller values are used. Larger values of C will further minimize errors. Acceptable values of R are primarily effected by the source resistance of the logic inputs. Generally, 100Ω resistors or larger are usable. A practical maximum value, limited by contamination on the PCB, is 1MΩ. FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 Power Dissipation of the Driver The power dissipation of the ISL89160, ISL89161, ISL89162 is dominated by the losses associated with the gate charge of the driven bridge FETs and the switching frequency. The internal bias current also contributes to the total dissipation but is usually not significant as compared to the gate charge losses. Equation 2 shows calculating the power dissipation of the driver: R gate P D = 2 • Q c • freq • V GS • ------------------------------------------ + I DD ( freq ) • V DD R +r 12 Vgs GATE-SOURCE VOLTAGE (V) Figure 16 illustrates how the gate charge varies with the gate voltage in a typical power MOSFET. In this example, the total gate charge for Vgs = 10V is 21.5nC when VDS = 40V. This is the charge that a driver must source to turn-on the MOSFET and must sink to turn-off the MOSFET. gate 10 VDS = 64V 8 DS ( ON ) (EQ. 2) where: freq = Switching frequency, VDS = 40V VGS = VDD bias of the ISL89160, ISL89161, ISL89162 6 Qc = Gate charge for VGS 4 IDD(freq) = Bias current at the switching frequency (see Figure 9) rDS(ON) = ON-resistance of the driver 2 0 Rgate = External gate resistance (if any). 0 2 4 6 8 10 12 14 16 18 20 22 24 Note that the gate power dissipation is proportionally shared with the external gate resistor and the output rDS(ON). When sizing an external gate resistor, do not overlook the power dissipated by this resistor. Qg, GATE CHARGE (nC) FIGURE 16. MOSFET GATE CHARGE vs GATE VOLTAGE Typical Application Circuit Vbridge ZVS Full Bridge SQR PWM L R L QUL VGUL U1A QUR VGUR SQR LL ISL89162 LR VLL U1B Red dashed lines emphasize the resonant switching delay LL of the low-side bridge FETs VLR VGLL VGUL LL: lower left LR: lower right UL: upper left UR: upper right GLL: gate lower left VGLR VGUR T2 T1A T1B QLL VGLL QLR VGLR LR U2A ½ ISL89160 U2B ½ ISL89160 This is an example of how the ISL89160, ISL89161, ISL89162, MOSFET drivers can be applied in a zero voltage switching full bridge. Two main signals are required: a 50% duty cycle square wave (SQR) and a PWM signal synchronized to the edges of the SQR input. An ISL89162 is used to drive T1 with alternating half cycles driving QUL and QUR. An ISL89160 is used to drive QLL and QLR also with alternating half cycles. Unlike the two high-side bridge FETs, the two low side bridge FETs are turned on with a rising edge delay. The delay is setup by the RCD network on the inputs to the ISL89160. The duration of the delay is chosen to turn on the low-side FETs when the voltage on their respective drains is at the resonant valley. For a complete description of the ZVS topology, refer to AN1603 “ISL6752_54 Evaluation Board Application Note”. 9 FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 General PCB Layout Guidelines The AC performance of the ISL89160, ISL89161, ISL89162 depends significantly on the design of the PC board. The following layout design guidelines are recommended to achieve optimum performance: • Place the driver as close as possible to the driven power FET. • Understand where the switching power currents flow. The high amplitude di/dt currents of the driven power FET will induce significant voltage transients on the associated traces. • Keep power loops as short as possible by paralleling the source and return traces. • Use planes where practical; they are usually more effective than parallel traces. • Avoid paralleling high amplitude di/dt traces with low level signal lines. High di/dt will induce currents and consequently, noise voltages in the low level signal lines. General EPAD Heatsinking Considerations The thermal pad is electrically connected to the GND supply through the IC substrate. The epad of the ISL89160, ISL89161, ISL89162 has two main functions: to provide a quiet GND for the input threshold comparators and to provide heat sinking for the IC. The EPAD must be connected to a ground plane and no switching currents from the driven FET should pass through the ground plane under the IC. Figure 17 is a PCB layout example of how to use vias to remove heat from the IC through the epad. EPAD GND PLANE • When practical, minimize impedances in low level signal circuits. The noise, magnetically induced on a 10k resistor, is 10x larger than the noise on a 1k resistor. • Be aware of magnetic fields emanating from transformers and inductors. Gaps in these structures are especially bad for emitting flux. • If you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to minimize coupling. • The use of low inductance components such as chip resistors and chip capacitors is highly recommended. • Use decoupling capacitors to reduce the influence of parasitic inductance in the VDD and GND leads. To be effective, these caps must also have the shortest possible conduction paths. If vias are used, connect several paralleled vias to reduce the inductance of the vias. COMPONENT LAYER EPAD GND PLANE BOTTOM LAYER FIGURE 17. TYPICAL PCB PATTERN FOR THERMAL VIAS For maximum heatsinking, it is recommended that a ground plane, connected to the EPAD, be added to both sides of the PCB. A via array, within the area of the EPAD, will conduct heat from the EPAD to the GND plane on the bottom layer. The number of vias and the size of the GND planes required for adequate heatsinking is determined by the power dissipated by the ISL89160, ISL89161, ISL89162, the air flow and the maximum temperature of the air around the IC. • It may be necessary to add resistance to dampen resonating parasitic circuits especially on OUTA and OUTB. If an external gate resistor is unacceptable, then the layout must be improved to minimize lead inductance. • Keep high dv/dt nodes away from low level circuits. Guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. This is especially true for control circuits that source the input signals to the ISL89160, ISL89161, ISL89162. • Avoid having a signal ground plane under a high amplitude dv/dt circuit. This will inject di/dt currents into the signal ground paths. • Do power dissipation and voltage drop calculations of the power traces. Many PCB/CAD programs have built in tools for calculation of trace resistance. • Large power components (Power FETs, Electrolytic caps, power resistors, etc.) will have internal parasitic inductance which cannot be eliminated. This must be accounted for in the PCB layout and circuit design. • If you simulate your circuits, consider including parasitic components especially parasitic inductance. 10 FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 1/13/11 FN7719.1 1/12/11 11/2/10 CHANGE Removed Option C Reference from Visio Graphics due to parts not releasing yet. Converted to New Intersil Template Updated page 1 Graphic by depicting 2 lines showing positive threshold and 2 lines showing negative threshold: page 1 - Updated copyright to include 2011 page 1 - Removed Related Literature from due to documentation being nonexistent at this time. page 2 - Updated Pin Description Table by placing both pin numbers 1 and 8 on same line page 3 - Updated Ordering Information by adding option B parts page 4 - Added Note Reference to Inputs section in Electrical Spec Table page 5 - Changed Note in Electrical Spec Table From: Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. To: Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN7719.0 Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL89160, ISL89161, ISL89162 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/sear 11 FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 Package Outline Drawing L8.3x3I 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1 6/09 2X 1.950 3.00 B 0.15 8 5 3.00 (4X) 6X 0.65 A 1.64 +0.10/ - 0.15 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 1 4 4 8X 0.30 8X 0.400 ± 0.10 TOP VIEW 0.10 M C A B 2.38 +0.10/ - 0.15 BOTTOM VIEW SEE DETAIL "X" ( 2.38 ) ( 1.95) 0.10 C Max 0.80 C 0.08 C SIDE VIEW ( 8X 0.60) (1.64) ( 2.80 ) PIN 1 C 0 . 2 REF 5 (6x 0.65) 0 . 00 MIN. 0 . 05 MAX. ( 8 X 0.30) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. 12 The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7719.1 January 20, 2011 ISL89160, ISL89161, ISL89162 Small Outline Exposed Pad Plastic Packages (EPSOIC) M8.15D N INDEX AREA H 0.25(0.010) M 8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 TOP VIEW L SEATING PLANE -A- A D -C- α e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S SIDE VIEW MILLIMETERS MAX MIN MAX NOTES A 0.059 0.067 1.52 1.72 - A1 0.003 0.009 0.10 0.25 - B 0.0138 0.0192 0.36 0.46 9 C 0.0075 0.0098 0.19 0.25 - D 0.189 0.196 4.80 4.98 3 E 0.150 0.157 3.811 3.99 4 e h x 45° MIN 0.050 BSC 1.27 BSC - H 0.230 0.244 5.84 6.20 - h 0.010 0.019 0.25 0.50 5 L 0.016 0.050 0.41 1.27 6 8° 0° N α 8 0° 8 7 8° - P 0.118 0.137 3.00 3.50 11 P1 0.078 0.099 2.00 2.50 11 Rev. 0 5/07 NOTES: 1 2 3 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. P1 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. N P BOTTOM VIEW 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 11. Dimensions “P” and “P1” are thermal and/or electrical enhanced variations. Values shown are maximum size of exposed pad within lead count and body size. For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN7719.1 January 20, 2011