19-3346; Rev 1; 9/05 4A, 20ns, MOSFET Driver The MAX5078A/MAX5078B high-speed MOSFET drivers source and sink up to 4A peak current. These devices feature a fast 20ns propagation delay and 20ns rise and fall times while driving a 5000pF capacitive load. Propagation delay time is minimized and matched between the inverting and noninverting inputs. High sourcing/sinking peak currents, low propagation delay, and thermally enhanced packages make the MAX5078A/ MAX5078B ideal for high-frequency and high-power circuits. The MAX5078A/MAX5078B operate from a 4V to 15V single power supply and consume 40µA (typ) of supply current when not switching. These devices have an internal logic circuitry that prevents shoot-through during output state changes to minimize the operating current at a high switching frequency. The logic inputs are protected against voltage spikes up to +18V, regardless of the VDD voltage. The MAX5078A has CMOS input logic levels while the MAX5078B has TTL-compatible input logic levels. The MAX5078A/MAX5078B feature both inverting and noninverting inputs for greater flexibility in controlling the MOSFET. They are available in a 6-pin TDFN (3mm x 3mm) package and operate over the automotive temperature range of -40°C to +125°C. Applications Power MOSFET Switching Motor Control Switch-Mode Power Supplies Power-Supply Modules Features ♦ 4V to 15V Single Power Supply ♦ 4A Peak Source/Sink Drive Current ♦ 20ns (typ) Propagation Delay ♦ Matching Delay Between Inverting and Noninverting Inputs ♦ VDD / 2 CMOS (MAX5078A)/TTL (MAX5078B) Logic Inputs ♦ 0.1 x VDD (CMOS) and 0.3V (TTL) Logic-Input Hysteresis ♦ Up to +18V Logic Inputs (Regardless of VDD Voltage) ♦ Low Input Capacitance: 2.5pF (typ) ♦ 40µA (typ) Quiescent Current ♦ -40°C to +125°C Operating Temperature Range ♦ 6-Pin TDFN Package Ordering Information PART TEMP RANGE PINPACKAGE TOP MARK PKG CODE MAX5078AATT -40°C to +125°C 6 TDFN-EP* AHL T633-1 MAX5078BATT -40°C to +125°C 6 TDFN-EP* AHM T633-1 *EP = Exposed pad. Selector Guide DC-DC Converters PART PIN-PACKAGE MAX5078AATT 6 TDFN-EP VDD / 2 CMOS MAX5078BATT 6 TDFN-EP TTL Pin Configuration Typical Operating Circuit 4V TO 15V LOGIC INPUT TOP VIEW VDD MAX5078 MAX5078A MAX5078B OUT IN+ PWM IN IN- IN- 1 6 IN+ GND 2 5 OUT GND 3 4 VDD N GND TDFN-EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5078 General Description MAX5078 4A, 20ns, MOSFET Driver ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 6-Pin TDFN-EP (derate 18.2mW/°C above +70°C) .......1454mW Junction-to-Case Thermal Resistance (θJC) .......................8.5°C/W Operating Temperature Range..............................-40°C to +125°C Storage Temperature Range .................................-65°C to +150°C Junction Temperature ...........................................................+150°C Lead Temperature (soldering, 10s)......................................+300°C (Voltages referenced to GND.) VDD ..............................................................................-0.3V to +18V IN+, IN- ........................................................................-0.3V to +18V OUT .................................................................-0.3V to (VDD + 0.3V) OUT Short-Circuit Duration.......................................................10ms Continuous Source/Sink Current at OUT_ (PD < PDMAX).....200mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 4V to 15V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 15 V 3.5 3.85 V POWER SUPPLY VDD Operating Range VDD Undervoltage Lockout VDD UVLO 4 VDD rising 3.00 VDD Undervoltage Lockout Hysteresis VDD Undervoltage Lockout to Output Delay VDD Supply Current VDD rising IDD IDD-SW IN+ = 0V, IN- = VDD (not switching) 200 mV 12 µs VDD = 4V 28 55 VDD = 15V 40 75 1.2 2.2 Switching at 250kHz, CL = 0 0.5 µA mA DRIVER OUTPUT (SINK) Driver Output Resistance Pulling Down Peak Output Current (Sinking) RON-N IPK-N Output-Voltage Low Latchup Protection VDD = 15V, IOUT = -100mA TA = +25°C 1.1 1.8 TA = +125°C 1.5 2.4 VDD = 4.5V, IOUT = -100mA TA = +25°C 2.2 3.3 TA = +125°C 3.0 4.5 VDD = 15V, CL = 10,000pF IOUT = -100mA ILUP 4 A VDD = 4.5V 0.45 VDD = 15V 0.24 Reverse current IOUT (Note 2) Ω 400 V mA DRIVER OUTPUT (SOURCE) Driver Output Resistance Pulling Up RON-P Peak Output Current (Sourcing) IPK-P 2 VDD = 15V, IOUT = 100mA TA = +25°C 1.5 2.1 TA = +125°C 1.9 2.75 VDD = 4.5V, IOUT = 100mA TA = +25°C 2.75 4 TA = +125°C 3.75 5.5 VDD = 15V, CL = 10,000pF 4 _______________________________________________________________________________________ Ω A 4A, 20ns, MOSFET Driver (VDD = 4V to 15V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25°C.) (Note 1) PARAMETER SYMBOL Output-Voltage High CONDITIONS MIN VDD = 4.5V VDD 0.55 VDD = 15V VDD 0.275 IOUT = 100mA TYP MAX UNITS V LOGIC INPUT (Note 3) Logic 1 Input Voltage VIH MAX5078A MAX5078B (Note 4) Logic 0 Input Voltage Logic-Input Hysteresis VIL VHYS 0.7 x VDD 2.1 MAX5078A 0.3 x VDD MAX5078B 0.8 0.1 x VDD MAX5078A MAX5078B Logic-Input-Current Leakage Input Capacitance V IN+ = IN- = 0V or VDD V V 0.3 -1 CIN +0.1 +1 2.5 µA pF SWITCHING CHARACTERISTICS FOR VDD = 15V (Figure 1) OUT Rise Time tR OUT Fall Time tF CL = 1000pF 4 CL = 5000pF 18 CL = 10,000pF 32 CL = 1000pF 4 CL = 5000pF 15 CL = 10,000pF 26 ns ns Turn-On Delay Time tD-ON CL = 10,000pF (Note 2) 10 20 34 ns Turn-Off Delay Time tD-OFF CL = 10,000pF (Note 2) 10 20 34 ns SWITCHING CHARACTERISTICS FOR VDD = 4.5V (Figure 1) CL = 1000pF OUT Rise Time tR OUT Fall Time tF 7 CL = 5000pF 37 CL = 10,000pF 85 CL = 1000pF 7 CL = 5000pF 30 CL = 10,000pF 75 ns ns Turn-On Delay Time tD-ON CL = 10,000pF (Note 2) 18 35 70 ns Turn-Off Delay Time tD-OFF CL = 10,000pF (Note 2) 18 35 70 ns _______________________________________________________________________________________ 3 MAX5078 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VDD = 4V to 15V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MATCHING CHARACTERISTICS Mismatch Propagation Delays from Inverting and Noninverting Inputs to Output Note 1: Note 2: Note 3: Note 4: ∆tON-OFF VDD = 15V, CL = 10,000pF 2 VDD = 4.5V, CL = 10,000pF 4 ns All devices are 100% tested at TA = +25°C. Specifications over -40°C to +125°C are guaranteed by design. Limits are guaranteed by design, not production tested. The logic-input thresholds are tested at VDD = 4V and VDD = 15V. TTL compatible with reduced noise immunity. Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) TA = +125°C 30 20 20 10 10 TA = +25°C TA = -40°C 6 8 10 12 14 8 10 12 14 IDD-SW SUPPLY CURRENT vs. SUPPLY VOLTAGE 20 DUTY CYCLE = 50% VDD = 15V, CL = 0 5 4 500kHz 2 1 TA = -40°C 0 6 8 10 12 SUPPLY VOLTAGE (V) 14 16 MAX5078 toc03 12 14 16 DUTY CYCLE = 50% VDD = 15V, CL = 4700pF 90 80 70 1MHz 60 50 500kHz 40 30 50kHz 100kHz 10 0 0 4 10 20 50kHz 100kHz 8 SUPPLY CURRENT vs. SUPPLY VOLTAGE 1MHz 3 6 100 SUPPLY CURRENT (mA) TA = +25°C 30 IDD-SW SUPPLY CURRENT (mA) MAX5078 toc04 40 6 4 16 MAX5078 toc05 PROPAGATION DELAY TIME, HIGH-TO-LOW vs. SUPPLY VOLTAGE (CL = 5000pF) TA = +125°C TA = -40°C SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 10 4 6 SUPPLY VOLTAGE (V) 60 50 4 16 20 0 0 4 TA = +25°C 30 10 TA = -40°C 0 40 MAX5078 toc06 TA = +25°C 40 TA = +125°C 50 PROPAGATION DELAY (ns) 50 FALL TIME (ns) RISE TIME (ns) TA = +125°C 40 60 MAX5078 toc02 50 30 60 MAX5078 toc01 60 PROPAGATION DELAY TIME, LOW-TO-HIGH vs. SUPPLY VOLTAGE (CL = 5000pF) FALL TIME vs. SUPPLY VOLTAGE (CL = 5000pF) RISE TIME vs. SUPPLY VOLTAGE (CL = 5000pF) PROPAGATION DELAY (ns) MAX5078 4A, 20ns, MOSFET Driver 4 6 8 10 12 SUPPLY VOLTAGE (V) 14 16 4 6 8 10 12 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 14 16 4A, 20ns, MOSFET Driver VIN RISING 6 5 4 VIN FALLING 3 2 VIN RISING 2.0 MAX5078B (TTL INPUT) VDD = 15V 400 SUPPLY CURRENT (µA) 7 MAX5078B (TTL INPUT) 2.5 500 MAX5078 toc08 8 3.0 INPUT THRESHOLD VOLTAGE (V) MAX5078A (CMOS INPUT) 9 INPUT THRESHOLD VOLTAGE (V) MAX5078 toc07 10 SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT LOW-TO-HIGH) INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE 1.5 1.0 VIN FALLING MAX5078 toc09 INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE 300 200 100 0.5 1 0 0 4 6 8 10 12 16 14 12 14 16 2 4 6 8 10 12 14 SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT HIGH-TO-LOW) SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT LOW-TO-HIGH) SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT HIGH-TO-LOW) 3 2 1 100 2 4 6 8 10 12 14 3 2 0 0 16 4 1 0 0 MAX5078A (CMOS INPUT) VDD = 15V SUPPLY CURRENT (mA) 4 16 MAX5078 toc12 MAX5078A (CMOS INPUT) VDD = 15V SUPPLY CURRENT (mA) 200 5 MAX5078 toc11 5 MAX5078 toc10 300 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 LOGIC-INPUT VOLTAGE (V) LOGIC-INPUT VOLTAGE (V) LOGIC-INPUT VOLTAGE (V) DELAY MISMATCH BETWEEN IN+ AND IN- TO OUT vs. TEMPERATURE DELAY MISMATCH BETWEEN IN+ AND IN- TO OUT vs. TEMPERATURE LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 5000pF) OUTPUT FALLING 2 OUTPUT RISING 0 4 DELAY MISMATCH (ns) 4 -2 MAX5078 toc15 6 MAX5078 toc13 6 OUTPUT RISING IN2V/div 2 0 -2 -6 OUT 2V/div OUTPUT FALLING -4 MAX5078A (CMOS INPUT) VDD = 4.5V, CL = 10,000pF MAX5078 toc14 0 0 LOGIC-INPUT VOLTAGE (V) 400 SUPPLY CURRENT (µA) 10 SUPPLY VOLTAGE (V) MAX5078B (TTL INPUT) VDD = 15V DELAY MISMATCH (ns) 8 SUPPLY VOLTAGE (V) 500 -4 0 6 4 MAX5078A (CMOS INPUT) VDD = 15V, CL = 10,000pF IN+ = VDD -6 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 0 25 50 75 100 125 20ns/div TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX5078 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX5078 4A, 20ns, MOSFET Driver Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 5000pF) LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 10,000pF) MAX5078 toc16 MAX5078 toc17 MAX5078B (TTL INPUT) MAX5078B (TTL INPUT) IN2V/div IN2V/div OUT 2V/div OUT 2V/div IN+ = VDD IN+ = VDD 40ns/div 20ns/div LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 5000pF) LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 10,000pF) MAX5078 toc19 MAX5078 toc18 MAX5078B (TTL INPUT) IN2V/div IN2V/div OUT 5V/div OUT 2V/div MAX5078B (TTL INPUT) IN+ = VDD IN+ = VDD 20ns/div 40ns/div LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 10,000pF) MAX5078 toc20 IN2V/div OUT 5V/div MAX5078B (TTL INPUT) IN+ = VDD 40ns/div 6 _______________________________________________________________________________________ 4A, 20ns, MOSFET Driver LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 5000pF) MAX5078 toc21 MAX5078B (TTL INPUT) LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 10,000pF) MAX5078 toc22 MAX5078B (TTL INPUT) IN2V/div IN2V/div OUT 5V/div OUT 5V/div IN+ = VDD IN+ = VDD 20ns/div 40ns/div VDD vs. OUTPUT VOLTAGE VDD vs. OUTPUT VOLTAGE MAX5078 toc24 MAX5078 toc23 MAX5078B (TTL INPUT) VDD 5V/div MAX5078B (TTL INPUT) VDD 5V/div OUT 5V/div IN+ = 15V IN- = GND CL = 10,000pF 2ms/div IN+ = 15V IN- = GND CL = 10,000pF OUT 5V/div 2ms/div _______________________________________________________________________________________ 7 MAX5078 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) 4A, 20ns, MOSFET Driver MAX5078 Pin Description PIN NAME 1 IN- FUNCTION 2, 3 GND Ground 4 VDD Power Supply. Bypass to GND with one or more 0.1µF ceramic capacitors. 5 OUT Driver Output. Sources or sinks current to turn the external MOSFET on or off. 6 IN+ Noninverting Logic-Input Terminal. Connect to VDD when not used. — EP Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical ground connection. Inverting Logic-Input Terminal. Connect to GND when not used. Detailed Description VDD Undervoltage Lockout (UVLO) The MAX5078A/MAX5078B have internal undervoltage lockout (UVLO) for VDD. When VDD is below the UVLO threshold, OUT is pulled low independent of the state of the inputs. The undervoltage lockout is typically 3.5V with 200mV typical hysteresis to avoid chattering. When VDD rises above the UVLO threshold, the output goes high or low depending upon the logic-input levels. Bypass VDD using a low-ESR ceramic capacitor for proper operation (see the Applications Information section). Logic Inputs The MAX5078A has CMOS logic inputs while the MAX5078B has TTL-compatible logic inputs. The logic inputs are protected against the voltage spikes up to 18V, regardless of the VDD voltage. The TTL and CMOS logic inputs have 300mV and 0.1 x V DD hysteresis, respectively, to avoid double pulsing during transition. The low 2.5pF input capacitance reduces loading and increases switching speed. The logic inputs are high impedance and must not be left floating. If the inputs are left open, OUT can go to an undefined state as soon as VDD rises above the UVLO threshold. Therefore, the PWM output from the controller must assume proper state when powering up the device. The MAX5078A/MAX5078B have two logic inputs, providing greater flexibility in controlling the MOSFET. Use IN+ for noninverting logic and IN- for inverting logic operation. Connect IN+ to V DD and IN- to GND, if not used. Alternatively, the unused input can be used as an ON/OFF function. Use IN+ for active-low shutdown logic and IN- for active-high shutdown logic (see Figure 3). See Table 1 for all possible input combinations. 8 Driver Output The MAX5078A/MAX5078B have low RDS(ON) p-channel and n-channel devices (totem pole) in the output stage for the fast turn-on/turn-off, high-gate-charge switching MOSFETs. The peak source or sink current is typically 4A. The output voltage (VOUT) is approximately equal to VDD when in high state and is ground when in low state. The driver RDS(ON) is lower at higher VDD resulting in higher source-/sink-current capability and faster switching speeds. The propagation delays from the noninverting and inverting logic inputs to OUT are matched to 2ns typically. The break-before-make logic avoids any crossconduction between the internal p- and n-channel devices, and eliminates shoot-through, thus reducing the quiescent supply current. Applications Information RLC Series Circuit The driver’s RDS(ON) (RON), internal bond/lead inductance (LP), trace inductance (LS), gate inductance (LG), and gate capacitance (C G ) form a series RLC circuit with a second-order characteristic equation. The series RLC circuit has an undamped natural frequency (ϖ0) and a damping ratio (ζ) where: ϖ0 = 1 (LP + LS + LG ) × CG RON ξ= 2 × (LP + LS + LG ) CG The damping ratio needs to be greater than 0.5 (ideally 1) to avoid ringing. Add a small resistor (RGATE) in series with the gate when driving a very low gatecharge MOSFET, or when the driver is placed away from the MOSFET. _______________________________________________________________________________________ 4A, 20ns, MOSFET Driver MAX5078 IN+ VIH VIL VDD MAX5078A MAX5078B 90% IN- OUT 10% tD-OFF1 tD-ON1 tF IN- tR P BREAKBEFOREMAKE CONTROL IN+ OUT N VIH VIL tD-OFF2 tD-ON2 GND RISING MISMATCH = tD-ON2 - tD-ON1 FALLING MISMATCH = tD-OFF2 - tD-OFF1 Figure 1. Timing Diagram Figure 2. MAX5054 Simplified Diagram (1 Driver) Use the following equation to calculate the series resistor: The current required to charge and discharge the internal nodes is frequency dependent (see the IDD-SW Supply Current vs. Supply Voltage graph in the Typical Operating Characteristics). The power dissipation (PQ) due to the quiescent switching supply current (IDD-SW) can be calculated as: PQ = VDD x IDD-SW RGATE ≥ (LP + LS + LG ) − RON CG LP can be approximated as 2nH for the TDFN package. LS is on the order of 20nH/in. Verify LG with the MOSFET vendor. Supply Bypassing and Grounding Pay extra attention to bypassing and grounding the MAX5078A/MAX5078B. Peak supply and output currents may exceed 4A when driving large external capacitive loads. Supply voltage drops and ground shifts create negative feedback for inverters and may degrade the delay and transition times. Ground shifts due to poor device grounding may also disturb other circuits sharing the same AC ground return path. Any series inductance in the VDD, OUT, and/or GND paths can cause oscillations due to the very high di/dt when switching the MAX5078A/MAX5078B with any capacitive load. Place one or more 0.1µF ceramic capacitors in parallel as close to the device as possible to bypass VDD to GND. Use a ground plane to minimize ground return resistance and series inductance. Place the external MOSFET as close as possible to the MAX5078A/MAX5078B to further minimize board inductance and AC path impedance. Power Dissipation Power dissipation of the MAX5078A/MAX5078B consists of three components: caused by the quiescent current, capacitive charge/discharge of internal nodes, and the output current (either capacitive or resistive load). Maintain the sum of these components below the maximum power dissipation limit. For capacitive loads, use the following equation to estimate the power dissipation: PCLOAD = CLOAD x (VDD)2 x fSW where CLOAD is the capacitive load, VDD is the supply voltage, and fSW is the switching frequency. Calculate the total power dissipation (PT) as follows: PT = PQ + PCLOAD Use the following equations to estimate the MAX5078A/ MA5078B total power dissipation when driving a groundreferenced resistive load: PT = PQ + PRLOAD PRLOAD = D x RON(MAX) x ILOAD2 where D is the fraction of the period the MAX5078A/ MA5078B’s output pulls high, RON(MAX) is the maximum on-resistance of the device with the output high, and I LOAD is the output load current of the MAX5078A/ MAX5078B. Layout Information The MAX5078A/MAX5078B MOSFET drivers source and sink large currents to create very fast rising and falling edges at the gate of the switching MOSFET. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. _______________________________________________________________________________________ 9 MAX5078 4A, 20ns, MOSFET Driver Table 1. MAX5078 Truth Table IN+ IN- OUT Low Low Low Low High Low High Low High High High Low VDD MAX5078 PWM INPUT OFF Use the following PC board layout guidelines when designing with the MAX5078A/MAX5078B: • • • • • Place one or more 0.1µF decoupling ceramic capacitors from VDD to GND as close to the device as possible. Connect VDD and GND to large copper areas. Place one bulk capacitor of 10µF (min) on the PC board with a low resistance path to the VDD input and GND of the MAX5078A/MAX5078B. Two AC current loops form between the device and the gate of the driven MOSFET. The MOSFET looks like a large capacitance from gate to source when the gate pulls low. The active current loop is from the MOSFET gate to OUT of the MAX5078A/MAX5078B, to GND of the MAX5078A/MAX5078B, and to the source of the MOSFET. When the gate of the MOSFET pulls high, the active current is from the VDD terminal of the decoupling capacitor, to V DD of the MAX5078A/MAX5078B, to OUT of the MAX5078A/ MAX5078B, to the MOSFET gate, to the MOSFET source, and to the negative terminal of the decoupling capacitor. Both charging current and discharging current loops are important. Minimize the physical distance and the impedance in these AC current paths. Keep the device as close to the MOSFET as possible. In a multilayer PC board, the inner layers should consist of a GND plane containing the discharging and charging current loops. Pay extra attention to the ground loop and use a low-impedance source when using a TTL logicinput device. Fast fall time at OUT may corrupt the input during transition. IN+ ON GND Figure 3. Unused Input as an ON/OFF Function Additional Application Circuits VS VDD VDD MAX5078A MAX5078B OUT IN+ IN- N GND Figure 4. Noninverting Application VS 4V TO 15V VDD Exposed Pad The TDFN-EP package has an exposed pad on the bottom of its package. This pad is internally connected to GND. For the best thermal conductivity, solder the exposed pad to the ground plane in order to dissipate 1.9W. Do not use the ground-connected pad as the only electrical ground connection or ground return. Use GND (pins 2 and 3) as the primary electrical ground connection. IN- OUT VOUT MAX5078A MAX5078B OUT IN+ FROM PWM CONTROLLER (BOOST) IN- GND Figure 5. Boost Converter 10 ______________________________________________________________________________________ N 4A, 20ns, MOSFET Driver TRANSISTOR COUNT: 258 PROCESS: CMOS VDD IN+ MAX5078A MAX5078B OUT P INFROM PWM CONTROLLER (BOOST) GND VDD IN+ VOUT MAX5078A MAX5078B OUT N INGND Figure 6. MAX5078A/MAX5078B In High-Power Synchronous Buck Converter VIN VOUT 4V TO 15V VDD 4V TO 15V VDD MAX5078 PWM IN VDD OUT IN+ MAX5078 MAX5078 OUT IN- GND IN+ OUT IN+ GND IN- IN- GND SIGNAL FROM PRIMARY Figure 7. Forward Converter with Secondary-Side Synchronous Rectification ______________________________________________________________________________________ 11 MAX5078 Chip Information 4V TO 15V Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 6, 8, &10L, DFN THIN.EPS MAX5078 4A, 20ns, MOSFET Driver D2 D A2 PIN 1 ID N 0.35x0.35 b PIN 1 INDEX AREA E [(N/2)-1] x e REF. E2 DETAIL A e k A1 CL A CL L L e e PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm -DRAWING NOT TO SCALE- 21-0137 G 1 2 COMMON DIMENSIONS MIN. MAX. D 0.70 2.90 0.80 3.10 E A1 2.90 0.00 3.10 0.05 L k 0.20 0.40 0.25 MIN. A2 0.20 REF. SYMBOL A PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e DOWNBONDS ALLOWED T633-1 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF NO T633-2 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF NO T833-1 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF NO T833-2 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF NO T833-3 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF YES T1033-1 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF NO T1433-1 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF YES T1433-2 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF NO PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm -DRAWING NOT TO SCALE- 21-0137 G 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.