HSP45256/883 TM December 1999 Features T UCT ODUC PROD IL TE P R E E T L U O OB S BSTIT T ER S LE SU ns 1-888-IN IB S S PO l.com atio FOR A tral Applic pp@intersi en ta call C email: cen or Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The Intersil HSP45256/883 is a high-speed, 256 tap binary correlator. It can be configured to perform one-dimensional or two-dimensional correlations of selectable data precision and length. Multiple HSP45256’s can be cascaded for increased correlation length. Unused taps can be masked out for reduced correlation length. • Reconfigurable 256 Stage Binary Correlator • 1-Bit Reference x 1, 2, 4, or 8-Bit Data • Separate Control and Reference Interfaces The correlation array consists of eight 32-tap stages. These may be cascaded internally to compare 1, 2, 4 or 8-bit input data with a 1-bit reference. Depending on the number of bits in the input data, the length of the correlation can be up to 256, 128, 64, or 32 taps. The HSP45256 can also be configured as two separate correlators with window sizes from 4 by 32 to 1 by 128 each. The Mask Register can be used to prevent any subset of the 256 bits from contributing to the correlation score. • Configurable for 1-D and 2-D Operation • Double Buffered Mask and Reference • Programmable Output Delay • Cascadable • Standard Microprocessor Interface Applications The9- output of the correlation array (correlation score) feeds the weight and sum logic, which gives added flexibility to the data format. In addition, an offset register is provided so that a preprogrammed value can be added to the correlation score. This result is then passed through a user programmable delay stage to the cascade summer. The delay stage simplifies the cascading of multiple correlators by compensating for the latency of previous correlators. • Radar/Sonar • Spread Spectrum Communications • Pattern/Character Recognition • Error Correction Coding Ordering Information PART NUMBER TEMP. RANGE ( oC) HSP45256GM-20/883 -55 to 125 85 Ld CPGA G85.A HSP45256GM-25/883 -55 to 125 85 Ld CPGA G85.A PACKAGE Binary Correlator PKG. NO. The Binary Correlator is configured by writing a set of control registers via a standard microprocessor interface. To simplify operation, both the Control and Reference Registers are double buffered. This allows the user to load new mask and reference data while the current correlation is in progress. Block Diagram DOUT0-7 DIN0-7 256 TAP CORRELATION ARRAY MUX AUXOUT0-8 DREF0-7 WEIGHT AND SUM DCONT0-7 CONTROL DELAY CASCADE SUMMER CASOUT0-12 A0-2 CASIN0-12 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 FN2997.4 HSP45256/883 Pinouts 85 PIN PGA TOP VIEW 1 A 2 3 4 5 6 CASIN CASIN CASIN CASIN CASIN CASIN 2 4 5 7 10 11 CAS OUT 2 7 8 9 10 11 CAS OUT 0 CAS OUT 3 CAS OUT 5 GND CAS OUT 8 CAS OUT 1 CAS OUT 4 CAS OUT 6 CAS OUT 7 CAS OUT 10 CAS OUT 9 CAS OUT 11 CAS OUT 12 B GND CASIN CASIN CASIN CASIN 1 3 6 9 C CLK CASIN INDEX PIN 0 D DIN7 VCC E DIN4 DIN5 DIN6 DOUT0 DOUT1 DOUT2 F DREF 6 DIN3 DIN2 DOUT DOUT 4 7 DOUT 3 G DIN0 DREF 7 DIN1 DOUT 6 DOUT 5 H DREF DREF 5 4 AUX OUT 1 AUX OUT 0 J DREF DREF 3 1 GND AUX OUT 2 K DREF 2 VCC R LOAD C LOAD AUX OUT 6 AUX OUT 4 AUX OUT 3 L DREF 0 GND TXFR A2 AUX OUT 8 AUX OUT 7 AUX OUT 5 CASIN CASIN 12 8 OEC GND VCC A1 DCONT DCONT 5 4 A0 DCONT DCONT OEA 6 2 DCONT DCONT DCONT DCONT 7 1 3 0 85 PIN PGA BOTTOM VIEW L DREF0 GND TXFR DREF2 V CC RLOAD DREF3 DREF1 DREF5 DREF4 DIN0 DREF7 DIN1 DREF6 DIN3 DIN4 DIN5 DIN7 VCC CLK CASIN0 INDEX PIN GND CASIN1 CASIN3 CASIN 2 CASIN 4 CASIN 5 1 2 3 A2 DCONT 7 DCONT 1 DCONT 3 DCONT0 CLOAD A0 DCONT 6 DCONT 2 OEA A1 DCONT 5 DCONT 4 AUXOUT 8 AUXOUT 7 AUXOUT 5 AUXOUT 4 AUXOUT 3 K AUXOUT 6 J GND AUXOUT 2 AUXOUT 1 AUXOUT 0 VCC DOUT6 DOUT5 DIN2 DOUT4 DOUT7 DOUT3 DIN6 DOUT0 DOUT1 DOUT2 GND CASOUT 12 CASOUT 9 CASOUT 11 CASOUT 7 CASOUT 10 H G F E D C CASIN 8 CASIN 12 CASIN6 CASIN 9 CASOUT 2 CASIN 7 CASIN 10 CASIN 11 OEC B CASOUT 1 CASOUT CASOUT 4 6 A 4 5 6 9-2 CASOUT CASOUT 0 3 7 8 CASOUT 5 GND 9 10 CASOUT 8 11 HSP45256/883 Pin Description SYMBOL PIN NUMBER TYPE DESCRIPTION VCC D2, G9, K2 The +5V power supply pin. GND A10, B1, D10, J10, L2 Ground. DIN0-7 D1, E1-E3, F2, F3, G1, G3 I The DIN0-7 bus consists of eight single data input pins. The assignment of the active pins is determined by the configuration. Data is loaded synchronous to the rising edge of CLK. DIN0 is the LSB. E9-E11, F9-F11, G10, G11 O The DOUT0-7 bus is the data output of the correlation array. The format of the output is dependent on the window configuration and bit weighting. DOUT0 is the LSB. C1 I System Clock. Positive edge triggered. CASIN0-12 A1-A6, B2-B5, C2, C5, C6 I CASIN0-12 allows multiple correlators to be cascaded by connecting CASOUT0-12 of one correlator to CASIN0-12 of another. The CASIN bus is added internally to the correlation score to form CASOUT. CASIN0 is the LSB. CASOUT0-12 A7-A9, A11, B6-B11, C10, C11, D11 O CASOUT0-12 is the output correlation score. This value is the delayed sum of all the 256 taps of one chip and CASIN0-12. When the part is configured to act as two independent correlators, CASOUT0-8 represents the correlation score for the first correlator while the second correlation score is available on the AUXOUT0-8 bus. In this configuration, the cascading feature is no longer an option. CASOUT0 is the LSB. OEC C7 I OEC is the output enable for CASOUT0-12. When OEC is high, the output is three-stated. Processing is not interrupted by this pin (active low). TXFR L3 I TXFR is a synchronous clock enable signal that allows the loading of the reference and mask inputs from the preload register to the correlation array. Data is transferred on the rising edge of CLK while TXFR is low (active low). F1, G2, H1, H2, J1, J2, K1, L1 I DREF0-7 is an 8-bit wide data reference input. This is the input data bus used to load the reference data. RLOAD going active initiates the loading of the reference registers. This input bus is used to load the reference registers of the correlation array. The manner in which the reference data is loaded is determined by the window configuration. If the window configuration is 1 x 256, the reference bits are loaded one at a time over DREF7. When the HSP45256 is configured as an 8 x 32 array, the data is loaded into all stages in parallel. In this case, DREF7 is the reference data for the first stage and DREF0 is the reference data for the eighth stage. The contents of the reference data registers are not affected by changing the window configuration. DREF0 is the LSB. K3 I RLOAD enables loading of the reference registers. Data on DREF0-7 is loaded into the preload registers on the rising edge of RLOAD. This data is transferred into the correlation array by TXFR (active low). J6, J7, K6, K7, L5-L8 I DCONT0-7 is the control data input, which is used to load the mask bit for each tap as well as the configuration registers. The mask data is sequentially loaded into the eight stages in the same manner as the reference data. DCONT0 is the LSB. K4 I CLOAD enables the loading of the data on DCONT0-7. The destination of this data is controlled by A0-2 (active low). J5, K5, L4 I A0-2 is a 3-bit address that determines what function will be performed when CLOAD is active. This address bus is set up with respect to the rising edge of the load signal, CLOAD. A0 is the LSB. H10, H11, J11, K9-K11, L9-L11 O AUXOUT0-8 is a 9-bit bus that provides either the data reference output or the 9-bit correlation score of the second correlator, depending on the configuration. When the user programs the chip to be two separate correlators, the score of the second correlator is output on this bus. When the user has programmed the chip to be one correlator, AUXOUT0-7 represents the reference data out, with the state of AUXOUT0-8 undefined. AUXOUT0 is the LSB. OEA K8 I The OEA signal is the output enable for the AUXOUT0-8 output. When OEA is high, the output is disabled. Processing is not interrupted by this pin (active low). Index Pin C3 DOUT0-7 CLK DREF0-7 RLOAD DCONT0-7 CLOAD# A0-2 AUXOUT0-8 Used for orienting pin in socket or printed circuit board. Must be left as a no connect in circuit. 9-3 HSP45256/883 Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 θJC Thermal Resistance (Typical, Note 1). . . θJA PGA Package . . . . . . . . . . . . . . . . . . . 36oC/W 10oC/W Maximum Package Power Dissipation at 125oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39W Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13,000 Gates Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL CONDITIONS GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 2.2 - V Logical Zero Input Voltage VIL VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Logical One Input Voltage Clock VIHC VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 3.0 - V Logical Zero Input Voltage Clock VILC VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Output HIGH Voltage VOH IOH = -400µA VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 2.6 - V Output LOW Voltage VOL IOL = +2.0mA VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 - 0.4 V Input Leakage Current II VIN = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Output Leakage Current IO VIN = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Standby Power Supply Current ICCSB VIN = VCC or GND VCC = 5.5V, Outputs Open 1, 2, 3 -55 ≤ TA ≤ 125 - 500 µA Operating Power Supply Current ICCOP f = 20 MHz, VIN = VCC or GND, VCC = 5.5V (Note 3) 1, 2, 3 -55 ≤ TA ≤ 125 - 140 mA 7, 8 -55 ≤ TA ≤ 125 - - - Functional Test FT (Note 4) NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 7mA/MHz. 4. Tested as follows: f = 1MHz, VIH (clock inputs) = 3.4V, VIH (all other inputs) = 2.6V, VIL = 0.4V, VOH ≥ 1.5V, and VOL ≤ 1.5V. 9-4 HSP45256/883 TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (Note 5) PARAMETER SYMBOL (NOTE 5) NOTES -25 (25.6MHz) -20 (20MHz) GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX MIN MAX UNITS CLK Period t CP 9, 10, 11 -55 ≤ TA ≤ 125 39 - 50 - ns CLK High t CH 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns CLK Low t CL 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns CLOAD Cycle Time t CLC 9, 10, 11 -55 ≤ TA ≤ 125 39 - 50 - ns CLOAD High t CLH 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns CLOAD Low t CLL 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns RLOAD Cycle Time t RLC 9, 10, 11 -55 ≤ TA ≤ 125 39 - 50 - ns RLOAD High t RLH 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns RLOAD Low t RLL 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns Set-up Time; DIN to CLK High t DS 9, 10, 11 -55 ≤ TA ≤ 125 13 - 15 - ns Hold Time; DIN to CLK High t DH 9, 10, 11 -55 ≤ TA ≤ 125 1 - 1 - ns Set-up Time; DREF to RLOAD High t RS 9, 10, 11 -55 ≤ TA ≤ 125 14 - 15 - ns Hold Time; DREF to RLOAD High t RH 9, 10, 11 -55 ≤ TA ≤ 125 1 - 1 - ns DCONT Set up Time t DCS 9, 10, 11 -55 ≤ TA ≤ 125 13 - 15 - ns DCONT Hold Time t DCH 9, 10, 11 -55 ≤ TA ≤ 125 1 - 1 - ns Address Set up Time t AS 9, 10, 11 -55 ≤ TA ≤ 125 13 - 15 - ns Address Hold Time t AH 9, 10, 11 -55 ≤ TA ≤ 125 1 - 1 - ns TXFR Set up Time t TS 9, 10, 11 -55 ≤ TA ≤ 125 13 - 15 - ns TXFR Hold Time t TH 9, 10, 11 -55 ≤ TA ≤ 125 1 - 1 - ns CLK to Output Delay DOUT, AUXOUT, CASOUT t DO 9, 10, 11 -55 ≤ TA ≤ 125 - 20 - 25 ns Output Enable Time t OE Note 6 9, 10, 11 -55 ≤ TA ≤ 125 - 20 - 20 ns TXFR High to CLK Low t THCL Note 7 9, 10, 11 -55 ≤ TA ≤ 125 3 - 4 - ns CLK Low to RLOAD, CLOAD High t CLLH Note 7 9, 10, 11 -55 ≤ TA ≤ 125 1 - 1 - ns NOTES: 5. AC testing is performed as follows: VCC = 4.5V and 5.5V. Input levels (CLK input) 4.0V and 0V; input levels (all other inputs) 3.0V and 0V; Timing reference levels (CLK) 2.0V; all others 1.5V. Output load per test load circuit with CL = 40pF. Output transition is measured at VOH ≥ 1.5V and VOL ≤ 1.5V. 6. Transition is measured at ±200mV from steady state voltage, Output loading per test load circuit, CL = 40pF. 7. Applicable only when TXFR and RLOAD or CLOAD are active on the same cycle of CLK. 9-5 HSP45256/883 TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS -25 PARAMETER Input Capacitance SYMBOL CIN Output Capacitance COUT Output Disable Time tOD CONDITIONS -20 NOTES TEMPERATURE (oC) MIN MAX MIN MAX UNITS 8 -55 ≤ TA ≤ 125 - 10 - 10 pF 8 -55 ≤ TA ≤ 125 - 10 - 10 pF 8, 9 -55 ≤ TA ≤ 125 - 20 - 20 ns VCC = Open, f = 1MHz All measurements are referenced to device GND. Output Rise Time tR From 0.8V to 2.0V 8, 9 -55 ≤ TA ≤ 125 - 8 - 8 ns Output Fall Time tF From 2.0V to 0.8V 8, 9 -55 ≤ TA ≤ 125 - 8 - 8 ns NOTES: 8. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 9. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples/5005 1, 7, 9 Group A Groups C and D Test Load Circuit S1 DUT (NOTE) C L IOH ± 1.5V EQUIVALENT CIRCUIT SWITCH S1 OPEN FOR ICCSB AND I CCOP TEST NOTE: Includes stray and jig capacitance. 9-6 IOL HSP45256/883 Timing Waveforms tCP tCH tCL t CLC CLK tCLH tDS tDH CLOAD DIN0-7 tTS tCLL tTH tAS tAH tCS tCH A0-7 tTS TXFR tDO DCONT0-7 DOUT0-7 CASOUT0-12, AUXOUT0-8 FIGURE 1. INPUT, OUTPUT TIMING FIGURE 2. tRLC tRLL tRLH OEA, OEC RLOAD tOD tAS tAH tRS tRH tOE AUXOUT0-8 CASOUT0-12 1.7V 1.3V A0-2 tr, tf DOUT0-7, CASOUT0-12 AUXOUT0-8 2.0V 0.8V DREF0-7 FIGURE 3. FIGURE 4. tCLLH tTHCL CLK TXFR RLOAD, CLOAD FIGURE 5. TRANSFER, LOAD TIMING WHEN BOTH OCCUR ON A SINGLE CYCLE 9-7 HSP45256/883 Burn-In Circuits 85 PIN PGA TOP VIEW 1 A PGA PIN PIN NAME 2 3 4 5 6 CASIN CASIN CASIN CASIN CASIN CASIN 2 4 5 7 10 11 CAS OUT 2 7 8 9 10 11 CAS OUT 0 CAS OUT 3 CAS OUT 5 GND CAS OUT 8 CAS OUT 1 CAS OUT 4 CAS OUT 6 CAS OUT 7 CAS OUT 10 CAS OUT 9 CAS OUT 11 GND CAS OUT 12 B GND CASIN CASIN CASIN CASIN 1 3 6 9 C CLK CASIN INDEX PIN 0 D DIN7 VCC E DIN4 DIN5 DIN6 F DREF 4 DIN3 DIN2 DOUT 4 DOUT 7 DOUT 3 G DIN0 DREF 7 DIN1 VCC DOUT 6 DOUT 5 H DREF 5 DREF 4 AUX OUT 1 AUX OUT 0 J DREF 3 DREF 1 GND AUX OUT 2 K DREF 2 VCC R LOAD C LOAD AUX OUT 6 AUX OUT 4 AUX OUT 3 L DREF 0 GND TXFR A2 AUX OUT 8 AUX OUT 7 AUX OUT 5 BURN-IN SIGNAL PGA PIN CASIN CASIN 8 12 OEC DOUT0 DOUT1 DOUT2 PIN NAME A1 DCONT DCONT 5 4 A0 DCONT DCONT OEA 6 2 DCONT DCONT DCONT DCONT 7 1 3 0 BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL A1 CASIN2 F3 B11 CASOUT10 VCC/2 F9 DOUT4 VCC/2 K2 VCC VCC A2 CASIN4 F5 C1 CLK F0 F10 DOUT7 VCC/2 K3 RLOAD F3 A3 CASIN5 F6 C2 CASIN0 F1 F11 DOUT3 VCC/2 K4 CLOAD F3 A4 CASIN7 F1 C5 CASIN8 F2 G1 DIN0 F1 K5 A0 F9 A5 CASIN10 F4 C6 CASIN12 F6 G2 DREF7 F8 K6 DCONT6 F7 A6 CASIN11 F5 C7 OEC F11 G3 DIN1 F2 K7 DCONT2 F6 A7 CASOUT0 VCC/2 C10 CASOUT9 VCC/2 G9 VCC VCC K8 OEA F11 A8 CASOUT3 VCC/2 C11 CASOUT11 VCC/2 G10 DOUT6 VCC/2 K9 AUXOUT6 VCC/2 A9 CASOUT5 VCC/2 D1 DIN7 F8 G11 DOUT5 VCC/2 K10 AUXOUT4 VCC/2 A10 GND GND D2 VCC VCC H1 DREF5 F6 K11 AUXOUT3 VCC/2 A11 CASOUT8 VCC/2 D10 GND GND H2 DREF4 F8 L1 DREF0 F4 B1 GND GND D11 CASOUT12 VCC/2 H10 AUXOUT1 VCC/2 L2 GND GND B2 CASIN1 F2 E1 DIN4 F5 H11 AUXOUT0 VCC/2 L3 TXFR F2 9-8 HSP45256/883 (Continued) PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL B3 CASIN3 F4 E2 DIN5 F6 J1 DREF3 F7 L4 A2 F11 B4 CASIN6 F7 E3 DIN6 F7 J2 DREF1 F5 L5 DCONT7 F8 B5 CASIN9 F3 E9 DOUT0 VCC/2 J5 A1 F10 L6 DCONT1 F5 B6 CASOUT2 VCC/2 E10 DOUT1 VCC/2 J6 DCONT5 F6 L7 DCONT3 F7 B7 CASOUT1 VCC/2 E11 DOUT2 VCC/2 J7 DCONT4 F8 L8 DCONT0 F4 B8 CASOUT4 VCC/2 F1 DREF6 F7 J10 GND GND L9 AUXOUT8 VCC/2 B9 CASOUT6 VCC/2 F2 DIN3 F4 J11 AUXOUT2 VCC/2 L10 AUXOUT7 VCC/2 B10 CASOUT7 VCC/2 F3 DIN2 F3 K1 DREF2 F6 L11 AUXOUT5 VCC/2 NOTES: 10. V CC/2 (2.7V ±10%) used for outputs only. 11. 47kΩ (±20%) resistor connected to all pins except VCC and GND. 12. V CC = 5.5 ± 0.5V. 13. 0.1µF (min) capacitor between V CC and GND per position. 14. FO = 100kHz ± 10%, F1 = F0/2, F2 = F1/2 . . . F11 = F10/2, 40 - 60% Duty Cycle. 15. Input Voltage Limits: VIL = 0.8V max, VIH = 4.5 ± 10%. Metal Topology DIE DIMENSIONS: 254 mils x 214 mils x 19 ± 1 mil METALLIZATION: Type: Si - Al or Si-Al-Cu Thickness: 8kÅ GLASSIVATION: Type: Nitrox Thickness: 10kÅ WORST CASE CURRENT DENSITY: 0.96 x 105 A/cm 2 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 9-9