ISL9221 ® Data Sheet April 3, 2008 Dual Input Lithium Ion Battery Charger with OVP USB Bypass and 10mA LDO The ISL9221 Lithium Ion charging IC is designed to meet the charging requirements of most of today’s handheld devices. The IC provides two inputs for either USB connection where the current is limited by the USB standard or for powering/charging from a power adapter. If the voltage at either VUSB or VDC pin is within the safe allowable range, the PPR pin is pulled low indicating to the system processor that external power is available. Charging can be enabled/disabled by controlling the state of the EN pin. While charging, the CHG pin is pulled low indicating the battery is being charged. FN6541.1 Features • Lithium Ion/Polymer battery charging • Dual input - USB host or car/wall adapter • Input voltage withstanding up to 28V • 5.4V overvoltage protection on VUSB inputs • Charging current up to 1.2A • 4.9V/10mA linear regulator with input OVP • Current limit on bypass path • Programmable end-of-charge current • Programmable charging current • Programmable USB current limit The battery is charged to 4.2V with only a 1% error across the temperature range. USB charge current, Adapter charge current and charge termination currents can be programmed via external resistors. The ISL9221 adds an additional feature in providing a limited amount of current to system architecture while protecting the system from destructively high voltage. • Charging and power present indicator pins • Charge enable pin • Reverse current protection • Pb-free (RoHS compliant) Applications The device contains Thermal regulation and protection to provide additional safety features of this device. When the temperature exceeds +125°C, the current will fold back to reduce and control the die temperature. • Smart Handheld Devices Ordering Information • Handheld Test Equipment PART NUMBER (Note) ISL9221IRZ PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # 9221 -40°C to +85°C 12 Ld 4x3 DFN L12.4x3 ISL9221IRZ-T* 9221 -40°C to +85°C 12 Ld 4x3 DFN L12.4x3 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 • Cell Phones, PDAs, MP3 Players • Digital Still Cameras Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages” Pinout ISL9221 (12 LD DFN) TOP VIEW VDC 1 VUSB 2 11 BAT PPR 3 10 USB_BYP CHG 4 9 IVDC EN 5 8 GND IMIN 6 7 IUSB 12 VDC_LDO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL9221 Absolute Maximum Ratings Thermal Information Supply Voltage (VDC, VUSB). . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V Other Input Voltage (EN, IMIN, IUSB, IVDC) . . . . . . . . . . -0.3V to 7V Open Drain Pull Voltage (PPR, CHG) . . . . . . . . . . . . . . .-0.3V to 7V Other Pin Voltage(VDC_LDO, USB_BYP, VBAT) . . . . . .-0.3V to 7V Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 4x3 DFN Package . . . . . . . . . . . . . . . . . . . . 41 3.5 Maximum Junction Temperature (Plastic Package)+ . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VUSB) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.3V Supply Voltage (VDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 6.7V Typical Adapter Charge Current . . . . . . . . . . . . . . . . 100mA to 1.2A Typical USB Charge Current . . . . . . . . . . . . . . . . 46.5mA to 465mA Typical USB Bypass Current . . . . . . . . . . . . . . . . . . . 0mA to 200mA Typical LDO Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 10mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 3. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. Electrical Specifications Typical Values are tested at USB = VDC = 5V and ambient temperature at +25°C, unless otherwise noted. All maximum and minimum values are guaranteed under the recommended operating conditions. MIN (Note 3) TYP Rising VUSB/VDC Threshold 3.4 3.9 4.2 V Falling VUSB/VDC Threshold 3.2 3.7 4.0 V - 150 250 mV 20 80 - mV EN = HIGH or both inputs are floating - 0.05 0.5 µA PARAMETERS SYMBOL CONDITIONS MAX (Note 3) UNITS CHARGER POWER-ON THRESHOLDS INPUT VOLTAGE OFFSET Rising Edge of VDC or VUSB Relative to VBAT VOSHC Falling Edge of VDC or VUSB Relative to VBAT VOSLC VBAT = 4.0V, use CHG pin to indicate the comparator output STANDBY CURRENT BAT Pin Sink Current ISTANDBY VDC Pin Supply Current IVDC EN = HIGH, ILDO = 0 - 365 420 µA VUSB Pin Supply Current IVUSB EN = HIGH, USB_BYP disconnected - 300 360 µA EN = LOW, ILDO = 0, USB_BYP disconnected - 0.63 0.85 mA Load = 10mA 4.158 4.2 4.242 V Load = 10mA (TJ = +25°C) 4.174 4.2 4.226 V VDC/USB Pin Supply Current VOLTAGE REGULATION Output Voltage VBAT VDC Linear ON-resistance VBAT =3.8V, IVDC = 0.3A, (TJ = +25°C) - 600 - mΩ USB Linear ON-resistance VBAT =3.8V, IUSB = 0.3A, (TJ = +25°C) - 600 - mΩ 1.19 1.22 1.25 V CHARGE CURRENT IVDC Pin Output Voltage VIVDC VBAT = 3.8V VDC Constant Current Accuracy IVDC_CHRG RIVDC = 12.4kΩ, VBAT = 2.7V to 3.8V 500 550 580 mA VDC Trickle Charge Current IVDC_TRKL 16 18 20 % 2 RIVDC = 12.4kΩ, VBAT = 2.2V, given as a % of the IVDC_CHARGE FN6541.1 April 3, 2008 ISL9221 Electrical Specifications Typical Values are tested at USB = VDC = 5V and ambient temperature at +25°C, unless otherwise noted. All maximum and minimum values are guaranteed under the recommended operating conditions. (Continued) PARAMETERS SYMBOL IUSB Pin Output Voltage VIUSB CONDITIONS VBAT = 3.8V MIN (Note 3) TYP MAX (Note 3) UNITS 1.19 1.22 1.25 V VUSB Constant Current Accuracy IUSB_CHRG RIUSB = 29.4kΩ,VBAT = 2.7V to 3.8V 211 232 246 mA VUSB Trickle Charge Current IUSB_TRKL 16 18 20 % - IUSB_CHRG - % 46.5 55 63.5 mA VMIN 2.5 2.6 2.7 V VRCH 3.8 3.9 4.0 V VDC Overvoltage Level OVP 6.7 6.8 6.9 V VDC Overvoltage Hysteresis HOVP - 90 130 mV - 1 - µs 5.3 5.4 5.5 V VUSB Overvoltage Hysteresis - 60 90 mV VUSB Overvoltage Protection Delay - 1 - µs - 400 600 mA Measured at 200mA, 4.3V < VDC < 5.3V - 1.3 2.0 Ω IOUT = 150mA, VUSB > 4.3V - 200 - mV TFOLD - 125 - °C EN Pin Logic Input HIGH VIH 1.3 - - V EN Pin Logic Input LOW VIL - - 0.4 V 350 600 850 kΩ 10 - - mA - 4.94 - V Initial accuracy, ILDO = 10mA; TJ = +25°C -2.0 - +2.0 % Line/Load, ILDO = 10µA to 10mA, VDC = VLDO + 0.5V to 6.5V; TJ = -40°C to +125°C -2.8 - +2.8 % - 30 50 mV 12 - - mA RIUSB = 29.4kΩ, VBAT = 2.2V and if IUSB_CHRG ≤ IVDC_TRKL, then given as a % of the IUSB_CHRG If IUSB_CHRG ≤ IVDC_TRKL DC and USB End-of-Charge Threshold IMIN RMIN = 10kΩ PRECONDITIONING CHARGE THRESHOLD Preconditioning Charge Threshold Voltage RECHARGE THRESHOLD Recharge Threshold Voltage PROTECTIONS VDC Overvoltage Protection Delay VUSB Overvoltage Level Short Circuit (USB_BYP) IOCP BYPASS FETS Resistance VUSB to USB_BYP USB_ rDS(ON) Drop Out VUSB to USB_BYP VUSBDO INTERNAL TEMPERATURE MONITORING Current Fold Back Threshold LOGIC INPUT AND OUTPUT EN Pin Internal Pull-down Resistance CHG and PRR Sink Current Pin Voltage = 0.8V LINEAR REGULATOR Output Voltage VLDO Voltage Regulation Accuracy VREG Dropout (VDC to VLDO) VDO ILDO = 10mA, VLDO= 4.9V, VDC > VLDO+0.5V Current Limit ILIMIT For ILDO = 10mA option, VDC = 5.5V 3 FN6541.1 April 3, 2008 ISL9221 Pin Assignments NAME PIN TYPE DESCRIPTION VDC 1 AI Input pin from car adapter or AC/DC adapter VUSB 2 AI Input pin from USB host device VDC_LDO 12 AO Output pin of Linear Regulator USB_BYP 10 AO Output pin from USB bypass circuitry IVDC 9 AI Battery current setting pin for adapter power IUSB 7 AI Current setting pin for USB power IMIN 6 AI End-of-charge current setting pin BAT 11 AO Output pin to battery EN 5 DI Active low charge enable pin PPR 3 OD Active low power present indicator pin CHG 4 OD Active low charging indication pin GND 8 G Ground pad TABLE 1. TYPE CHART SYMBOL DESCRIPTION A Analog Pin D Digital Pin I Input Pin O Output Pin OD Open-Drain G The maximum current drawn from the VUSB pin is the combination of the load at USB_BYP and the programmed USB charging current. A 1µF bypass capacitor is recommended on the VUSB pin. Higher values of bypass capacitance can be utilized but the designer should refer to the maximum allowed bus capacitance per USB application standard. When using ceramic capacitors, a small resistance value, such as 1Ω in series with the capacitor, is recommended to reduce voltage overshoot. Ground IVDC Functional Pin Descriptions VDC Adapter input pin. This pin is usually connected to adapter power. The maximum input voltage is 28V. The charge current from this pin is programmable up to 1.2A by selection of the resistor on the IVDC pin. When this pin is connected to a power source, no charge current is drawn from the USB pin. A 1µF or larger value ceramic capacitor is recommended for decoupling. Adapter charging current setting pin. A resistor on this pin sets the maximum charging current to be delivered to the BAT pin. The maximum current, however, may be reduced by the adapter’s current limit or by the power dissipation within the charging IC. IUSB USB charge current pin. This pin is connected internally to a current source for setting the programmed charging current delivered to the BAT pin. VDC_LDO BAT Linear regulator output. A 0.1µF to 1µF ceramic capacitor from this pin to ground is required. Charger IC output pin. This pin is to be connected to the positive (+) terminal of the battery. The charging IC monitors this pin to determine the charge state of the battery. USB_BYP USB input bypass pin. This is an output from the low current bypass FET connected to the USB input pin. The USB_BYP can be connected to the system to provide safe, voltage-limited power from the USB input pin. A 1µF bypass capacitor from the BAT pin to ground is recommended. The charging IC relies on the battery to help stabilize the circuitry and it is not recommended to operate the charger IC without a battery connected to this pin. EN VUSB VUSB Input pin. This pin is usually connected to a USB port power connector. The maximum input voltage is 28V. However, the internal OVP circuitry will trip at 5.4V. 4 Enable charging pin. This pin is a logic level input to control charging by the system processor. An external pull-up resistor should be connected to processor’s I/O power supply. FN6541.1 April 3, 2008 ISL9221 CHG The USB_BYP and VDC_LDO stay on regardless of the state of this pin. This ensures that the processor can be powered up when an external source is connected to the VDC or VUSB input pin. Charge indication pin. This open-drain pin is pulled low to indicate when the battery is being charged. If connected to the processor, a pull-up resistor should be connected to the processors I/O supply. PPR The CHG pin can also be used to drive an LED to indicate to the user the battery is being charged. Power presence indication pin. This pin is used to notify the system processor or enable the power circuitry when a source is connected. The pin is an open drain output pin, which pulls low when a valid voltage (above POR) is present at either the VDC or VUSB pin. The PPR pin is held low regardless of the state of the EN pin. If connected to the processor, a pull-up resistor should be connected to the processors I/O supply. If connected to power circuitry, a pull-up should be tied to the appropriate bypass supply. GND Ground pin. This provides the ground path for all internal circuits. I/O_VDD I/O_VDD Typical Application OFF LDO OUTPUT ON CHG PPR VDC_LDO VDC EN VDC INPUT TO MCU TO BATTERY BAT IVDC GND RIVDC IUSB RIUSB IMIN VUSB USB_BYP ISL9221 USB INPUT RIMIN FIGURE 1. APPLICATIONS CIRCUIT USB_BYP 5 FN6541.1 April 3, 2008 ISL9221 Block Diagram LDO LDO BYPASS USB_BYP 4.35V TO 6.5V VDC BAT + VMIN + VRCH 4.35V TO 5.25V VUSB 2.6V THERM 3.9V + CC/CV - 4.2V 6.8VOVP 150/80mV 5.4VOVP VOS VOLTAGE/CURRENT CONTROLLER VOS + + VDC + VUSB EN IUSB + - I/O CNTL PPR + IDC CHG IMIN 1.22V + GND FIGURE 1. SIMPLIFIED BLOCK DIAGRAM USB Charge Current When the EN pin is pulled low and a valid USB voltage is present at the USB pin, the IC will charge the battery at a rate dependent on the IUSB setting. The charge current maybe reduced by the USB source if it is set to a value higher than the current limit of the USB source. Equation 1 for setting the IUSB current is as follows: 6820 IUSB = ------------------ ( mA ) R IUSB (EQ. 1) Where RIUSB is in kΩ. The current set by the IUSB pin for charging the battery is in addition to current drawn by the load on the USB_BYP. The system designer should consider the maximum expected USB_BYP load current when selecting the USB charging current so as not to exceed the current limits set by the USB standards. Typically at room temperature, the rDS(ON) across the charge path, VUSB to BAT is 600mΩ. If the entire USB current limit of 465mA is being supplied to the battery, the drop across the charging FET could be more than 300mV. Thus, the voltage at the USB pin needs to be maintained above ~4.5V. 6 Otherwise, the period to charge the battery may be prolonged. Adapter Charge Current When the EN pin is pulled low and a valid adapter voltage is present at the VDC pin, the IC will charge the battery at a rate dependent on the IVDC setting; the charge on the battery and the source connected to the VDC pin. An example of this is while the IVDC is set for 1000mA, the adapter supply may only provide 800mA and the battery is limited to the 800mA. Typically the rDS(ON) across the charge path, VDC to BAT is 600mΩ. At a 1.0A charging rate, 600mV is dropped across the charge path. Thus, the voltage at the VDC pin needs to be maintained above ~4.80V. Otherwise the period to charge the battery may be prolonged. 6820 IVDC = ------------------ ( mA ) R IVDC (EQ. 2) Where RIVDC is in kΩ. It is recommended that the maximum charging current be programmed to between 100mA and 1200mA. FN6541.1 April 3, 2008 ISL9221 Floating Charge Voltage Power-Good Condition The floating voltage during the constant voltage phase is 4.2V. The floating voltage has 1% accuracy over the ambient temperature range of -40°C to +85°C. Even if there is a power present at one of the power input pins, the charger will not deliver power to the battery for charging if three of the conditions below are not met: Trickle Charge Current • VDC or VUSB > VPOR When the battery voltage is below 2.7V (VBATmin), the charger operates in trickle/preconditioning mode, where the charge current is typically 18% of the programmed current set by RIVDC. • VDC or VUSB - VBAT > VOS End-of-Charge Indication When an EOC condition (charge current falls below IMIN during constant-voltage charging) is encountered, the internal open-drain MOSFET at the CHG pin turn-off. IMIN threshold is programmable by the resistor RIMIN at the IMIN pin for both adapter and USB inputs. If the programmed fast charge current is less than IMIN, then after the de-bounce period for VBAT = VBATmax expires, EOC occurs. Once EOC is reached, the status is latched and can be reset by one of the following conditions: • VDC or VUSB < VOVP Where VPOR is the power on reset voltage and VOS is the offset voltage of the input-to-output comparator. All of these voltages have hysteresis, as given in the “Electrical Specifications” table on page 2. POR_DLY 6.8VOVP OVP- HOVP POR VDC 5.4V OVP OVP- HOVP POR VUSB • The part is disabled and re-enabled • The selected input source is removed and reapplied • The BAT pin voltage falls below the recharge threshold (~3.9V) PPR ENABLE ACTIVE EN IMIN IMIN sets the charge termination current for EOC (End-ofCharge). IMIN can be calculated by Equation 3: 550 IMIN = ---------------- ( mA ) R IMIN CHG ILDO + ICHG (EQ. 3) IVDC ILDO Where RIMIN is in kΩ. IMIN is applicable for both adapter and USB charging. Power Presence Indication When either the Adapter power or USB is above the POR threshold, the PPR internal Open-Drain MOSFET pulls the pin low indicating that there is a valid source on one of the power input pins. If only one source is connected and it is above VOVP or both sources are connected and both exceed VOVP, the PPR will be released (HIGH) indicating that the voltage at the pin(s) is invalid. If one input is valid while the other isn’t, the PPR pin will be pulled low. Thermal Fold Back (Thermaguard™) The thermal fold back function reduces the charge current when the internal temperature reaches the thermal foldback threshold, which is typically +125°C. This protects the charger from excessive thermal stress at high input voltages. 7 IUSB_BYP + ICHRG IUSB_BYP IVUSB VBAT USB_BYP 4.94V VDC_LDO 0V FIGURE 2. . CHARGING PROFILE Input Bypass Capacitors Due to the wall or car power adapter power lead inductance, the VDC input capacitor type must be properly selected to prevent high voltage transient during a hot-plug event. This is also true for the USB input capacitor. A tantalum capacitor is a good choice for its high ESR, providing damping to the voltage transient. Multi-layer ceramic capacitors, however FN6541.1 April 3, 2008 ISL9221 have a very low ESR and hence when chosen as input capacitors, a 1Ω series resistor must be placed between the capacitor and ground, as shown in the Typical Applications Section, to provide adequate damping. CHG CHARGE DISABLE EN Fault Summary If VDC is greater than 6.8V, then the VDC_LDO and charging FETs are turned off until VDC < VOVP - HOVP (Where HOVP is the OVP hysteresis). PPR will be asserted high (off), unless VUSB is valid. If VUSB is greater than 5.4V, then the VUSB bypass and charging FETs are turned off until VUSB < VOVP - HOVP. PPR will be asserted high (off), unless VDC is valid. CHARGE ENABLE VMAX VRCH If the load on VUSB_BYP exceeds 400mA, the FET will be current limited to protect the load and the IC. IMAX If VUSB_BYP > VUSB, USB Bypass FET is turned off. VMIN State Diagram VBAT 0.18*IMAX IMIN ICHG EOC FIGURE 3. TIMING DIAGRAM 8 The state diagram for the charger functions is shown in Figure 4. The diagram starts with the Power-off state. When at least one input voltage rises above the POR threshold, the charger resets itself. If both input voltages are above the POR threshold, the charger selects the VDC input as the power source. Then if the EN pin is at a logic HIGH voltage, the charger will stay in the disabled state. If the EN pin is LOW or is brought LOW charging begins. Any time the EN pin is asserted high, the charger returns to the disabled state. When the EOC condition is reached, the CHG will turn to a logic HIGH to indicate a charge complete status but charging will continue. FN6541.1 April 3, 2008 ISL9221 VDC BAD, VUSB GOOD VDC = GOOD, IF VPOR < VDC < 6.8V VUSB = GOOD, IF VPOR < VUSB < 5.4V POWER OFF CHARGER: OFF PPR: OFF CHG: OFF LDO: OFF BYP: OFF VOVP < VDC, VUSB BAD VDC BAD, VOVP < VUSB VDC GOOD, VUSB GOOD EN = HI VDC BAD, VUSB GOOD EN = HI NOT ENABLED, EN = HI POR VDC INPUT CHARGER: OFF PPR: ON CHG: OFF LDO: ON BYP: ON POR USB INPUT ONLY CHARGER: OFF PPR: ON CHG: OFF LDO: OFF BYP: ON VDC GOOD, VOVP < VUSB VBAT < VMIN, EN = LOW VMIN < VBAT < VMAX, EN = LOW POR VDC INPUT CHARGER: OFF PPR: ON CHG: OFF LDO: ON BYP: OFF NOT ENABLED, EN = HI VOVP < VDC, VUSB GOOD TRICKLE CHARGE CHARGER: ON PPR: ON CHG: ON LDO: ON (IF VDC GOOD) BYP: ON (IF VUSB GOOD) OVP USB INPUT ONLY CHARGER: OFF PPR: OFF CHG: OFF LDO: OFF BYP: OFF VDC GOOD, VUSB BAD EN = HI OVP VDC INPUT SELECTED CHARGER: OFF PPR: OFF CHG: OFF LDO: OFF BYP: OFF VMIN < VBAT < VMAX, EN = LOW VMIN < VBAT VDC BAD FAST CHARGE @ IUSB CHARGER: ON PPR: ON CHG: ON LDO: OFF BYP: ON FAST CHARGE @ IVDC CHARGER: ON PPR: ON CHG: ON LDO: ON BYP: ON (IF VUSB GOOD) VDC GOOD RECHARGE CONDITION MET, VBAT < VRCH VMAX = VBAT, EN = LOW VMAX = VBAT, EN = HI CHARGE COMPLETE CHARGER: ON PPR: ON CHG: OFF LDO: ON (IF VDC GOOD) BYP: ON (IF VUSB GOOD) VMAX = VBAT, EN = LOW VMAX = VBAT, EN = HI FIGURE 4. STATE DIAGRAM FOR CHARGER FUNCTIONS 9 FN6541.1 April 3, 2008 ISL9221 Logic Function State Table VDC INPUT VIN < VPOR PGOOD, VPOR < VDC < VOVP USB INPUT VIN > VOVP VIN < VPOR X X X X X BAT CHARGING VDC_LDO OUTPUT USB_BYP Hi Z No, Reverse Blocked No, Reverse Blocked No, Reverse Blocked Low Low Yes, USB Charging No, reverse blocked Yes Low Low Low Yes, VDC Charging Yes No, Reverse Blocked Low Low Low Yes, VDC Charging Yes Yes High (Disables Charging) Low Hi Z No, Reverse Blocked Yes No, Reverse Blocked Yes High (Disables Charging) Low Hi Z No, Reverse Blocked No, reverse blocked Yes Yes High (Disables Charging) Low Hi Z No, Reverse Blocked Yes Yes VIN > VOVP EN PPR CHG X Don’t Care Hi Z Low Yes Yes X Yes X Yes Yes X PGOOD, VPOR < VUSB < VOVP X X Yes X NOTES: 4. ”X” denotes that the input is either less than VPOR or greater than VOVP 5. VDC_VOVP is a nominal 6.8V 6. VUSB_VOVP is a nominal 5.4V 10 FN6541.1 April 3, 2008 ISL9221 Dual Flat No-Lead Plastic Package (DFN) L12.4x3 12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-229-VGED-4 ISSUE C) 2X 0.15 C A A D MILLIMETERS 2X 0.15 C B SYMBOL 0.80 A1 - A3 E 6 INDEX AREA b D2 B // A SIDE VIEW C SEATING PLANE 0.10 0.08 A3 7 8 - - 0.05 - 0.23 0.30 5,8 4.00 BSC 3.15 3.30 3.40 7,8 3.00 BSC 1.55 e 1.70 1.80 7,8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 12 2 Nd 6 3 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 2 4. All dimensions are in millimeters. Angles are in degrees. NX k (DATUM A) 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. E2/2 NX L N N-1 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX b e 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 5 (Nd-1)Xe REF. BOTTOM VIEW NX (b) C NOTES 1.00 NOTES: D2/2 1 C MAX 0.90 Rev. 1 2/05 D2 (DATUM B) 8 0.18 E E2 NOMINAL 0.20 REF D TOP VIEW 6 INDEX AREA MIN A 0.10 M C A B CL (A1) L 5 e SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6541.1 April 3, 2008