LATTICE ISPGDX160VA

ispGDX 160V/VA
TM
In-System Programmable
3.3V Generic Digital Crosspoint
TM
Features
Functional Block Diagram
ISP
Control
I/O Pins A
I/O Pins D
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.3V Core Power Supply
— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*
— 250MHz Maximum Clock Frequency*
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)*
— Low-Power: 16.5mA Quiescent Icc*
— 24mA IOL Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability*
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
I/O
Cells
Boundary
Scan
Control
Global Routing
Pool
(GRP)
I/O
Cells
I/O Pins C
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
I/O Pins B
Description
• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (four) or
Programmable Clocks/Clock Enables from I/O Pins
(40)
— Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
The ispGDXV/VA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface requirements including:
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.5ns and clock-to-output delays of
3.5ns.
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
Simulation
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
* “VA” Version Only
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
gdx160va_04
1
July 2000
Specifications ispGDX160V/VA
Description (Continued)
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock
(CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals
is programmable for each I/O cell. The MUX0 and MUX1
inputs control a fast 4:1 MUX, allowing dynamic selection
of up to four signal sources for a given output. A wider
16:1 MUX can be implemented with the MUX expander
feature of each I/O and a propagation delay increase of
2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs
can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of
I/O pins. CLKEN disables the register clock when
CLKEN = 0.
In addition, there are no pin-to-pin routing constraints for
1:1 or 1:n signal routing. That is, any I/O pin configured
as an input can drive one or more I/O pins configured as
outputs.
Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDXV devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
into the device using non-volatile E2CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.
All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private commands.
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
12mA source current (at JEDEC LVTTL levels) and can
be tied together in parallel for greater drive. On the
ispGDXVA, each I/O pin is individually programmable for
3.3V or 2.5V output levels as described later. Programmable output slew rate control can be defined
independently for each I/O pin to reduce overall ground
bounce and switching noise.
The ispGDXV I/Os are designed to withstand “live insertion” system environments. The I/O buffers are disabled
during power-up and power-down cycles. When designing for “live insertion,” absolute maximum rating conditions
for the Vcc and I/O pins must still be met.
Table 1. ispGDXV Family Members
ispGDXV/VA Device
ispGDX80VA
ispGDX160V/VA ispGDX240VA
I/O Pins
80
160
240
I/O-OE Inputs*
20
40
60
I/O-CLK / CLKEN Inputs*
20
40
60
I/O-MUXsel1 Inputs*
I/O-MUXsel2 Inputs*
20
20
40
40
60
60
Dedicated Clock Pins**
2
4
4
EPEN
1
1
1
TOE
1
4
1
1
4
1
1
4
1
BSCAN Interface
RESET
Pin Count/Package
100-Pin TQFP
208-Pin PQFP 388-Ball fpBGA
208-Ball fpBGA
272-Ball BGA
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to
25% of the I/Os.
** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and
CLKEN3 respectively in all devices.
2
Specifications ispGDX160V/VA
Architecture
The various I/O pin sets are also shown in the block
diagram below. The A, B, C, and D I/O pins are grouped
together with one group per side.
The ispGDXV/VA architecture is different from traditional
PLD architectures, in keeping with its unique application
focus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing
Pool (GRP). Unlike ispLSI devices, there are no programmable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines as well as a 4x4 crossbar switch controlled by software for increased routing flexiability (Figure
1). The four data inputs to the MUX (called M0, M1, M2,
and M3) come from I/O signals in the GRP and/or
adjacent I/O cells. Each MUX data input can access one
quarter of the total I/Os. For example, in a 160 I/O
ispGDXV, each data input can connect to one of 40 I/O
pins. MUX0 and MUX1 can be driven by designated I/O
pins called MUXsel1 and MUXsel2. Each MUXsel input
covers 25% of the total I/O pins (e.g. 40 out of 160). MUX0
and MUX1 can be driven from either MUXsel1 or MUXsel2.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.
Figure 1. ispGDXV/VA I/O Cell and GRP Detail (160 I/O Device)
Logic “0” Logic “1”
160 I/O Inputs
I/OCell 0
I/O Cell 159
I/O Cell 1
I/O Cell 158
••
•
E2CMOS
Programmable
Interconnect
To 2 Adjacent
I/O Cells above
From MUX Outputs
of 2 Adjacent I/O Cells
4-to-1 MUX
N+2
I/O Group A
I/O Group B
I/O Group C
I/O Group D
N+1
N-1
•
•
•
•
•
•
Register
or Latch
M0
M1
M2
M3
MUX0 MUX1
4x4
Crossbar
Switch
N-2
From MUX Outputs
of 2 Adjacent I/O Cells
Prog.
Prog.
Pull-up Bus Hold
Latch
(VCCIO)
Bypass Option
A
B
D
Q
CLK
To 2 Adjacent
I/O Cells below
CLK_EN Reset
I/O
Pin
C
R
Prog. Open Drain
2.5V/3.3V Output
Prog. Slew Rate
Boundary
Scan Cell
I/O Cell N
••
•
I/O Cell 78
I/O Cell 81
••••••
I/O Cell 79
80 I/O Cells
I/O Cell 80
80 I/O Cells
160 Input GRP
Inputs Vertical
Outputs Horizontal
Global
Y0-Y3
Reset
Global
Clocks /
Clock_Enables
ispGDXV/VA architecture enhancements over ispGDX (5V)
3
Specifications ispGDX160V/VA
allow adjacent I/O cell outputs to be directly connected
without passing through the global routing pool. The
relationship between the [N+i] adjacent cells and A, B, C
and D inputs will vary depending on where the I/O cell is
located on the physical die. The I/O cells can be grouped
into “normal” and “reflected” I/O cells or I/O “hemispheres.” These are defined as:
I/O MUX Operation
MUX0
Data Input Selected
0
0
M0
0
1
M1
1
1
M2
1
0
M3
Device
Flexible mapping of MUXselx to MUXx allows the user to
change the MUX select assignment after the ispGDXV/
VA device has been soldered to the board. Figure 1
shows that the I/O cell can accept (by programming the
appropriate fuses) inputs from the MUX outputs of four
adjacent I/O cells, two above and two below. This enables cascading of the MUXes to enable wider (up to
16:1) MUX implementations.
Normal I/O Cells
Reflected I/O Cells
ispGDX80VA
B9-B0, A19-A0,
D19-D10
B10-B19, C0-C19,
D0-D9
ispGDX160V/VA
B19-B0, A39-A0,
D39-D20
B20-B39, C0-C39,
D0-D19
ispGDX240VA
B29-B0, A59-A0,
D59-D30
B30-B59, C0-C59,
D0-D29
Table 2 shows the relationship between adjacent I/O
cells as well as their relationship to direct MUX inputs.
Note that the MUX expansion is circular and that I/O cell
B20, for example, draws on I/Os B19 and B18, as well as
B21 and B22, even though they are in different hemispheres of the physical die. Table 2 shows some typical
cases and all boundary cases. All other cells can be
extrapolated from the pattern shown in the table.
The I/O cell also includes a programmable flow-through
latch or register that can be placed in the input or output
path and bypassed for combinatorial outputs. As shown
in Figure 1, when the input control MUX of the register/
latch selects the “A” path, the register/latch gets its inputs
from the 4:1 MUX and drives the I/O output. When
selecting the “B” path, the register/latch is directly driven
by the I/O input while its output feeds the GRP. The
programmable polarity Clock to the latch or register can
be connected to any I/O in the I/O-CLK/CLKEN set (onequarter of total I/Os) or to one of the dedicated clock input
pins (Yx). The programmable polarity Clock Enable input
to the register can be programmed to connect to any of
the I/O-CLK/CLKEN input pin set or to the global clock
enable inputs (CLKENx). Use of the dedicated clock
inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output
mode may be implemented by a dedicated architecture
bit and bypass MUX. I/O cell output polarity can be
programmed as active high or active low.
Figure 2. I/O Hemisphere Configuration of
ispGDX160V/VA
D20
D19
D0
B0
B19
B20
B39
C0
A39
The ispGDXV/VA allows adjacent I/O cell MUXes to be
cascaded to form wider input MUXes (up to 16 x 1)
without incurring an additional full Tpd penalty. However,
there are certain dependencies on the locality of the
adjacent MUXes when used along with direct MUX
inputs.
D39
C39
MUX Expander Using Adjacent I/O Cells
I/O cell 159
A0
I/O cell index increases in this direction
I/O cell 0
I/O cell 79
I/O cell index increases in this direction
MUX1
I/O cell 80
Adjacent I/O Cells
Direct and Expander Input Routing
Expansion inputs MUXOUT[n-2], MUXOUT[n-1],
MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable
for each I/O cell MUX. These expansion inputs share the
same path as the standard A, B, C and D MUX inputs, and
Table 2 also illustrates the routing of MUX direct inputs
that are accessible when using adjacent I/O cells as
inputs. Take I/O cell D23 as an example, which is also
shown in Figure 3.
4
Specifications ispGDX160V/VA
Figure 3. Adjacent I/O Cells vs. Direct Input Path for
ispGDX160V/VA, I/O D23
Special Features
Slew Rate Control
ispGDX160V/VA I/O Cell
All output buffers contain a programmable slew rate
control that provides software-selectable slew rate options.
I/O Group A
D21 MUX Out
S1 S0
I/O Group B
.m0
4x4
Crossbar
Switch
D22 MUX Out
I/O Group C
.m1
.m2
Open Drain Control
D23
All output buffers provide a programmable Open-Drain
option which allows the user to drive system level reset,
interrupt and enable/disable lines directly without the
need for an off-chip Open-Drain or Open-Collector buffer.
Wire-OR logic functions can be performed at the printed
circuit board level.
.m3
D24 MUX Out
I/O Group D
D25 MUX Out
It can be seen from Figure 3 that if the D21 adjacent I/O
cell is used, the I/O group “A” input is no longer available
as a direct MUX input.
Pull-up Resistor
All pins have a programmable active pull-up. A typical
resistor value for the pull-up ranges from 50kΩ to 80kΩ.
The ispGDXV/VA can implement MUXes up to 16 bits
wide in a single level of logic, but care must be taken
when combining adjacent I/O cell outputs with direct
MUX inputs. Any particular combination of adjacent I/O
cells as MUX inputs will dictate what I/O groups (A, B, C
or D) can be routed to the remaining inputs. By properly
choosing the adjacent I/O cells, all of the MUX inputs can
be utilized.
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds
the previously driven state when all drivers connected to
the pin (including the pin's output driver as well as any
other devices connected to the pin by external bus) are
tristated.
Table 2. Adjacent I/O Cells (Mapping of
ispGDX160V/VA)
ispGDX160VA New Features
Unique to the ispGDX160VA are user-programmable
I/Os supporting either 3.3V or 2.5V output voltage level
options. The ispGDX160VA uses a VCCIO pin to provide
the 2.5V reference voltage when used. The ispGDX160VA
VCCIO pin occupies the same location as VCC on the
ispGDX160V, allowing drop-in replacement. The
ispGDX160VA offers improved performance by reducing
fanout delays and has PCI compatible drive capability.
Data A/ Data B/ Data C/ Data D/
MUXOUT MUXOUT MUXOUT MUXOUT
Reflected
I/O Cells
Normal
I/O Cells
B20
B22
B21
B19
B18
B21
B22
B23
B24
B22
B23
B20
B21
B19
B20
B23
B25
B24
B22
B21
D16
D18
D17
D15
D14
D17
D19
D18
D16
D15
D18
D20
D19
D17
D16
D19
D21
D20
D18
D17
D20
D18
D19
D21
D22
D21
D19
D20
D22
D23
D22
D20
D21
D23
D24
D23
D21
D22
D24
D25
B16
B14
B15
B17
B18
B17
B15
B16
B18
B19
B18
B19
B16
B17
B18
B19
B20
B20
B21
B17
Only the ispGDX160VA is available in the fastest (3.5ns)
Commercial speed grade and in -5,-7, and -9ns Industrial
grades in all packages.
The ispGDX160VA has a device ID different from the
ispGDX160V requiring that the latest Lattice download
software be used for programming and verification. Although the ispGDX160VA and ispGDX160V are
functionally equivalent, they are not 100% JEDEC compatible. All design files must be recompiled targeting the
ispGDX160VA.
5
Specifications ispGDX160V/VA
Applications
Programmable Switch Replacement (PSR)
The ispGDXV/VA Family architecture has been developed to deliver an in-system programmable signal routing
solution with high speed and high flexibility. The devices
are targeted for three similar but distinct classes of endsystem applications:
Includes solid-state replacement and integration of mechanical DIP Switch and jumper functions. Through
in-system programming, pins of the ispGDXV/VA devices can be driven to HIGH or LOW logic levels to
emulate the traditional device outputs. PSR functions do
not require any input pin connections.
Programmable, Random Signal
Interconnect (PRSI)
These applications actually require somewhat different
silicon features. PRSI functions require that the device
support arbitrary signal routing on-chip between any two
pins with no routing restrictions. The routing connections
are static (determined at programming time) and each
input-to-output path operates independently. As a result,
there is little need for dynamic signal controls (OE,
clocks, etc.). Because the ispGDXV/VA device will interface with control logic outputs from other components
(such as ispLSI or ispMACH) on the board (which frequently change late in the design process as control logic
is finalized), there must be no restrictions on pin-to-pin
signal routing for this type of application.
This class includes PCB-level programmable signal routing and may be used to provide arbitrary signal swapping
between chips. It opens up the possibilities of programmable system hardware. It is characterized by the need
to provide a large number of 1:1 pin connections which
are statically configured, i.e., the pin-to-pin paths do not
need to change dynamically in response to control inputs.
Programmable Data Path (PDP)
This application area includes system data path transceiver, MUX and latch functions. With today’s 32- and
64-bit microprocessor buses, but standard data path glue
components still relegated primarily to eight bits, PCBs
are frequently crammed with a dozen or more data path
glue chips that use valuable real estate. Many of these
applications consist of “on-board” bus and memory interfaces that do not require the very high drive of standard
glue functions but can benefit from higher integration.
Therefore, there is a need for a flexible means to integrate these on-board data path functions in an analogous
way to programmable logic’s solution to control logic
integration. Lattice’s CPLDs make an ideal control logic
complement to the ispGDXV/VA in-system programmable data path devices as shown below.
PDP functions, on the other hand, require the ability to
dynamically switch signal routing (MUXing) as well as
latch and tri-state output signals. As a result, the programmable interconnect is used to define possible signal
routes that are then selected dynamically by control
signals from an external MPU or control logic. These
functions are usually formulated early in the conceptual
design of a product. The data path requirements are
driven by the microprocessor, bus and memory architecture defined for the system. This part of the design is the
earliest portion of the system design frozen, and will not
usually change late in the design because the result
would be total system and PCB redesign. As a result, the
ability to accommodate arbitrary any pin-to-any pin rerouting is not a strong requirement as long as the designer
has the ability to define his functions with a reasonable
degree of freedom initially.
Figure 4. ispGDXV/VA Complements Lattice CPLDs
Address
Inputs
(from P)
Control
Inputs
(from P)
Data Path
Bus #1
ispLSI/
ispMACH
Device
Decoders
System
Clock(s)
As a result, the ispGDXV/VA architecture has been
defined to support PSR and PRSI applications (including
bidirectional paths) with no restrictions, while PDP applications (using dynamic MUXing) are supported with a
minimal number of restrictions as described below. In this
way, speed and cost can be optimized and the devices
can still support the system designer’s needs.
ISP/JTAG
Buffers / Registers Interface
State Machines
Control
Outputs
ispGDXV/VA
Device
Buffers / Registers
Configuration
(Switch)
Outputs
The following diagrams illustrate several ispGDXV/VA
applications.
Data Path
Bus #2
6
Specifications ispGDX160V/VA
Applications (Continued)
Figure 5. Address Demultiplex/Data Buffering
Designing with the ispGDXV/VA
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
Control Bus
MUXed Address Data Bus
XCVR
I/OA
I/OB
OEA
OEB
Buffered
Data
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
To Memory/
Peripherals
Address
Latch
D
Address
Q
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O0-39 (160 I/O device), it is not
possible to use I/O0 and I/O9 in the same MUX function.
As previously discussed, data path functions will be
assigned early in the design process and these restrictions are reasonable in order to optimize speed and cost.
CLK
Figure 6. Data Bus Byte Swapper
XCVR
I/OA
D0-7
I/OB
XCVR
Data Bus A
Control Bus
OEA OEB
I/OA
OEA OEB
XCVR
D8-15
I/OA
User Electronic Signature
I/OB
Data Bus B
D0-7
The ispGDXV/VA Family includes dedicated User Electronic Signature (UES) E2CMOS storage to allow users
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific command. This information can be read even when the
security cell is programmed.
D8-15
I/OB
XCVR
OEA OEB
I/OA
I/OB
OEA OEB
Security
The ispGDXV/VA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
Figure 7. Four-Port Memory Interface
Bus 1
Bus 2
Bus 3
Bus 4
4-to-1
16-Bit MUX
Bidirectional
Port #1
OE1
Memory
Port
Port #2
OE2
OEM
Port #3
OE3
SEL0
Port #4
OE4
SEL1
To
Memory
Note: All OE and SEL lines driven by external arbiter logic (not shown).
7
Specifications ispGDX160VA
Absolute Maximum Ratings 1,2
Supply Voltage Vcc ................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Conditions
SYMBOL
PARAMETER
VCC
Supply Voltage
VCCIO
I/O Reference Voltage
MIN.
MAX.
UNITS
Commercial
TA = 0°C to +70°C
3.00
3.60
V
Industrial
TA = -40°C to +85°C
3.00
3.60
V
2.3
3.60
V
Table 2-0005/gdx160va
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
C1
C2
PARAMETER
I/O Capacitance
Dedicated Clock Capacitance
PACKAGE TYPE
TYPICAL
UNITS
PQFP
7
pf
BGA, fpBGA
10
pf
PQFP
8
pf
BGA, fpBGA
10
pf
TEST CONDITIONS
VCC = 3.3V, VI/O = 2.0V
VCC = 3.3V, VY = 2.0V
Table 2-0006/gdx160va
Erase/Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
8
MINIMUM
MAXIMUM
UNITS
10,000
—
Cycles
Specifications ispGDX160VA
Switching Test Conditions
Figure 8. Test Load
Input Pulse Levels
GND to VCCIO(MIN)
< 1.5ns 10% to 90%
Input Rise and Fall Time
Input Timing Reference Levels
VCCIO(MIN)/2
Output Timing Reference Levels
VCCIO(MIN)/2
Output Load
See Figure 8
VCCIO
R1
Device
Output
3-state levels are measured 0.5V from steady-state active level.
Test
Point
CL*
R2
Output Load Conditions (See Figure 8)
3.3V
R1
R2
R1
153Ω
134Ω
156Ω
144Ω 35pF
Active High
∞
134Ω
∞
144Ω 35pF
Active Low
153Ω
∞
156Ω
∞
35pF
Active High to Z
at VOH -0.5V
∞
134Ω
∞
144Ω
5pF
Active Low to Z
at VOL+0.5V
153Ω
∞
156Ω
∞
5pF
∞
∞
∞
∞
35pF
TEST CONDITION
A
B
C
*CL includes Test Fixture and Probe Capacitance.
2.5V
D
Slow Slew
R2
0213D
CL
Table 2-0004A/gdx160va
DC Electrical Characteristics for 3.3V Range1
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
–
3.0
–
VCCIO
VIL
VIH
Input Low Voltage
VOH ≤ VOUT or VOUT ≤ VOL (MAX)
-0.3
Input High Voltage
VOH ≤ VOUT or VOUT ≤ VOL(MAX)
2.0
VOL
Output Low Voltage
VCC = VCC (MIN)
IOL = +100µA
VOH
I/O Reference Voltage
Output High Voltage
VCC = VCC (MIN)
MAX. UNITS
3.6
V
–
0.8
V
–
5.25
V
–
–
0.2
V
IOL = +24mA
–
–
0.55
V
IOH = -100µA
2.8
–
–
V
IOH = -12mA
2.4
–
–
V
Table 2-0007/gdx160va
1. I/O voltage configuration must be set to VCC.
9
Specifications ispGDX160VA
DC Electrical Characteristics for 2.5V Range1
Over Recommended Operating Conditions
SYMBOL
VCCIO
VIL
VIH
PARAMETER
CONDITION
MIN.
TYP.
–
2.3
–
2.7
V
I/O Reference Voltage
MAX. UNITS
Input Low Voltage
VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX)
-0.3
–
0.7
V
Input High Voltage
VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX)
1.7
–
5.25
V
VOL
Output Low Voltage
VOH
Output High Voltage
VCCIO=MIN, IOL = 100µA
–
–
0.2
V
VCCIO=MIN, IOL = 8mA
–
–
0.6
V
VCCIO=MIN, IOH = -100µA
2.1
–
–
V
VCCIO=MIN, IOH = -8mA
1.8
–
–
1. I/O voltage configuration must be set to VCCIO.
V
2.5V/gdx160va
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
IIL
IIH
IPU
IBHLS
IBHHS
IBHLO
IBHHO
IBHT
IOS1
ICCQ4
MIN.
TYP.2
MAX.
UNITS
0V ≤ VIN ≤ VIL (MAX)
–
–
-10
µA
(VCCIO-0.2) ≤ VIN ≤ VCCIO
–
–
10
µA
VCCIO ≤ VIN ≤ 5.25V
–
–
50
µA
–
–
-200
µA
Bus Hold Low Sustaining Current
0V ≤ VIN ≤ VIL (MAX)
VIN = VIL (MAX)
40
–
–
µA
Bus Hold High Sustaining Current
VIN = VIH (MIN)
-40
–
–
µA
Bus Hold Low Overdrive Current
0V ≤ VIN ≤ VCCIO
–
–
550
µA
0V ≤ VIN ≤ VCCIO
–
–
-550
µA
CONDITION
PARAMETER
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
I/O Active Pullup Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
Output Short Circuit Current
Quiescent Power Supply Current
ICC
Dynamic Power Supply Current
per Input Switching
ICONT 5
Maximum Continuous I/O Pin Sink
Current Through Any GND Pin
VIL
–
VIH
V
VCC = 3.3V, VOUT = 0.5V, TA = 25°C
–
–
-250
mA
VIL = 0.5V, VIH = VCC
–
16.5
–
mA
One input toggling at 50% duty cycle,
outputs open.
–
See
Note 3
–
mA/
MHz
–
–
160
mA
–
DC Char_gdx160va
1. One output at a time for a maximum of one second. VOUT = 0.5V was selected to avoid test problems by
tester ground degradation. Characterized, but not 100% tested.
2. Typical values are at VCC = 3.3V and TA = 25°C.
3. ICC / MHz = (0.003 x I/O cell fanout) + 0.029.
e.g. An input driving four I/O cells at 40MHz results in a dynamic ICC of approximately ((0.003 x 4) + 0.029) x 40 = 1.64mA.
4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals.
5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.
10
Specifications ispGDX160VA
External Timing Parameters
Over Recommended Operating Conditions
TEST1
PARAMETER COND. #
tpd2
tsel2
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
tgco12
tgco22
tco12
tco22
ten2
tdis2
ttoeen2
ttoedis2
twh
twl
trst
trw
tsl
tsk
-5
-3
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
A
1 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)
–
3.5
–
5.0
ns
A
2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
–
3.5
–
5.0
ns
–
3 Clock Frequency, Max. Toggle
–
4 Clock Frequency with External Feedback (
–
250
–
143
–
MHz
166.7
–
111
–
MHz
5 Input Latch or Register Setup Time Before Yx
3.0
–
4.0
–
ns
–
6 Input Latch or Register Setup Time Before I/O Clock
2.5
–
3.0
–
ns
–
7 Output Latch or Register Setup Time Before Yx
2.5
–
4.0
–
ns
–
8 Output Latch or Register Setup Time Before I/O Clock
2.0
–
3.0
–
ns
–
9 Global Clock Enable Setup Time Before Yx
2.5
–
2.5
–
ns
–
10 Global Clock Enable Setup Time Before I/O Clock
1.5
–
1.5
–
ns
–
11 I/O Clock Enable Setup Time Before Yx
3.0
–
4.5
–
ns
–
12 Input Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
ns
–
13 Input Latch or Reg. Hold Time (I/O Clock)
0.5
–
1.5
–
ns
–
14 Output Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
ns
–
15 Output Latch or Reg. Hold Time (I/O Clock)
1.0
–
1.5
–
ns
–
16 Global Clock Enable Hold Time (Yx)
0.0
–
0.0
–
ns
–
17 Global Clock Enable Hold Time (I/O Clock)
1.0
–
1.5
–
ns
–
18 I/O Clock Enable Hold Time (Yx)
0.0
–
0.0
–
ns
A
19 Output Latch or Reg. Clock (from Yx) to Output Delay
–
3.5
–
5.0
ns
A
20 Input Latch or Register Clock (from Yx) to Output Delay
–
6.0
–
8.5
ns
A
21 Output Latch or Register Clock (from I/O pin) to Output Delay
–
4.0
–
6.0
ns
A
22 Input Latch or Register Clock (from I/O pin) to Output Delay
–
7.0
–
9.5
ns
1
tsu3+tgco1
)
B
23 Input to Output Enable
–
5.0
–
6.0
ns
C
24 Input to Output Disable
–
5.0
–
6.0
ns
B
25 Test OE Output Enable
–
6.0
–
6.0
ns
C
26 Test OE Output Disable
–
6.0
–
6.0
ns
–
27 Clock Pulse Duration, High
2.0
–
3.5
–
ns
–
28 Clock Pulse Duration, Low
2.0
–
3.5
–
ns
–
29 Register Reset Delay from RESET Low
–
8.0
–
14.0
ns
–
30 Reset Pulse Width
5.0
–
10.0
–
ns
D
31 Output Delay Adder for Output Timings Using Slow Slew Rate
–
3.5
–
5.0
ns
ns
0.5
–
0.5
–
A 32 Output Skew (tgco1 Across Chip)
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
11
Specifications ispGDX160VA
External Timing Parameters
Over Recommended Operating Conditions
TEST1
PARAMETER COND. #
tpd2
tsel2
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
tgco12
tgco22
tco12
tco22
ten2
tdis2
ttoeen2
ttoedis2
twh
twl
trst
trw
tsl
tsk
-9
-7
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
A
1 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)
–
7.0
–
9.0
ns
A
2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
–
7.0
–
9.0
ns
–
3 Clock Frequency, Max. Toggle
100
–
83
–
MHz
–
4 Clock Frequency with External Feedback (
80
–
62.5
–
MHz
–
5 Input Latch or Register Setup Time Before Yx
5.5
–
7.0
–
ns
–
6 Input Latch or Register Setup Time Before I/O Clock
4.5
–
6.0
–
ns
–
7 Output Latch or Register Setup Time Before Yx
5.5
–
7.0
–
ns
–
8 Output Latch or Register Setup Time Before I/O Clock
4.5
–
6.0
–
ns
–
9 Global Clock Enable Setup Time Before Yx
3.5
–
4.0
–
ns
–
10 Global Clock Enable Setup Time Before I/O Clock
2.5
–
3.0
–
ns
–
11 I/O Clock Enable Setup Time Before Yx
6.5
–
8.5
–
ns
–
12 Input Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
ns
–
13 Input Latch or Reg. Hold Time (I/O Clock)
2.5
–
3.0
–
ns
–
14 Output Latch or Reg. Hold Time (Yx)
0.0
–
0.0
–
ns
–
15 Output Latch or Reg. Hold Time (I/O Clock)
2.5
–
3.0
–
ns
–
16 Global Clock Enable Hold Time (Yx)
0.0
–
0.0
–
ns
–
17 Global Clock Enable Hold Time (I/O Clock)
2.5
–
3.0
–
ns
–
18 I/O Clock Enable Hold Time (Yx)
0.0
–
0.0
–
ns
A
19 Output Latch or Reg. Clock (from Yx) to Output Delay
–
7.0
–
9.0
ns
A
20 Input Latch or Register Clock (from Yx) to Output Delay
–
11.0
–
13.5
ns
A
21 Output Latch or Register Clock (from I/O pin) to Output Delay
–
9.0
–
11.5
ns
A
22 Input Latch or Register Clock (from I/O pin) to Output Delay
–
13.0
–
15.7
ns
1
tsu3+tgco1
)
B
23 Input to Output Enable
–
8.5
–
10.5
ns
C
24 Input to Output Disable
–
8.5
–
10.5
ns
B
25 Test OE Output Enable
–
8.5
–
10.5
ns
C
26 Test OE Output Disable
–
8.5
–
10.5
ns
–
27 Clock Pulse Duration, High
5.0
–
6.0
–
ns
–
28 Clock Pulse Duration, Low
5.0
–
6.0
–
ns
–
29 Register Reset Delay from RESET Low
–
18.0
–
22.0
ns
–
30 Reset Pulse Width
14.0
–
18.0
–
ns
D
31 Output Delay Adder for Output Timings Using Slow Slew Rate
–
7.0
–
9.0
ns
ns
1.0
–
A 32 Output Skew (tgco1 Across Chip)
–
0.5
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
12
Specifications ispGDX160VA
External Timing Parameters (Continued)
ispGDX160VA timings are specified with a GRP load
(fanout) of four I/O cells. The figure below shows the ∆
GRP Delay with increased GRP loads. These deltas
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
which do not use the GRP have no fanout delay adder.
ispGDX160VA Maximum ∆ GRP Delay vs. I/O Cell Fanout
∆ GRP Delay (ns)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0 4 10
20 30 40 50
I/O Cell Fanout
13
60
70
Specifications ispGDX160VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-3
PARAMETER
DESCRIPTION1
#
-5
MIN. MAX. MIN. MAX. UNITS
Inputs
tio
32
Input Buffer Delay
—
0.4
—
0.9
ns
GRP
tgrp
33
GRP Delay
—
1.1
—
1.1
ns
MUX
tmuxd
34
I/O Cell MUX A/B/C/D Data Delay
—
1.0
—
1.5
ns
tmuxexp
tmuxs
35
36
I/O Cell MUX A/B/C/D Expander Delay
I/O Cell Data Select
—
—
1.5
1.0
—
—
2.0
1.5
ns
ns
tmuxsio
tmuxsg
37
38
I/O Cell Data Select (I/O Clock)
I/O Cell Data Select (Yx Clock)
—
—
1.5
1.5
—
—
3.0
2.0
ns
ns
tmuxselexp
Register
39
I/O Cell MUX Data Select Expander Delay
—
1.5
—
2.0
ns
tiolat
tiosu
40
41
I/O Latch Delay
I/O Register Setup Time Before Clock
—
—
1.0
0.8
—
—
1.0
2.0
ns
ns
tioh
tioco
42
43
I/O Register Hold Time After Clock
I/O Register Clock to Output Delay
—
—
1.7
1.2
—
—
1.5
0.5
ns
ns
tior
tcesu
44
45
I/O Reset to Output Delay
I/O Clock Enable Setup Time Before Clock
—
—
1.0
2.3
—
—
1.5
2.0
ns
ns
tceh
Data Path
46
I/O Clock Enable Hold Time After Clock
—
0.2
—
0.5
ns
tfdbk
tiobp
47
48
I/O Register Feedback Delay
I/O Register Bypass Delay
—
—
0.6
0.0
—
—
0.9
0.0
ns
ns
tioob
tmuxcg
49
50
I/O Register Output Buffer Delay
I/O Register A/B/C/D Data Input MUX Delay (Yx Clock)
—
—
0.0
1.5
—
—
0.0
2.0
ns
ns
tmuxcio
tiodg
51
52
I/O Register A/B/C/D Data Input MUX Delay (I/O Clock)
I/O Register I/O MUX Delay (Yx Clock)
—
—
1.5
3.5
—
—
3.0
4.0
ns
ns
tiodio
Outputs
53
I/O Register I/O MUX Delay (I/O Clock)
—
3.5
—
5.0
ns
tob
tobs
54
55
Output Buffer Delay
Output Buffer Delay (Slow Slew Option)
—
—
1.0
4.5
—
—
1.5
6.5
ns
ns
toeen
toedis
56
57
I/O Cell OE to Output Enable
I/O Cell OE to Output Disable
—
—
3.5
3.5
—
—
4.0
4.0
ns
ns
tgoe
ttoe
58
59
GRP Output Enable and Disable Delay
Test OE Enable and Disable Delay
—
—
0.0
2.5
—
—
0.0
2.0
ns
ns
Clocks
tioclk
60
I/O Clock Delay
—
0.3
—
2.0
ns
tgclk
tgclkeng
61
62
Global Clock Delay
Global Clock Enable (Yx Clock)
—
—
1.3
1.5
—
—
2.0
2.5
ns
ns
tgclkenio
tioclkeng
63
64
Global Clock Enable (I/O Clock)
I/O Clock Enable (Yx Clock)
—
—
1.0
0.5
—
—
3.5
2.5
ns
ns
65
Global Reset to I/O Register Latch
—
6.0
—
11.0
ns
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
14
Specifications ispGDX160VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-7
PARAMETER
DESCRIPTION1
#
-9
MIN. MAX. MIN. MAX. UNITS
Inputs
tio
32
Input Buffer Delay
—
1.4
—
1.9
ns
GRP
tgrp
33
GRP Delay
—
1.1
—
1.1
ns
MUX
tmuxd
34
I/O Cell MUX A/B/C/D Data Delay
—
2.0
—
2.5
ns
tmuxexp
tmuxs
35
36
I/O Cell MUX A/B/C/D Expander Delay
I/O Cell Data Select
—
—
2.5
2.0
—
—
3.0
2.5
ns
ns
tmuxsio
tmuxsg
37
38
I/O Cell Data Select (I/O Clock)
I/O Cell Data Select (Yx Clock)
—
—
4.5
2.5
—
—
6.0
3.0
ns
ns
tmuxselexp
Register
39
I/O Cell MUX Data Select Expander Delay
—
2.5
—
3.0
ns
tiolat
tiosu
40
41
I/O Latch Delay
I/O Register Setup Time Before Clock
—
—
1.0
3.2
—
—
1.0
4.4
ns
ns
tioh
tioco
42
43
I/O Register Hold Time After Clock
I/O Register Clock to Output Delay
—
—
2.3
0.5
—
—
2.6
0.5
ns
ns
tior
tcesu
44
45
I/O Reset to Output Delay
I/O Clock Enable Setup Time Before Clock
—
—
1.5
2.5
—
—
1.5
2.0
ns
ns
tceh
Data Path
46
I/O Clock Enable Hold Time After Clock
—
1.0
—
2.0
ns
tfdbk
tiobp
47
48
I/O Register Feedback Delay
I/O Register Bypass Delay
—
—
1.2
0.3
—
—
1.3
0.6
ns
ns
tioob
tmuxcg
49
50
I/O Register Output Buffer Delay
I/O Register A/B/C/D Data Input MUX Delay (Yx Clock)
—
—
0.6
2.5
—
—
0.7
3.0
ns
ns
tmuxcio
tiodg
51
52
I/O Register A/B/C/D Data Input MUX Delay (I/O Clock)
I/O Register I/O MUX Delay (Yx Clock)
—
—
4.5
5.0
—
—
6.0
6.0
ns
ns
tiodio
Outputs
53
I/O Register I/O MUX Delay (I/O Clock)
—
7.0
—
9.0
ns
tob
tobs
54
55
Output Buffer Delay
Output Buffer Delay (Slow Slew Option)
—
—
2.2
9.2
—
—
2.9
11.9
ns
ns
toeen
toedis
56
57
I/O Cell OE to Output Enable
I/O Cell OE to Output Disable
—
—
6.0
6.0
—
—
7.5
7.5
ns
ns
tgoe
ttoe
58
59
GRP Output Enable and Disable Delay
Test OE Enable and Disable Delay
—
—
0.0
2.5
—
—
0.0
3.0
ns
ns
Clocks
tioclk
60
I/O Clock Delay
—
3.2
—
4.4
ns
tgclk
tgclkeng
61
62
Global Clock Delay
Global Clock Enable (Yx Clock)
—
—
2.7
3.7
—
—
3.4
5.4
ns
ns
tgclkenio
tioclkeng
63
64
Global Clock Enable (I/O Clock)
I/O Clock Enable (Yx Clock)
—
—
5.7
4.2
—
—
8.4
6.4
ns
ns
65
Global Reset to I/O Register Latch
—
13.7
—
16.4
ns
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
15
Specifications ispGDX160V
Absolute Maximum Ratings 1,2
Supply Voltage Vcc ................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Conditions
SYMBOL
PARAMETER
MAX.
UNITS
Commercial
TA = 0°C to +70°C
3.0
3.6
V
Industrial
TA = -40°C to +85°C
3.0
3.6
V
Input Low Voltage
-0.3
0.8
V
Input High Voltage
2.0
5.25
VCC
Supply Voltage
VIL
VIH1
1
MIN.
V
Table 2-0005/gdxv
1. Typical 100mV of input hysteresis.
Capacitance (TA=25oC, f=1.0 MHz)
TYPICAL
UNITS
I/O Capacitance
8
pf
VCC = 3.3V, VI/O = 2.0V
Dedicated Clock Capacitance
10
pf
VCC = 3.3V, VY = 2.0V
SYMBOL
C1
C2
PARAMETER
TEST CONDITIONS
Table 2 - 0006
Erase/Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
16
MINIMUM
MAXIMUM
UNITS
10,000
—
Cycles
Specifications ispGDX160V
Switching Test Conditions
Input Pulse Levels
+ 3.3V
GND to 3.0V
≤ 1.5ns 10% to 90%
Input Rise and Fall Time
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
Device
Output
Test
Point
See figure at right
Output Load Conditions
TEST CONDITION
R1
R2
CL
153Ω
134Ω
35pF
Active High
∞
134Ω
35pF
Active Low
A
B
C
D
153Ω
∞
35pF
Active High to Z
at VOH -0.5V
∞
134Ω
5pF
Active Low to Z
at VOL +0.5V
153Ω
∞
5pF
∞
∞
Slow Slew
CL *
R2
3-state levels are measured 0.5V from steady-state
active level.
*CL includes Test Fixture and Probe Capacitance.
35pF
Table 2-0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
MIN.
TYP.2
MAX.
UNITS
IOL =24 mA
–
–
0.55
V
Output High Voltage
IOH =-12 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
Input or I/O High Leakage Current
VCC ≤ VIN ≤ 5.25V
–
–
10
µA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Bus Hold Low Sustaining Current
VIN = VIL (Max.)
50
–
–
µA
Bus Hold High Sustaining Current
VIN = VIH (Min.)
-50
–
–
µA
Bus Hold Low Overdrive Current
0V ≤ VIN ≤ VCC
–
–
550
µA
Bus Hold High Overdrive Current
0V ≤ VIN ≤ VCC
–
PARAMETER
VOL
VOH
IIL
IIH
IIL-PU
IBHLS
IBHHS
IBHLO
IBHHO
IBHT
IOS1
ICCQ4
ICC
Output Low Voltage
ICONT5
Maximum Continuous I/O Pin Sink
Current Through Any GND Pin
CONDITION
Bus Hold Trip Points
–
-550
µA
VIL
–
VIH
V
Output Short Circuit Current
VCC = 3.3V, VOUT = 0.5V, TA = 25˚C
–
–
-250
mA
Quiescent Power Supply Current
VIL = 0.5V, VIH = VCC
–
70
–
mA
Dynamic Power Supply Current
per Input Switching
One input toggling @ 50% duty cycle,
outputs open.
–
See
Note 3
–
mA/MHz
–
–
96
mA
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Typical values are at VCC = 3.3V and TA = 25oC.
3. ICC / MHz = (0.01 x I/O cell fanout) + 0.04
e.g. An input driving four I/O cells at 40 MHz results in a dynamic ICC of approximately ((0.01 x 4) + 0.04) x 40 = 3.2 mA.
4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bidirectionals.
5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.
17
Specifications ispGDX160V
External Timing Parameters
Over Recommended Operating Conditions
1
PARAMETER TEST
COND.
tpd
tsel
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
tgco1
tgco2
tco1
tco2
ten
tdis
ttoeen
ttoedis
twh
twl
trst
trw
tsl
tsk
#
-5
DESCRIPTION
-7
UNITS
MIN. MAX. MIN. MAX.
A
1
Data Prop. Delay from Any I/O pin to Any I/O pin (4:1 MUX)
A
2
Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
–
3
Clock Frequency, Max. Toggle
–
4
Clock Frequency with External Feedback (
–
5
–
–
–
5.0
–
7.0
ns
–
6.5
–
9.0
ns
143
–
100
–
MHz
110
–
80.0
–
MHz
Input Latch or Register Setup Time Before Yx
4.0
–
5.5
–
ns
6
Input Latch or Register Setup Time Before I/O Clock
3.0
–
4.5
–
ns
7
Output Latch or Register Setup Time Before Yx
4.0
–
5.5
–
ns
–
8
Output Latch or Register Setup Time Before I/O Clock
3.0
–
4.5
–
ns
–
9
Global Clock Enable Setup Time Before Yx
2.5
–
3.5
–
ns
–
10 Global Clock Enable Setup Time Before I/O Clock
1.5
–
2.5
–
ns
–
11 I/O Clock Enable Setup Time Before Yx
4.5
–
6.5
–
ns
–
12 Input Latch or Register Hold Time (Yx)
0.0
–
0.0
–
ns
–
13 Input Latch or Register Hold Time (I/O Clock)
1.5
–
2.5
–
ns
–
14 Output Latch or Register Hold Time (Yx)
0.0
–
0.0
–
ns
–
15 Output Latch or Register Hold Time (I/O Clock)
1.5
–
2.5
–
ns
–
16 Global Clock Enable Hold Time (Yx)
0.0
–
0.0
–
ns
–
17 Global Clock Enable Hold Time (I/O Clock)
1.5
–
2.5
–
ns
1
tsu3+tgco1
)
–
18 I/O Clock Enable Hold Time (Yx)
0.0
–
0.0
–
ns
A
19 Output Latch or Register Clock (from Yx) to Output Delay
–
5.0
–
7.0
ns
A
20 Input Latch or Register Clock (from Yx) to Output Delay
–
8.5
–
11.0
ns
A
21 Output Latch or Register Clock (from I/O pin) to Output Delay
–
6.0
–
9.0
ns
A
22 Input Latch or Register Clock (from I/O pin) to Output Delay
–
9.5
–
13.0
ns
B
23 Input to Output Enable
–
6.0
–
8.5
ns
C
24 Input to Output Disable
–
6.0
–
8.5
ns
B
25 Test OE Output Enable
–
9.0
–
12.0
ns
C
26 Test OE Output Disable
–
9.0
–
12.0
ns
–
27 Clock Pulse Duration, High
3.5
–
5.0
–
ns
–
28 Clock Pulse Duration, Low
3.5
–
5.0
–
ns
–
29 Register Reset Delay from RESET Low
–
14.0
–
18.0
ns
–
30 Reset Pulse Width
10.0
–
14.0
–
ns
D
31 Output Delay Adder for Output Timings Using Slow Slew Rate
–
8.0
–
12.0
ns
–
0.5
–
0.5
ns
A
32 Output Skew (tgco1 Across Chip)
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
18
Specifications ispGDX160V
External Timing Parameters (Continued)
ispGDX160V timings are specified with a GRP load
(fanout) of four I/O cells. The figure below shows the ∆
GRP Delay with increased GRP loads. These deltas
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
which do not use the GRP have no fanout delay adder.
ispGDX160V Maximum ∆ GRP Delay vs. I/O Cell Fanout
∆ GRP Delay (ns)
10
8
6
4
2
0 4 10
20
30
40
50
I/O Cell Fanout
19
60
70
Specifications ispGDX160V
Internal Timing Parameters1
Over Recommended Operating Conditions
-5
PARAMETER
DESCRIPTION1
#
-7
MIN. MAX. MIN. MAX. UNITS
Inputs
tio
32
Input Buffer Delay
—
0.9
—
1.4
ns
GRP
tgrp
33
GRP Delay
—
1.1
—
1.1
ns
MUX
tmuxd
34
I/O Cell MUX A/B/C/D Data Delay
—
1.5
—
2.0
ns
tmuxexp
tmuxs
35
36
I/O Cell MUX A/B/C/D Expander Delay
I/O Cell Data Select
—
—
2.0
3.0
—
—
2.5
4.0
ns
ns
tmuxsio
tmuxsg
37
38
I/O Cell Data Select (I/O Clk)
I/O Cell Data Select (Yx Clk)
—
—
4.5
3.5
—
—
6.5
4.5
ns
ns
tmuxselexp
Register
39
I/O Cell MUX Data Select Expander Delay
—
3.5
—
4.5
ns
tiolat
tiosu
40
41
I/O Latch Delay
I/O Register Setup Time Before Clock
—
—
1.0
2.0
—
—
1.0
3.2
ns
ns
tioh
tioco
42
43
I/O Register Hold Time After Clock
I/O Register Clock to Output Delay
—
—
1.5
0.5
—
—
2.3
0.5
ns
ns
tior
tcesu
44
45
I/O Reset to Output Delay
I/O Clock Enable Setup Time Before Clock
—
—
1.5
2.0
—
—
1.5
2.5
ns
ns
tceh
Data Path
46
I/O Clock Enable Hold Time After Clock
—
0.5
—
1.0
ns
tfdbk
tiobp
47
48
I/O Register Feedback Delay
I/O Register Bypass Delay
—
—
0.9
0.0
—
—
1.2
0.3
ns
ns
tioob
tmuxcg
49
50
I/O Register Output Buffer Delay
I/O Register A/B/C/D Data Input MUX Delay (Yx Clk)
—
—
0.0
2.0
—
—
0.6
2.5
ns
ns
tmuxcio
tiodg
51
52
I/O Register A/B/C/D Data Input MUX Delay (I/O Clk)
I/O Register I/O MUX Delay (Yx Clk)
—
—
3.0
4.0
—
—
4.5
5.0
ns
ns
tiodio
Outputs
53
I/O Register I/O MUX Delay (I/O Clk)
—
5.0
—
7.0
ns
tob
tobs
54
55
Output Buffer Delay
Output Buffer Delay (Slow Slew Option)
—
—
1.5
9.5
—
—
2.2
14.2
ns
ns
toeen
toedis
56
57
I/O Cell OE to Output Enable
I/O Cell OE to Output Disable
—
—
4.0
4.0
—
—
6.0
6.0
ns
ns
tgoe
ttoe
58
59
GRP Output Enable and Disable Delay
Test OE Enable and Disable Delay
—
—
0.0
5.0
—
—
0.0
6.0
ns
ns
Clocks
tioclk
60
I/O Clock Delay
—
2.0
—
3.2
ns
tgclk
tgclkeng
61
62
Global Clock Delay
Global Clock Enable (Yx Clk)
—
—
2.0
2.5
—
—
2.7
3.7
ns
ns
tgclkenio
tioclkeng
63
64
Global Clock Enable (I/O Clk)
I/O Clock Enable (Yx Clk)
—
—
3.5
2.5
—
—
5.7
4.2
ns
ns
65
Global Reset to I/O Register Latch
—
11.0
—
13.7
ns
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
20
Specifications ispGDX160V/VA
Switching Waveforms
DATA
(I/O INPUT)
VALID INPUT
MUXSEL (I/O INPUT)
VALID INPUT
tsu
tsel
DATA (I/O INPUT)
VALID INPUT
th
t gco
CLK
tco
tpd
COMBINATORIAL
I/O OUTPUT
REGISTERED
I/O OUTPUT
1/fmax
(external fdbk)
Combinatorial Output
t suce
t ceh
OE (I/O INPUT)
CLKEN
tdis
ten
Registered Output
COMBINATORIAL
I/O OUTPUT
I/O Output Enable/Disable
RESET
t rw
twh
t rst
twl
REGISTERED
I/O OUTPUT
CLK
(I/O INPUT)
Clock Width
Reset
ispGDXV Timing Model
tgoe #58
OE
MUX Expander Input
tmuxd #34
tmuxs #36
tmuxio #37
tmuxg #38
tmuxcg #50
tmuxcio #51
TOE
ttoe #59
A
B
C
D
tiobp #48
D
MUX0
GRP
MUX Expander Output
tmuxexp #35
tmuxselexp #39
Q
tioob #49
I/O Pin
CLKEN
MUX1
tob #54
tobs #55
toeen #56
toedis #57
CLK
tgrp #33
tiod #52, #53
tiolat #40
tiosu #41
tioh #42
tioco #43
tior #44
tcesu #45
tceh #46
tgr #65
RESET
tfdbk #47
tio #32
CLKEN
CLK
tioclkeg #64
tioclk #60
Y0,1,2,3
0902/gdx160v/va
tgclk #61
Y0,1,2,3, Enable
tgclkeng #62
tgclkenio #63
21
Specifications ispGDX160V/VA
ispGDX Development System
The ispGDX Development System supports ispGDX
design using a simple language syntax and an easy-touse Graphical User Interface (GUI) called Design
Manager. From creation to In-System Programming, the
ispGDX system is an easy-to-use, self-contained design
tool delivered on CD-ROM media.
Status Bar and the work area. The figure below shows
these elements of the ispGDX GUI.
The Menu Bar displays topics related to functions used in
the design process. Access the various drop-down menus
and submenus by using the mouse or “hot” keys. The
menu items available in the ispGDX system are FILE,
EDIT, DEVICE, INVOKE, INTERFACES, VIEW, WINDOW and HELP.
Features
• Easy-to-use Text Entry System
The Tool Bar is a quick and easy way to perform many of
the functions found in the menus with a single click of the
mouse. File, Edit, Undo, Redo, Find, Print Download and
Compiler are just some of the Icons found in the ispGDX
Tool Bar. For instance, the Compiler Icon performs the
same function as the Invoke => Compiler menu commands, including design analysis and rule checking and
the fitting operation.
• ispGDX Design Compiler
- Design Rule Checker
- I/O Connectivity Checker
- Automatic Compiler Function
• Industry Standard JEDEC File for Programming
• Min / Max Timing Report
• Interfaces To Popular Timing Simulators
The Status Bar displays action prompts and the line and
column numbers reflect the location of the cursor within
the message window or the work area.
• User Electronic Signature (UES) Support
• Detailed Log and Report Files For Easy Design Debug
• On-Line Help
Workstation Version
• Windows® 3.1x, Windows 95, Windows 98 and Windows NT® Compatible Graphical User Interface
The ispGDX software is also available for use under the
Sun O/S 4.1.x or Solaris 2.4 or 2.5. The Sun version of the
ispGDX software is invoked from the command line
under the UNIX operating system. A GUI is not supported
in this environment.
• SUN O/S, Command Line Driven version available
PC Version
With the ispGDX GUI for the PC, command line entry is
not required. The tools run under Microsoft Windows 3.1,
Windows 95, Windows 98 and Windows NT. When the
ispGDX software is invoked, the Design Manager and an
accompanying message window are displayed. The
Design Manager consists of the Menu Bar, Tool Bar,
In the UNIX environment, the ispGDX Design File (GDF)
must be created using a text editor. Once the GDF has
been created, invoke the ispGDX workstation software
from the UNIX command line. The following is an example of how to invoke ispGDX software.
Lattice’s ispGDX Development System Interface
Usage:
ispGDX
[-i input_file]
[-of[edif|orcad|viewlogic|verilog|vhdl]]
[-p part name]
[-r par_file]
Where:
-i input_file
-of [edif | orcad | viewlogic |
verilog | vhdl]
-p part_name
-r par_file
22
ispGDX design file
Output format
ispGDX part number
Read parameters from
parameter file
Specifications ispGDX160V/VA
ispGDX Development System (Continued)
This example shows a simple, but complete, 32-bit 3:1
MUX design. Once completed, the compiler takes over.
The GDF File
The GDF file is a simple text description of the design
function, device and pin parameters. The file has four
parts: device selection, set and constant statements, a
pin section and a connection section. A sample file looks
like this:
Powerful Syntax
Lattice’s ispGDX Design System uses simple, but powerful, syntax to easily define a design. The !(bang) operator
controls pin polarity and can be used in both the pin and
connection sections of the design definition. Dot extensions define data inputs, select controls for the 4:1
multiplexor, and control inputs of sequential elements
and tri-state buffers. Dot extensions are .M# (MUX Input),
.S# (MUX Select), and control functions, such as .CLK,
.EN, .OE and .A (shown in adjacent table). Pin Attributes
are assigned in the pin section of the GDF as well.
SLOWSLEW selects the slow slew rate for an output
buffer. The Pull parameter can be used to select the
internal pull-up or bus hold latch. OPEN drain can be
used to select open drain operation. The COMB attribute
distinguishes the structure for bidirectional pins. If COMB
is used, the input register, or latch, of an output buffer will
be applied to bidirectional pins.
// 32-Bit Data 3 to 1 Mux
DESIGN
datamux;
PART ispGDX160V-7Q208;
PARAM SECURITY ON;
PARAM OPENDRAIN ON;
PARAM PULL HOLD;
SET
SET
SET
SET
BUS_A
BUS_B
BUS_C
BUS_D
INPUT
INPUT
INPUT
OUTPUT
//
//
//
//
USE OPEN DRAIN
OPTION
USE BUS HOLD
LATCH OPTION
[dataA31..dataA0];
[dataB31..dataB0];
[dataC31..dataC0];
[dataD31..dataD0];
BUS_A
BUS_B
BUS_C
BUS_D
Please consult the ispGDX Development System Manual
for full details.
{A31..A0};
{B31..B0};
{C31..C0};
{D31..D0};
ispGDX GDF File Dot Extensions
INPUT [oe] {B37};
INPUT [clk] {B36};
INPUT [sel1]
INPUT [sel0]
{B38};
{B39};
Type
Dot Ext.
.M0
MUXA Data input to 4:1 MUX
MUX
Input
.M1
MUXB Data input to 4:1 MUX
.M2
MUXC Data Input to 4:1 MUX
.M3
MUXD Data input to 4:1 MUX
.S0
MUX0 Selection input to 4:1 MUX
.S1
MUX1 Selection input to 4:1 MUX
MUX
Selection
BEGIN
BUS_D.m0
BUS_D.m1
BUS_D.m2
BUS_D.m3
=
=
=
=
BUS_A;
BUS_B;
BUS_C;
VCC;
Control
// Default all
// outputs to VCC
MUX
Output
Description
.CLK
Clock for a register
.EN
Latch enable for a latch signal
.OE
Output enable for 3-state output
or bidirectional signal
.CE
Clock enable for register clock
.A
Adjacent MUX output of an I/O cell
ispGDXV Dot Ext
BUS_D.s1 = sel1;
BUS_D.s0 = sel0;
BUS_D.oe = oe;
BUS_D.clk = clk;
END
23
Specifications ispGDX160V/VA
ispGDX Development System (Continued)
The ispGDX Design System Compiler
Third-Party Timing Simulation
After the GDF file is created, the compiler checks the
syntax and provides helpful hints and the location of any
syntax errors. The compiler performs design rule checks,
such as, clock and enable designations, the use of input/
output/BIDI usage, and the proper use of attributes. I/O
connectivity is also checked to ensure polarity, MUX
selection controls, and connections are properly made.
Compilation is completed automatically and report and
programming files are saved.
The ispGDX Design System will generate simulation
netlists as specified by a user. The simulation netlist
formats available are: EDIF, Verilog (OVI compliant),
VHDL (VITAL compliant), Viewlogic, and OrCAD.
For In-System Programming, Lattice’s ispGDX devices
may be programmed, alone or in a chain with up to 100
other Lattice ISP devices, using Lattice’s ISP Daisy
Chain Download software. This powerful Windows-based
tool can be launched from the Tool Bar or by Invoking the
Download option from the drop down menu within the
ispGDX Design System. ISP Daisy Chain Download
version 7.1 or above supports the ispGDX Family devices.
Reports Generated
When the ispGDX system compiles a design and generates the specified netlists, the following output files are
created:
Report Files:
.log
Compiler History
.rpt
Compiler Report
.mfr
Maximum Frequency Timing Report
.tsu
Set-up and Hold Timing Report
.tco
Clock to Out Timing Report
.tpt
Timing Report
Simulation File:
.sim
Post-Route Simulation With LAC Format
Netlists:
.edo
.vlo
.ifo
.vho
.vhn
.vto
EDIF Output
Verilog Output
OrCAD Output
VHDL non-VITAL with Maximum Delays Output
VHDL non-VITAL with Maximum Delays Output
VHDL VITAL Output
Download:
.jed
JEDEC Device Programming File
24
Specifications ispGDX160V/VA
In-System Programmability
All necessary programming of the ispGDXV/VA is done
via four TTL level logic interface signals. These four
signals are fed into the on-chip programming circuitry
where a state machine controls the programming.
when the pin is left unconnected, in which case the pin is
pulled high by the permanent internal pullup. This allows
ISP programming and BSCAN testing to take place as
specified by the Instruction Table.
On-chip programming can be accomplished using an
IEEE 1149.1 boundary scan protocol. The IEEE 1149.1compliant interface signals are Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS) control. The EPEN pin is also used to enable or
disable the JTAG port.
When the pin is driven low, the JTAG TAP controller is
driven to a reset state asynchronously. It stays there
while the pin is held low. After pulling the pin high the
JTAG controller becomes active. The intent of this feature is to allow the JTAG interface to be directly controlled
by the data bus of an embedded controller (hence the
name Embedded Port Enable). The EPEN signal is used
as a “device select” to prevent spurious programming
and/or testing from occuring due to random bit patterns
on the data bus. Figure 9 illustrates the block diagram for
the ispJTAG interface.
The embedded controller port enable pin (EPEN) is used
to enable the JTAG tap controller and in that regard has
similar functionality to a TRST pin. When the pin is driven
high, the JTAG TAP controller is enabled. This is also true
Figure 9. ispJTAG Device Programming Interface
TDO
TDI
TMS
TCK
ispJTAG
Programming
Interface
EPEN
ispGDX
160V/VA
Device
ispLSI
Device
ispMACH
Device
25
ispGDX
160V/VA
Device
ispGDX
160V/VA
Device
Specifications ispGDX160V/VA
Boundary Scan
The ispGDXV/VA devices provide IEEE1149.1a test
capability and ISP programming through a standard
Boundary Scan Test Access Port (TAP) interface.
allows customers using boundary scan test to have full
test capability with only a single BSDL file.
The ispGDXV/VA devices are identified by the 32-bit
JTAG IDCODE register. The device ID assignments are
listed in Table 4.
The boundary scan circuitry on the ispGDXV/VA Family
operates independently of the programmed pattern. This
Figure 10. Boundary Scan Register Circuit for I/O Pins
HIGHZ
EXTEST
SCANIN
(from previous
cell
BSCAN
Registers
BSCAN
Latches
D
D
Q
TOE
Normal
Function
OE
Q
0
1
EXTEST
PROG_MODE
Normal
Function
Shift DR
D
Q
D
Q
Clock DR
D
0
I/O Pin
1
Q
SCANOUT
(to next cell)
Update DR
Reset
Table 3. I/O Shift Register Order
DEVICE
ispGDX160V/VA
I/O SHIFT REGISTER ORDER
TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B20 .. B39, I/O C0 .. C39, I/O D0 .. D19, I/O B19 .. B0,
I/O A39.. A0, I/O D39 .. D20, TDO
I/O Shift Reg Order/ispGDXVA
Table 4. ispGDX160V/VA Device ID Codes
DEVICE
32-BIT BOUNDARY SCAN ID CODE
ispGDX160V
0000, 0000, 0011, 0101, 0011, 0000, 0100, 0011
ispGDX160VA
0001, 0000, 0011, 0101, 0011, 0000, 0100, 0011
ID Code/GDX160V/VA
26
Specifications ispGDX160V/VA
Boundary Scan (Continued)
The ispJTAG programming is accomplished by executing Lattice private instructions under the Boundary Scan
State Machine.
Downlowad (ispDCD™), ispCODE ‘C’ routines or any
third-party programmers. Contact Lattice Technical Support to obtain more detailed programming information.
Details of the programming sequence are transparent to
the user and are handled by Lattice ISP Daisy Chain
Figure 11. Boundary Scan Register Circuit for Input-Only Pins
Input Pin
SCANIN
(from previous
cell
D
SCANOUT
(to next cell)
Q
Shift DR
Clock DR
Figure 12. Boundary Scan State Machine
1
0
Test-Logic-Reset
0
1
Run-Test/Idle
Select-DR-Scan
0
1
Capture-DR
0
Shift-DR
0
1
Exit1-DR
1
0
Pause-DR
1
1
Select-IR-Scan
0
1
Capture-IR
0
Shift-IR
0
1
Exit1-IR
1
0
Pause-IR
1
0
1
0
0
Exit2-DR
1
Update-DR
1
0
27
0
Exit2-IR
1
Update-IR
1
0
Specifications ispGDX160V/VA
Boundary Scan (Continued)
Figure 13. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
Tbtsu
Tbtch
Tbth
Tbtcl
Tbtcp
TCK
Tbtvo
Tbtco
TDO
Valid Data
Tbtcsu
Data to be
captured
Tbtoz
Valid Data
Tbtch
Data Captured
Tbtuov
Tbtuco
Data to be
driven out
Symbol
Valid Data
Parameter
Tbtuoz
Valid Data
Min
Max
Units
tbtcp
TCK [BSCAN test] clock pulse width
100
–
ns
tbtch
TCK [BSCAN test] pulse width high
50
–
ns
tbtcl
TCK [BSCAN test] pulse width low
50
–
ns
tbtsu
TCK [BSCAN test] setup time
20
–
ns
tbth
TCK [BSCAN test] hold time
25
–
ns
trf
TCK [BSCAN test] rise and fall time
50
–
mV/ns
tbtco
TAP controller falling edge of clock to valid output
–
25
ns
tbtoz
TAP controller falling edge of clock to data output disable
–
25
ns
tbtvo
TAP controller falling edge of clock to data output enable
–
25
ns
tbtcpsu
BSCAN test Capture register setup time
20
–
ns
tbtcph
BSCAN test Capture register hold time
25
–
ns
tbtuco
BSCAN test Update reg, falling edge of clock to valid output
–
50
ns
tbtuoz
BSCAN test Update reg, falling edge of clock to output disable
–
50
ns
tbtuov
BSCAN test Update reg, falling edge of clock to output enable
–
50
ns
28
Specifications ispGDX160V/VA
Signal Descriptions
Signal Name
Description
I/O
Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs,
each may be independently latched, registered or tristated. They can also each assume one other
control function (OE, CLK/CLKEN, and MUXsel as described in the text).
TOE
Test Output Enable Pin – This pin tristates all I/P pins when a logic low is driven.
RESET
Active LOW Input Pin – Resets all I/O register outputs when LOW.
Yx/CLKENx
Input Pins –These can be either Global Clocks or Clock Enables.
EPEN
Input Pin – JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low,
JTAG TAP controller is driven to reset.
TDI
Input Pin – Serial data input during ISP programming or Boundary Scan mode.
TCK
Input Pin – Serial data clock during ISP programming or Boundary Scan mode.
TMS
Input Pin – Control input during ISP programming or Boundary Scan mode.
TDO
Output Pin – Serial data output during ISP programming or Boundary Scan mode.
GND
Ground (GND)
VCC
Vcc – Supply voltage (3.3V).
VCCIO2
Input – This pin is used if optional 2.5V output is to be used. Every I/O can independently select either
3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin
must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw
current from this supply.
NC1
No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
2. “VA” version only.
29
Specifications ispGDX160V/VA
Signal Locations: ispGDX160V/VA
Signal
208-Pin PQFP
208-Ball fpBGA
272-Ball BGA
TOE
178
D9
A12
RESET
185
A8
D10
Y0/CLKEN0
75
N8
V10
Y1/CLKEN1
76
R8
Y10
Y2/CLKEN2
180
B9
C11
Y3/CLKEN3
181
C9
A11
EPEN
183
A9
B10
TDI
81
P9
Y12
TCK
80
T9
U11
TMS
79
T8
V11
TDO
78
P8
W11
GND
6, 15, 25, 35, 44, 54, 63,
77, 91, 100, 110, 119, 129,
139, 148, 159, 168, 182,
195, 204
D4, D13, G7, G8, G9,
A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12,
G10, H7, H8, H9, H10, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10,
J7, J8, J9, J10, K7, K8, M11, M12, N4, N17, U4, U8, U13, U17
K9, K10, N4, N13
VCC
1, 17, 33, 49, 65, 89, 105,
121, 137, 153, 1561, 170,
184, 193
E131, F4, F13, L4, L13, C181, D6, D11, D15, F4, F17, K4, L17, R4, R17, U6,
M4, M13, N5, N11, N12 U10, U15
D5, D6, D12, E4
VCCIO
1561
E131
C181
NC
73, 74, 179
A10, P7, T7
A2, A6, A7, A10, A15, A19, A20, B1, B2, B4, B11,
B14, B18, B19, B20, C2, C3, C10, D2, D3, D16, E2,
E17, E19, H1, H3, H18, H20, K20, L1, N1, N3, N18
N20, T2, T4, T19, U5, U18, U19, V3, V14, V18, V19,
W1, W2, W3, W7, W10, W14, W19, W20, Y1, Y2, Y6,
Y9, Y11, Y18, Y20
1. VCC on ispGDX160V, VCCIO on ispGDX160VA.
30
Specifications ispGDX160V/VA
I/O Locations: ispGDX160V/VA (Ordered by I/O Signal Name and 208-Pin PQFP Location)
I/O
Signal
VCC
I/O A0
I/O A1
I/O A2
I/O A3
GND
I/O A4
I/O A5
I/O A6
I/O A7
I/O A8
I/O A9
I/O A10
I/O A11
GND
I/O A12
VCC
I/O A13
I/O A14
I/O A15
I/O A16
I/O A17
I/O A18
I/O A19
GND
I/O A20
I/O A21
I/O A22
I/O A23
I/O A24
I/O A25
I/O A26
VCC
I/O A27
GND
I/O A28
I/O A29
I/O A30
I/O A31
I/O A32
I/O A33
I/O A34
I/O A35
GND
I/O A36
I/O A37
I/O A38
I/O A39
VCC
I/O B0
I/O B1
I/O B2
I/O B3
GND
I/O B4
I/O B5
I/O B6
I/O B7
I/O B8
I/O B9
I/O B10
I/O B11
GND
I/O B12
VCC
Control
Signal
I/O
208
208 272
PQFP fpBGA BGA Signal
CLK/CLKEN
OE
MUXsel1
MUXsel2
2
3
4
5
B2
B1
C2
A1
E4
C1
D1
E3
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
7
8
9
10
11
12
13
14
C1
D3
D2
D1
E3
E2
E1
F3
E1
F3
G4
F2
F1
G3
G2
G1
CLK/CLKEN
16
F2
H2
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
18
19
20
21
22
23
24
F1
G4
G2
G3
G1
H4
H2
J4
J3
J2
J1
K2
K3
K1
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
26
27
28
29
30
31
32
H3
H1
J1
J3
J2
J4
K1
L2
L3
L4
M1
M2
M3
M4
MUXsel2
34
K3
N2
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
36
37
38
39
40
41
42
43
K2
K4
L1
L2
L3
M1
M2
M3
P1
P2
R1
P3
R2
T1
P4
R3
CLK/CLKEN
OE
MUXsel1
MUXsel2
45
46
47
48
N1
N2
N3
P1
U1
T3
U2
V1
CLK/CLKEN
OE
MUXsel1
MUXsel2
50
51
52
53
P2
R1
R2
T1
U3
V2
W4
V4
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
55
56
57
58
59
60
61
62
P3
T2
R3
P4
T3
R4
T4
P5
Y3
Y4
V5
W5
Y5
V6
U7
W6
CLK/CLKEN
64
R5
V7
I/O B13
I/O B14
I/O B15
I/O B16
I/O B17
I/O B18
I/O B19
GND
I/O B20
I/O B21
I/O B22
I/O B23
I/O B24
I/O B25
I/O B26
VCC
I/O B27
GND
I/O B28
I/O B29
I/O B30
I/O B31
I/O B32
I/O B33
I/O B34
I/O B35
GND
I/O B36
I/O B37
I/O B38
I/O B39
VCC
I/O C0
I/O C1
I/O C2
I/O C3
GND
I/O C4
I/O C5
I/O C6
I/O C7
I/O C8
I/O C9
I/O C10
I/O C11
GND
I/O C12
VCC
I/O C13
I/O C14
I/O C15
I/O C16
I/O C17
I/O C18
I/O C19
GND
I/O C20
I/O C21
I/O C22
I/O C23
I/O C24
I/O C25
I/O C26
VCC
I/O C27
NOTE: VCC and GND Pads Shown for Reference,
1VCC
Control
Signal
208
208 272
I/O
PQFP fpBGA BGA Signal
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
66
67
68
69
70
71
72
N6
T5
R6
P6
T6
N7
R7
Y7
V8
W8
Y8
U9
V9
W9
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
82
83
84
85
86
87
88
R9
N9
T10
P10
R10
N10
T11
W12
V12
U12
Y13
W13
V13
Y14
MUXsel2
90
P11
Y15
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
92
93
94
95
96
97
98
99
R11
T12
P12
R12
T13
R13
T14
P13
W15
Y16
U14
V15
W16
Y17
V16
W17
CLK/CLKEN
OE
MUXsel1
MUXsel2
101
102
103
104
R14
T15
T16
R15
U16
V17
W18
Y19
CLK/CLKEN
OE
MUXsel1
MUXsel2
106
107
108
109
P14
P15
R16
N14
T17
V20
U20
T18
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK
OE
MUXsel1
MUXsel2
111
112
113
114
115
116
117
118
P16
N15
N16
M14
M15
M16
L15
L14
T20
R18
P17
R19
R20
P18
P19
P20
CLK/CLKEN
120
L16
N19
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
122
123
124
125
126
127
128
K13
K15
K14
K16
J13
J15
J14
M17
M18
M19
M20
L19
L18
L20
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
130
131
132
133
134
135
136
J16
H14
H16
H15
H13
G16
G14
K19
K18
K17
J20
J19
J18
J17
MUXsel2
138
G15
H19
in ispGDX160V
31
Control
Signal
GND
I/O C28
CLK/CLKEN
I/O C29
OE
I/O C30
MUXsel1
I/O C31
MUXsel2
I/O C32
CLK/CLKEN
I/O C33
OE
I/O C34
MUXsel1
I/O C35
MUXsel2
GND
I/O C36
CLK/CLKEN
I/O C37
OE
I/O C38
MUXsel1
I/O C39
MUXsel2
VCC
I/O D0
CLK/CLKEN
I/O D1
OE
VCC/VCCIO1
I/O D2
MUXsel1
I/O D3
MUXsel2
GND
I/O D4
CLK/CLKEN
I/O D5
OE
I/O D6
MUXsel1
I/O D7
MUXsel2
I/O D8
CLK/CLKEN
I/O D9
OE
I/O D10
MUXsel1
I/O D11
MUXsel2
GND
I/O D12
CLK/CLKEN
VCC
I/O D13
OE
I/O D14
MUXsel1
I/O D15
MUXsel2
I/O D16
CLK/CLKEN
I/O D17
OE
I/O D18
MUXsel1
I/O D19
MUXsel2
GND
VCC
I/O D20
CLK/CLKEN
I/O D21
OE
I/O D22
MUXsel1
I/O D23
MUXsel2
I/O D24
CLK/CLKEN
I/O D25
OE
I/O D26
MUXsel1
VCC
I/O D27
MUXsel2
GND
I/O D28
CLK/CLKEN
I/O D29
OE
I/O D30
MUXsel1
I/O D31
MUXsel2
I/O D32
CLK/CLKEN
I/O D33
OE
I/O D34
MUXsel1
I/O D35
MUXsel2
GND
I/O D36
CLK/CLKEN
I/O D37
OE
I/O D38
MUXsel1
I/O D39
MUXsel2
208
208 272
PQFP fpBGA BGA
140
141
142
143
144
145
146
147
G13
F16
F14
F15
E16
E14
E15
D16
G20
G19
F20
G18
F19
E20
G17
F18
149
150
151
152
C16
D15
D14
C15
D20
E18
D19
C20
154
155
B16
A16
D18
C19
157
158
B15
A15
B17
C17
160
161
162
163
164
165
166
167
C14
B14
A14
C13
B13
A13
C12
B12
A18
A17
C16
B16
A16
C15
D14
B15
169
D11
C14
171
172
173
174
175
176
177
A12
C11
B11
D10
A11
B10
C10
A14
C13
B13
A13
D12
C12
B12
186
187
188
189
190
191
192
C8
B8
D8
A7
C7
B7
D7
A9
B9
C9
D9
A8
B8
C8
194
A6
B7
196
197
198
199
200
201
202
203
C6
B6
A5
C5
B5
A4
B4
C4
C7
B6
A5
D7
C6
B5
A4
C5
205
206
207
208
A3
C3
B3
A2
A3
D5
C4
B3
Specifications ispGDX160V/VA
I/O Locations: ispGDX160V/VA (Ordered by 208-Ball BGA Location)
I/O
Signal
Control
Signal
I/O
208
208 272
PQFP fpBGA BGA Signal
Control
Signal
208
208 272
I/O
PQFP fpBGA BGA Signal
Control
Signal
208
208 272
PQFP fpBGA BGA
I/O A3
MUXsel2
5
A1
E3
I/O A9
OE
12
E2
G3
I/O C8
CLK
115
M15
R20
I/O D39
MUXsel2
208
A2
B3
I/O A8
CLK/CLK_EN
11
E3
F1
I/O C9
OE
116
M16
P18
I/O D36
CLK/CLKEN
205
A3
A3
I/O C33
OE
145
E14
E20
I/O A36
CLK/CLKEN
45
N1
U1
I/O D33
OE
201
A4
B5
I/O C34
MUXsel1
146
E15
G17
I/O A37
OE
46
N2
T3
I/O D30
MUXsel1
198
A5
A5
I/O C32
CLK/CLKEN
144
E16
F19
I/O A38
MUXsel1
47
N3
U2
I/O D27
MUXsel2
194
A6
B7
I/O A13
OE
18
F1
J4
I/O B13
OE
66
N6
Y7
I/O D23
MUXsel2
189
A7
D9
I/O A12
CLK/CLKEN
16
F2
H2
I/O B18
MUXsel1
71
N7
V9
I/O D17
OE
175
A11
D12
I/O A11
MUXsel2
14
F3
G1
I/O B21
OE
83
N9
V12
I/O D13
OE
171
A12
A14
I/O C30
MUXsel1
142
F14
F20
I/O B25
OE
87
N10
V13
I/O D9
OE
165
A13
C15
I/O C31
MUXsel2
143
F15
G18
I/O C3
MUXsel2
109
N14
T18
I/O D6
MUXsel1
162
A14
C16
I/O C29
OE
141
F16
G19
I/O C5
OE
112
N15
R18
I/O D3
MUXsel2
158
A15
C17
I/O A17
OE
22
G1
K2
I/O C6
MUXsel1
113
N16
P17
I/O D1
OE
155
A16
C19
I/O A15
MUXsel2
20
G2
J2
I/O A39
MUXsel2
48
P1
V1
I/O A1
OE
3
B1
C1
I/O A16
CLK/CLKEN
21
G3
J1
I/O B0
CLK/CLKEN
50
P2
U3
I/O A0
CLK/CLKEN
2
B2
E4
I/O A14
MUXsel1
19
G4
J3
I/O B4
CLK/CLKEN
55
P3
Y3
MUXsel1
207
B3
C4
I/O C28
CLK/CLKEN
140
G13
G20
I/O B7
MUXsel2
58
P4
W5
I/O D34
MUXsel1
202
B4
A4
I/O C26
MUXsel1
136
G14
J17
I/O B11
MUXsel2
62
P5
W6
I/O D32
CLK/CLKEN
200
B5
C6
I/O C27
MUXsel2
138
G15
H19
I/O B16
CLK/CLKEN
69
P6
Y8
I/O D29
OE
197
B6
B6
I/O C25
OE
135
G16
J18
I/O B23
MUXsel2
85
P10
Y13
I/O D25
OE
191
B7
B8
I/O A21
OE
27
H1
L3
I/O B27
MUXsel2
90
P11
Y15
I/O D21
OE
187
B8
B9
I/O A19
MUXsel2
24
H2
K1
I/O B30
MUXsel1
94
P12
U14
W17
I/O D38
I/O D18
MUXsel1
176
B10
C12
I/O A20
CLK/CLKEN
26
H3
L2
I/O B35
MUXsel2
99
P13
I/O D15
MUXsel2
173
B11
B13
I/O A18
MUXsel1
23
H4
K3
I/O C0
CLK/CLKEN
106
P14
T17
I/O D11
MUXsel2
167
B12
B15
I/O C24
CLK/CLKEN
134
H13
J19
I/O C1
OE
107
P15
V20
I/O D8
CLK/CLKEN
164
B13
A16
I/O C21
OE
131
H14
K18
I/O C4
CLK/CLKEN
111
P16
T20
I/O D5
OE
161
B14
A17
I/O C23
MUXsel2
133
H15
J20
I/O B1
OE
51
R1
V2
I/O D2
MUXsel1
157
B15
B17
I/O C22
MUXsel1
132
H16
K17
I/O B2
MUXsel1
52
R2
W4
I/O D0
CLK/CLKEN
154
B16
D18
I/O A22
MUXsel1
28
J1
L4
I/O B6
MUXsel1
57
R3
V5
I/O A4
CLK/CLKEN
7
C1
E1
I/O A24
CLK/CLKEN
30
J2
M2
I/O B9
OE
60
R4
V6
I/O A2
MUXsel1
4
C2
D1
I/O A23
MUXsel2
29
J3
M1
I/O B12
CLK/CLKEN
64
R5
V7
I/O D37
OE
206
C3
D5
I/O A25
OE
31
J4
M3
I/O B15
MUXsel2
68
R6
W8
I/O D35
MUXsel2
203
C4
C5
I/O C17
OE
126
J13
L19
I/O B19
MUXsel2
72
R7
W9
I/O D31
MUXsel2
199
C5
D7
I/O C19
MUXsel2
128
J14
L20
I/O B20
CLK/CLKEN
82
R9
W12
I/O D28
CLK/CLKEN
196
C6
C7
I/O C18
MUXsel1
127
J15
L18
I/O B24
CLK/CLKEN
86
R10
W13
I/O D24
CLK/CLKEN
190
C7
A8
I/O C20
CLK/CLKEN
130
J16
K19
I/O B28
CLK/CLKEN
92
R11
W15
I/O D20
CLK/CLKEN
186
C8
A9
I/O A26
MUXsel1
32
K1
M4
I/O B31
MUXsel2
95
R12
V15
I/O D19
MUXsel2
177
C10
B12
I/O A28
CLK/CLKEN
36
K2
P1
I/O B33
OE
97
R13
Y17
I/O D14
MUXsel1
172
C11
C13
I/O A27
MUXsel2
34
K3
N2
I/O B36
CLK/CLKEN
101
R14
U16
I/O D10
MUXsel1
166
C12
D14
I/O A29
OE
37
K4
P2
I/O B39
MUXsel2
104
R15
Y19
I/O D7
MUXsel2
163
C13
B16
I/O C13
OE
122
K13
M17
I/O C2
MUXsel1
108
R16
U20
I/O D4
CLK/CLKEN
160
C14
A18
I/O C15
MUXsel2
124
K14
M19
I/O B3
MUXsel2
53
T1
V4
I/O C39
MUXsel2
152
C15
C20
I/O C14
MUXsel1
123
K15
M18
I/O B5
OE
56
T2
Y4
I/O C36
CLK/CLKEN
149
C16
D20
I/O C16
CLK/CLKEN
125
K16
M20
I/O B8
CLK/CLKEN
59
T3
Y5
I/O A7
MUXsel2
10
D1
F2
I/O A30
MUXsel1
38
L1
R1
I/O B10
MUXsel1
61
T4
U7
I/O A6
MUXsel1
9
D2
G4
I/O A31
MUXsel2
39
L2
P3
I/O B14
MUXsel1
67
T5
V8
I/O A5
OE
8
D3
F3
I/O A32
CLK/CLKEN
40
L3
R2
I/O B17
OE
70
T6
U9
I/O D26
MUXsel1
192
D7
C8
I/O C11
MUXsel2
118
L14
P20
I/O B22
MUXsel1
84
T10
U12
I/O D22
MUXsel1
188
D8
C9
I/O C10
MUXsel1
117
L15
P19
I/O B26
MUXsel1
88
T11
Y14
I/O D16
CLK/CLKEN
174
D10
A13
I/O C12
CLK/CLKEN
120
L16
N19
I/O B29
OE
93
T12
Y16
I/O D12
CLK/CLKEN
169
D11
C14
I/O A33
OE
41
M1
T1
I/O B32
CLK/CLKEN
96
T13
W16
I/O C38
MUXsel1
151
D14
D19
I/O A34
MUXsel1
42
M2
P4
I/O B34
MUXsel1
98
T14
V16
I/O C37
OE
150
D15
E18
I/O A35
MUXsel2
43
M3
R3
I/O B37
OE
102
T15
V17
I/O C35
MUXsel2
147
D16
F18
I/O C7
MUXsel2
114
M14
R19
I/O B38
MUXsel1
103
T16
W18
I/O A10
MUXsel1
13
E1
G2
32
Specifications ispGDX160V/VA
I/O Locations: ispGDX160V/VA (Ordered by 272-Ball BGA Location)
I/O
208
208 272
PQFP fpBGA BGA Signal
Control
Signal
208
208 272
I/O
PQFP fpBGA BGA Signal
I/O
Signal
Control
Signal
I/O D36
CLK/CLKEN
205
A3
A3
I/O C32
CLK/CLKEN
144
E16
F19
I/O C5
OE
112
N15
I/O D34
MUXsel1
202
B4
A4
I/O C30
MUXsel1
142
F14
F20
I/O C7
MUXsel2
114
M14
R19
I/O D30
MUXsel1
198
A5
A5
I/O A11
MUXsel2
14
F3
G1
I/O C8
CLK
115
M15
R20
I/O D24
CLK/CLKEN
190
C7
A8
I/O A10
MUXsel1
13
E1
G2
I/O A33
OE
41
M1
T1
I/O D20
CLK/CLKEN
186
C8
A9
I/O A9
OE
12
E2
G3
I/O A37
OE
46
N2
T3
I/O D16
CLK/CLKEN
174
D10
A13
I/O A6
MUXsel1
9
D2
G4
I/O C0
CLK/CLKEN
106
P14
T17
I/O D13
OE
171
A12
A14
I/O C34
MUXsel1
146
E15
G17
I/O C3
MUXsel2
109
N14
T18
I/O D8
CLK/CLKEN
164
B13
A16
I/O C31
MUXsel2
143
F15
G18
I/O C4
CLK/CLKEN
111
P16
T20
I/O D5
OE
161
B14
A17
I/O C29
OE
141
F16
G19
I/O A36
CLK/CLKEN
45
N1
U1
I/O D4
CLK/CLKEN
160
C14
A18
I/O C28
CLK/CLKEN
140
G13
G20
I/O A38
MUXsel1
47
N3
U2
I/O D39
MUXsel2
208
A2
B3
I/O A12
CLK/CLKEN
16
F2
H2
I/O B0
CLK/CLKEN
50
P2
U3
I/O D33
OE
201
A4
B5
I/O C27
MUXsel2
138
G15
H19
I/O B10
MUXsel1
61
T4
U7
I/O D29
OE
197
B6
B6
I/O A16
CLK/CLKEN
21
G3
J1
I/O B17
OE
70
T6
U9
I/O D27
MUXsel2
194
A6
B7
I/O A15
MUXsel2
20
G2
J2
I/O B22
MUXsel1
84
T10
U12
I/O D25
OE
191
B7
B8
I/O A14
MUXsel1
19
G4
J3
I/O B30
MUXsel1
94
P12
U14
I/O D21
OE
187
B8
B9
I/O A13
OE
18
F1
J4
I/O B36
CLK/CLKEN
101
R14
U16
I/O D19
MUXsel2
177
C10
B12
I/O C26
MUXsel1
136
G14
J17
I/O C2
MUXsel1
108
R16
U20
I/O D15
MUXsel2
173
B11
B13
I/O C25
OE
135
G16
J18
I/O A39
MUXsel2
48
P1
V1
I/O D11
MUXsel2
167
B12
B15
I/O C24
CLK/CLKEN
134
H13
J19
I/O B1
OE
51
R1
V2
V4
Control
Signal
208
208 272
PQFP fpBGA BGA
R18
I/O D7
MUXsel2
163
C13
B16
I/O C23
MUXsel2
133
H15
J20
I/O B3
MUXsel2
53
T1
I/O D2
MUXsel1
157
B15
B17
I/O A19
MUXsel2
24
H2
K1
I/O B6
MUXsel1
57
R3
V5
I/O A1
OE
3
B1
C1
I/O A17
OE
22
G1
K2
I/O B9
OE
60
R4
V6
I/O D38
MUXsel1
207
B3
C4
I/O A18
MUXsel1
23
H4
K3
I/O B12
CLK/CLKEN
64
R5
V7
I/O D35
MUXsel2
203
C4
C5
I/O C22
MUXsel1
132
H16
K17
I/O B14
MUXsel1
67
T5
V8
I/O D32
CLK/CLKEN
200
B5
C6
I/O C21
OE
131
H14
K18
I/O B18
MUXsel1
71
N7
V9
I/O D28
CLK/CLKEN
196
C6
C7
I/O C20
CLK/CLKEN
130
J16
K19
I/O B21
OE
83
N9
V12
I/O D26
MUXsel1
192
D7
C8
I/O A20
CLK/CLKEN
26
H3
L2
I/O B25
OE
87
N10
V13
I/O D22
MUXsel1
188
D8
C9
I/O A21
OE
27
H1
L3
I/O B31
MUXsel2
95
R12
V15
I/O D18
MUXsel1
176
B10
C12
I/O A22
MUXsel1
28
J1
L4
I/O B34
MUXsel1
98
T14
V16
I/O D14
MUXsel1
172
C11
C13
I/O C18
MUXsel1
127
J15
L18
I/O B37
OE
102
T15
V17
I/O D12
CLK/CLKEN
169
D11
C14
I/O C17
OE
126
J13
L19
I/O C1
OE
107
P15
V20
I/O D9
OE
165
A13
C15
I/O C19
MUXsel2
128
J14
L20
I/O B2
MUXsel1
52
R2
W4
I/O D6
MUXsel1
162
A14
C16
I/O A23
MUXsel2
29
J3
M1
I/O B7
MUXsel2
58
P4
W5
I/O D3
MUXsel2
158
A15
C17
I/O A24
CLK/CLKEN
30
J2
M2
I/O B11
MUXsel2
62
P5
W6
I/O D1
OE
155
A16
C19
I/O A25
OE
31
J4
M3
I/O B15
MUXsel2
68
R6
W8
I/O C39
MUXsel2
152
C15
C20
I/O A26
MUXsel1
32
K1
M4
I/O B19
MUXsel2
72
R7
W9
I/O A2
MUXsel1
4
C2
D1
I/O C13
OE
122
K13
M17
I/O B20
CLK/CLKEN
82
R9
W12
W13
I/O D37
OE
206
C3
D5
I/O C14
MUXsel1
123
K15
M18
I/O B24
CLK/CLKEN
86
R10
I/O D31
MUXsel2
199
C5
D7
I/O C15
MUXsel2
124
K14
M19
I/O B28
CLK/CLKEN
92
R11
W15
I/O D23
MUXsel2
189
A7
D9
I/O C16
CLK/CLKEN
125
K16
M20
I/O B32
CLK/CLKEN
96
T13
W16
I/O D17
OE
175
A11
D12
I/O A27
MUXsel2
34
K3
N2
I/O B35
MUXsel2
99
P13
W17
I/O D10
MUXsel1
166
C12
D14
I/O C12
CLK/CLKEN
120
L16
N19
I/O B38
MUXsel1
103
T16
W18
I/O D0
CLK/CLKEN
154
B16
D18
I/O A28
CLK/CLKEN
36
K2
P1
I/O B4
CLK/CLKEN
55
P3
Y3
I/O C38
MUXsel1
151
D14
D19
I/O A29
OE
37
K4
P2
I/O B5
OE
56
T2
Y4
I/O C36
CLK/CLKEN
149
C16
D20
I/O A31
MUXsel2
39
L2
P3
I/O B8
CLK/CLKEN
59
T3
Y5
I/O A4
CLK/CLK_EN
7
C1
E1
I/O A34
MUXsel1
42
M2
P4
I/O B13
OE
66
N6
Y7
I/O A3
MUXsel2
5
A1
E3
I/O C6
MUXsel1
113
N16
P17
I/O B16
CLK/CLKEN
69
P6
Y8
I/O A0
CLK/CLKEN
2
B2
E4
I/O C9
OE
116
M16
P18
I/O B23
MUXsel2
85
P10
Y13
OE
150
D15
E18
I/O C10
MUXsel1
117
L15
P19
I/O B26
MUXsel1
88
T11
Y14
I/O C37
I/O C33
OE
145
E14
E20
I/O C11
MUXsel2
118
L14
P20
I/O B27
MUXsel2
90
P11
Y15
I/O A8
CLK/CLKEN
11
E3
F1
I/O A30
MUXsel1
38
L1
R1
I/O B29
OE
93
T12
Y16
I/O A7
MUXsel2
10
D1
F2
I/O A32
CLK/CLKEN
40
L3
R2
I/O B33
OE
97
R13
Y17
I/O A5
OE
8
D3
F3
I/O A35
MUXsel2
43
M3
R3
I/O B39
MUXsel2
104
R15
Y19
MUXsel2
147
D16
F18
I/O C35
33
Specifications ispGDX160V/VA
Signal Configuration: ispGDX160V/VA
ispGDX160V/VA 272-Ball BGA Signal Diagram
20
19
18
17
16
15
14
13
A
NC1
NC1
I/O
D4
I/O
D5
I/O
D8
NC1
I/O
D13
Y3/
I/O
1
D16 TOE CLKEN3 NC
B
NC1
NC1
NC1
I/O
D2
I/O
D7
I/O
D11
NC1
I/O
D15
I/O
D19
C
I/O
C39
I/O VCCIO I/O
D1 VCC2 D3
I/O
D6
I/O
D9
I/O
D12
I/O
D14
Y2/
I/O
NC1
D18 CLKEN2
D
I/O
C36
I/O
C38
I/O
D0
GND NC1
E
I/O
C33
NC1
I/O
C37
NC1
F
I/O
C30
I/O
C32
I/O
C35 VCC
G
I/O
C28
I/O
C29
I/O
C31
H
NC1
I/O
C27
NC1 GND
J
I/O
C23
I/O
C24
I/O
C25
I/O
C26
GND GND GND GND
I/O
A13
K
NC1
I/O
C20
I/O
C21
I/O
C22
L
I/O
C19
I/O
C17
M
I/O
C16
N
VCC
12
11
10
9
8
7
6
5
4
3
I/O
D20
I/O
D24
NC1
NC1
I/O
D30
I/O
D34
I/O
D36
NC1 GND
A
I/O
NC1 EPEN D21
I/O
D25
I/O
D27
I/O
D29
I/O
D33
NC1
I/O
D39
NC1
NC1
B
I/O
D26
I/O
D28
I/O
D32
I/O
D35
I/O
D38
NC1
NC1
I/O
A1
C
I/O
I/O
I/O
1
D23 GND D31 VCC D37 GND NC
NC1
I/O
A2
D
I/O
I/O
GND
VCC
D10
D17
RESET
I/O
D22
2
1
I/O
A0
I/O
A3
NC1
I/O
A4
E
VCC
I/O
A5
I/O
A7
I/O
A8
F
I/O
A6
I/O
A9
I/O
A10
I/O
A11
G
GND NC1
I/O
A12
NC1
H
I/O
A14
I/O
A15
I/O
A16
J
GND GND GND GND
I/O
VCC A18
I/O
A17
I/O
A19
K
I/O
C18 VCC
GND GND GND GND
I/O
A22
I/O
A21
I/O
A20
NC1
L
I/O
C15
I/O
C14
GND GND GND GND
I/O
A26
I/O
A25
I/O
A24
I/O
A23
M
NC1
I/O
C12
NC1 GND
GND NC1
I/O
A27
NC1
N
P
I/O
C11
I/O
C10
I/O
C9
I/O
C6
I/O
A31
I/O
A29
I/O
A28
P
R
I/O
C8
I/O
C7
I/O
C5
VCC
I/O
VCC A35
I/O
A32
I/O
A30
R
T
I/O
C4
NC1
I/O
C3
I/O
C0
NC1
I/O
A37
NC1
I/O
A33
T
U
I/O
C2
NC1
I/O
I/O
I/O
NC1 GND B36 VCC B30 GND B22 TCK
I/O
I/O
VCC B17 GND B10 VCC NC1 GND
I/O
B0
I/O
A38
I/O
A36
U
V
I/O
C1
NC1
NC1
I/O
B37
I/O
B34
I/O
B31
NC1
I/O
B25
I/O
I/O
Y0/
B21 TMS CLKEN0 B18
I/O
B14
I/O
B12
I/O
B9
I/O
B6
I/O
B3
NC1
I/O
B1
I/O
A39
V
W
NC1
NC1
I/O
B38
I/O
B35
I/O
B32
I/O
B28
NC1
I/O
B24
I/O
B20 TDO
I/O
B19
I/O
B15
NC1
I/O
B11
I/O
B7
I/O
B2
NC1
NC1
NC1
W
Y
NC1
I/O
B39
NC1
I/O
B33
I/O
B29
I/O
B27
I/O
B26
I/O
B23
TDI
NC1 CLKEN1 NC1
I/O
B16
I/O
B13
NC1
I/O
B8
I/O
B5
I/O
B4
NC1
NC1
Y
20
19
18
17
16
15
14
13
12
11
8
7
6
5
4
3
2
1
ispGDX160V/VA
I/O
C34
Bottom View
I/O
C13
I/O
A34
NC1
Y1/
10
1. NCs are not to be connected to any active signals, Vcc or GND.
2. VCCIO on ispGDX160VA. VCC on ispGDX160V.
34
9
Specifications ispGDX160V/VA
Signal Configuration: ispGDX160V/VA
ispGDX160V/VA 208-Ball fpBGA Signal Diagram
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
I/O
D1
I/O
D3
I/O
D6
I/O
D9
I/O
D13
I/O
D17
NC
I/O
D23
I/O
D27
I/O
D30
I/O
D33
I/O
D36
I/O
D39
I/O
A3
A
B
I/O
D0
I/O
D2
I/O
D5
I/O
D8
I/O
D11
I/O
D15
Y2/
I/O
I/O
D18 CLKEN2 D21
I/O
D25
I/O
D29
I/O
D32
I/O
D34
I/O
D38
I/O
A0
I/O
A1
B
C
I/O
C36
I/O
C39
I/O
D4
I/O
D7
I/O
D10
I/O
D14
Y3/
I/O
I/O
D19 CLKEN3 D20
I/O
D24
I/O
D28
I/O
D31
I/O
D35
I/O
D37
I/O
A2
I/O
A4
C
D
I/O
C35
I/O
C37
I/O
C38
GND
VCC
I/O
D12
I/O
D16
I/O
D26
VCC
VCC
GND
I/O
A5
I/O
A6
I/O
A7
D
E
I/O
C32
I/O
C34
I/O VCCIO/
C33 VCC2
ispGDX160V/VA
VCC
I/O
A8
I/O
A9
I/O
A10
E
F
I/O
C29
I/O
C31
I/O
C30
VCC
Bottom View
VCC
I/O
A11
I/O
A12
I/O
A13
F
G
I/O
C25
I/O
C27
I/O
C26
I/O
C28
GND
GND
GND
GND
I/O
A14
I/O
A16
I/O
A15
I/O
A17
G
H
I/O
C22
I/O
C23
I/O
C21
I/O
C24
GND
GND
GND
GND
I/O
A18
I/O
A20
I/O
A19
I/O
A21
H
J
I/O
C20
I/O
C18
I/O
C19
I/O
C17
GND
GND
GND
GND
I/O
A25
I/O
A23
I/O
A24
I/O
A22
J
K
I/O
C16
I/O
C14
I/O
C15
I/O
C13
GND
GND
GND
GND
I/O
A29
I/O
A27
I/O
A28
I/O
A26
K
L
I/O
C12
I/O
C10
I/O
C11
VCC
VCC
I/O
A32
I/O
A31
I/O
A30
L
M
I/O
C9
I/O
C8
I/O
C7
VCC
VCC
I/O
A35
I/O
A34
I/O
A33
M
N
I/O
C6
I/O
C5
I/O
C3
GND
VCC
VCC
I/O
B25
I/O
I/O
Y0/
B21 CLKEN0 B18
P
I/O
C4
I/O
C1
I/O
C0
I/O
B35
I/O
B30
I/O
B27
I/O
B23
TDI
R
I/O
C2
I/O
B39
I/O
B36
I/O
B33
I/O
B31
I/O
B28
I/O
B24
Y1/
I/O
I/O
B20 CLKEN1 B19
T
I/O
B38
I/O
B37
I/O
B34
I/O
B32
I/O
B29
I/O
B26
I/O
B22
TCK
TMS
NC
16
15
14
13
12
11
10
9
8
7
1 EPEN RESET
I/O
D22
TOE
TDO
1. NCs are not to be connected to any active signals, Vcc or GND.
2. VCCIO on ispGDX160VA. VCC on ispGDX160V.
35
NC
1
1
I/O
B13
VCC
GND
I/O
A38
I/O
A37
I/O
A36
N
I/O
B16
I/O
B11
I/O
B7
I/O
B4
I/O
B0
I/O
A39
P
I/O
B15
I/O
B12
I/O
B9
I/O
B6
I/O
B2
I/O
B1
R
I/O
B17
I/O
B14
I/O
B10
I/O
B8
I/O
B5
I/O
B3
T
6
5
4
3
2
1
Specifications ispGDX160V/VA
Pin Configuration: ispGDX160V/VA
Control
Data
VCC
I/O A 0
I/O A 1
I/O A 2
I/O A 3
GND
I/O A 4
I/O A 5
I/O A 6
I/O A 7
I/O A 8
I/O A 9
I/O A 10
I/O A 11
GND
I/O A 12
VCC
I/O A 13
I/O A 14
I/O A 15
I/O A 16
I/O A 17
I/O A 18
I/O A 19
GND
I/O A 20
I/O A 21
I/O A 22
I/O A 23
I/O A 24
I/O A 25
I/O A 26
VCC
I/O A 27
GND
I/O A 28
I/O A 29
I/O A 30
I/O A 31
I/O A 32
I/O A 33
I/O A 34
I/O A 35
GND
I/O A 36
I/O A 37
I/O A 38
I/O A 39
VCC
I/O B 0
I/O B 1
I/O B 2
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
Data
—
CLK/CLKEN
OE
MUXsel1
MUXsel2
—
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
—
CLK/CLKEN
—
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
—
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
—
MUXsel2
—
CLK/CLKEN
OE
MUXsel1
MUXsel2
CLK/CLKEN
OE
MUXsel1
MUXsel2
—
CLK/CLKEN
OE
MUXsel1
MUXsel2
—
CLK/CLKEN
OE
MUXsel1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
ispGDX160V/VA
Top View
Data
Control
I/O B 3
MUXsel2
GND
—
I/O B 4
CLK/CLKEN
I/O B 5
OE
I/O B 6
MUXsel1
I/O B 7
MUXsel2
I/O B 8
CLK/CLKEN
I/O B 9
OE
I/O B 10
MUXsel1
I/O B 11
MUXsel2
GND
—
I/O B 12
CLK/CLKEN
VCC
—
I/O B 13
OE
I/O B 14
MUXsel1
I/O B 15
MUXsel2
I/O B 16
CLK/CLKEN
I/O B 17
OE
I/O B 18
MUXsel1
I/O B 19
MUXsel2
1NC
—
1NC
—
CLK_EN0/Y0
—
CLK_EN1/Y1
—
GND
—
TDO
—
TMS
—
TCK
—
TDI
—
I/O B 20
CLK/CLKEN
I/O B 21
OE
I/O B 22
MUXsel1
I/O B 23
MUXsel2
I/O B 24
CLK/CLKEN
I/O B 25
OE
I/O B 26
MUXsel1
VCC
—
I/O B 27
MUXsel2
GND
—
I/O B 28
CLK/CLKEN
I/O B 29
OE
I/O B 30
MUXsel1
I/O B 31
MUXsel2
I/O B 32
CLK/CLKEN
I/O B 33
OE
I/O B 34
MUXsel1
I/O B 35
MUXsel2
GND
—
I/O B 36
CLK/CLKEN
I/O B 37
OE
I/O B 38
MUXsel1
I/O B 39
MUXsel2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Control
I/O D 39
MUXsel2
I/O D 38
MUXsel1
I/O D 37
OE
I/O D 36
CLK/CLKEN
GND
—
I/O D 35
MUXsel2
I/O D 34
MUXsel1
I/O D 33
OE
I/O D 32
CLK/CLKEN
I/O D 31
MUXsel2
I/O D 30
MUXsel1
I/O D 29
OE
I/O D 28
CLK/CLKEN
GND
—
I/O D 27
MUXsel2
VCC
—
I/O D 26
MUXsel1
I/O D 25
OE
I/O D 24
CLK/CLKEN
I/O D 23
MUXsel2
I/O D 22
MUXsel1
I/O D 21
OE
I/O D 20
CLK/CLKEN
RESET
—
VCC
—
EPEN
—
GND
—
Y3/CLK_EN3
—
Y2/CLK_EN2
—
NC1
—
TOE
—
I/O D 19
MUXsel2
I/O D 18
MUXsel1
I/O D 17
OE
I/O D 16
CLK/CLKEN
I/O D 15
MUXsel2
I/O D 14
MUXsel1
I/O D 13
OE
VCC
—
I/O D 12
CLK/CLKEN
GND
—
I/O D 11
MUXsel2
I/O D 10
MUXsel1
I/O D 9
OE
I/O D 8
CLK/CLKEN
I/O D 7
MUXsel2
I/O D 6
MUXsel1
I/O D 5
OE
I/O D 4
CLK/CLKEN
GND
—
I/O D 3
MUXsel2
I/O D 2
MUXsel1
ispGDX160V/VA 208-Pin PQFP Pinout Diagram
1. No Connect Pins (NC) are not to be connected to any active signal, Vcc or GND.
2. VCCIO on ispGDX160VA. VCC on ispGDX160V.
36
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
Data
Control
VCCIO/VCC2
I/O D1
I/O D 0
VCC
I/O C 39
I/O C 38
I/O C 37
I/O C 36
GND
I/O C 35
I/O C 34
I/O C 33
I/O C 32
I/O C 31
I/O C 30
I/O C 29
I/O C 28
GND
I/O C 27
VCC
I/O C 26
I/O C 25
I/O C 24
I/O C 23
I/O C 22
I/O C 21
I/O C 20
GND
I/O C 19
I/O C 18
I/O C 17
I/O C 16
I/O C 15
I/O C 14
I/O C 13
VCC
I/O C 12
GND
I/O C 11
I/O C 10
I/O C 9
I/O C 8
I/O C 7
I/O C 6
I/O C 5
I/O C 4
GND
I/O C 3
I/O C 2
I/O C 1
I/O C 0
VCC
—
OE
CLK/CLKEN
—
MUXsel2
MUXsel1
OE
CLK/CLKEN
—
MUXsel2
MUXsel1
OE
CLK/CLKEN
MUXsel2
MUXsel1
OE
CLK/CLKEN
—
MUXsel2
—
MUXsel1
OE
CLK/CLKEN
MUXsel2
MUXsel1
OE
CLK/CLKEN
—
MUXsel2
MUXsel1
OE
CLK/CLKEN
MUXsel2
MUXsel1
OE
—
CLK/CLKEN
—
MUXsel2
MUXsel1
OE
CLK/CLKEN
MUXsel2
MUXsel1
OE
CLK/CLKEN
—
MUXsel2
MUXsel1
OE
CLK/CLKEN
—
Specifications ispGDX160V/VA
Part Number Description
ispGDX XXXXX - X XXXX X
Device Family
Grade
Blank = Commercial
I = Industrial
Device Number
160V
160VA
Speed
3 = 3.5ns Tpd
5 = 5ns Tpd
7 = 7ns Tpd
9 = 9ns Tpd
Package
Q208 = 208-Pin PQFP
B208 = 208-Ball fpBGA
B272 = 272-Ball BGA
0212/ispGDXVA
Ordering Information
COMMERCIAL
FAMILY
ispGDXVA
ispGDXV*
tpd (ns)
ORDERING NUMBER
PACKAGE
3.5
ispGDX160VA-3Q208
208-Pin PQFP
3.5
ispGDX160VA-3B208
208-Ball fpBGA
3.5
ispGDX160VA-3B272
272-Ball BGA
5
ispGDX160VA-5Q208
208-Pin PQFP
5
ispGDX160VA-5B208
208-Ball fpBGA
5
ispGDX160VA-5B272
272-Ball BGA
7
ispGDX160VA-7Q208
208-Pin PQFP
7
ispGDX160VA-7B208
208-Ball fpBGA
7
ispGDX160VA-7B272
272-Ball BGA
5
ispGDX160V-5Q208
208-Pin PQFP
5
ispGDX160V-5B208
208-Ball fpBGA
5
ispGDX160V-5B272
272-Ball BGA
7
ispGDX160V-7Q208
208-Pin PQFP
7
ispGDX160V-7B208
208-Ball fpBGA
7
ispGDX160V-7B272
272-Ball BGA
INDUSTRIAL
FAMILY
ispGDXVA
ispGDXV*
Table 2-0041A/ispGDXV/A
tpd (ns)
ORDERING NUMBER
PACKAGE
5
ispGDX160VA-5Q208I
208-Pin PQFP
5
ispGDX160VA-5B208I
208-Ball fpBGA
5
ispGDX160VA-5B272I
272-Ball BGA
7
ispGDX160VA-7Q208I
208-Pin PQFP
7
ispGDX160VA-7B208I
208-Ball fpBGA
7
ispGDX160VA-7B272I
272-Ball BGA
9
ispGDX160VA-9Q208I
208-Pin PQFP
9
ispGDX160VA-9B208I
208-Ball fpBGA
9
ispGDX160VA-9B272I
272-Ball BGA
7
ispGDX160V-7Q208I
208-Pin PQFP
Table 2-0041C/ispGDXV
*Use ispGDX160VA for new designs.
Note: The ispGDX160VA devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower,
e.g. ispGDX160VA-3B208-5I.
37