CMOS, 330 MHz Triple 10-Bit High Speed Video DAC FEATURES 330 MSPS Throughput Rate Triple 10-Bit D/A Converters Complementary Outputs DAC Output Current Range 2mA to 18.5mA 64-Lead LQFP Package FUNCTIONAL BLOCK DIAGRAM 19 ， IORP 10 DATA REGISTER 10 G9-G0 10 DATA REGISTER 10 B9-B0 10 DATA REGISTER 10 DAC DAC DAC QQ : MODE 34 1 VOLTAGE REFERENCE CIRCUIT RSET COMP 66 4 2 NOTE: Te l: 18 1. V18 must be connected to 1.8V power supply for core circuit. There are ‘VDDA’, ‘VDDC’, ‘VDDD’ and ‘DVDD’ in this group. 2. VSS must be connected to ground. There are ‘VSSA’, ‘VSSC’, ‘VSSD’ ,‘DVSS’ and OVSS33 in this group. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， PRODUCT HIGHLIGHTS 1. 330 MSPS throughput. 2. Guaranteed monotonic to 10 bits. 1 IORN IOGP IOGN IOBP POWER-DOWN VSS 51 8 R9-R0 PWD GENERAL DESCRIPTION The IT6902 is a triple high speed, digital-to-analog converter on a single monolithic chip. There are three high speed, 10-bit, video D/A converters with complementary outputs, a standard TTL input interface, and a high impedance, analog output current source. 3.3V /1.8V power supply and clock are all required to make the part functional. The IT6902 also has a Power-Down Mode. The IT6902 is fabricated in a 1.8V CMOS process and available in a 64-lead LQFP package. OVDD33 58 5 APPLICATIONS Digital Video Systems High Resolution Color Graphics Image Processing Video Signal Reconstruction 1 71 44 V18 廖 R IT6902 IOBN CMOS, 330 MHz Triple 10-Bit High Speed Video DAC 0.7 0 Resolution (Each DAC) Offset Error 0 Gain Error 0 0.77 10 Volts Volts Bits 0 LSB LSB -1 +1 LSB Differential Linearity Error -1 +1 LSB QQ : Integral Linearity Error Yes Monotonic Input Data=(3FFh) Input Data=(000h) 51 8 0.665 71 44 STATIC PERFORMANCE MAX Luminance Voltage MIN Luminance Voltage 58 5 DIGITAL AND CONTROL INPUTS Volts 0.8 Input Low Voltage, VIL 66 4 CLOCK CONTROL 34 1 2.0 Input High Voltage, VIH 330 Volts 0.2 Data and Control Hold, t2 1.5 Clock Pulsewidth High, t3 1.4 ns 1.4 ns 司 ANALOG OUTPUTS 2 公 Output Current 2 ns mA RSET=1k 6 % % of Max Luminance Voltage 技 有 1 Video Channel to Video Channel Ω ~ 100Ω 18.5 限 Video Channel to Video Channel Mismatch ns ， Clock Pulsewidth Low, t4 18 Data and Control Setup, t1 l: MHz Te fCLK ns 讯 科 Output Skew -2.5 1 2.5 % Overshoot/Undershoot -12 1 12 % 1 1 3 3 ns ns 深 圳 市 金 合 Video Noise Injection Ratio Video Channel Rise/Fall Time Maximum Settling Time After % of Max Luminance Voltage Overshoot/Undershoot POWER DISSIPATION RGB Channels Supply Current 0.5 64.5 mA Voltage Reference Supply Current 50 280 uA Digital Supply Current 0.3 3.8 mA 2 19 ， 3.3V/1.8V SPECIFICATIONS (OVDD33=3.3V±5%, VDDA=VDDC=VDDD=DVDD=1.8V±5%, RSET=100Ω, RL=37.5Ω. All specification are TA=25℃, unless otherwise noted) Parameter Min Typ Max Unit Test Conditions Min. current is measured in power-down mode. 廖 R IT6902-SPECIFICATIONS CMOS, 330 MHz Triple 10-Bit High Speed Video DAC 51 8 19 ， 廖 R dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 68.56 63.11 70.97 64.17 67.6 61.88 70.86 66.7 67.78 61.46 71 44 AC LINEARITY Spurious-Free Dynamic Range Single-Ended Output fCLK=27 MHz, fOUT=0.5 MHz fCLK=27 MHz, fOUT=1.0 MHz fCLK=48 MHz, fOUT=0.4 MHz fCLK=48 MHz, fOUT=0.9 MHz fCLK=60 MHz, fOUT=0.5 MHz fCLK=60 MHz, fOUT=1.0 MHz fCLK=80 MHz, fOUT=0.3 MHz fCLK=80 MHz, fOUT=0.7 MHz fCLK=135 MHz, fOUT=0.5 MHz fCLK=135 MHz, fOUT=1.0 MHz 3 CMOS, 330 MHz Triple 10-Bit High Speed Video DAC l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R PIN CONFIGURATION 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te Figure2. IT6902 TOP VIEW 4 CMOS, 330 MHz Triple 10-Bit High Speed Video DAC Mnemonic B9-B0 14 LDET 17,44 18,45 19 DVSS DVDD EN_DET 20 DE 21-30 G9-G0 31 32 33 OVSS OVDD CLOCK 34-43 R9-R0 46 PWD Function R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular PCB power or ground plane. Load detecting result. When EN_DET=’1’, LDET will output the load detecting result. 2 ‘1’: Detecting Rload > 50 ohm. (Plug-out) ‘0’: Detecting Rload < 50 ohm. (Plug-in) Ground. Digital I/O power supply (1.8V). Load detecting enable. ‘1’: Enable load detecting circuit to monitor plug-in (out). ‘0’: Disable load detecting circuit. Data enable. ‘1’: Enable R9-R0, G9-G0 and B9-B0 input to DAC. ‘0’: Disable data input to DAC. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular PCB power or ground plane. Ground. Digital I/O power supply (3.3 V). Clock input (TTL Compatible). The rising edge of CLOCK latches the R9-R0, G9-G0, and B9-B0 pixel. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular PCB power or ground plane. Power-down mode enable. ‘1’: Power-down mode; When in power-down mode, all functions of this chip are disabled. Reduced power consumption is available in this mode. There are no outputs in Pin 53, 54, 56, 57, 59, and 60. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， Pin No. 3-12 廖 R PIN FUNCTION DESCRIPTIONS 47,48 ‘0’:Normal mode; The chip will work correctly in normal mode. The consuming current of power-down mode and normal mode were measured in page 2 (power dissipation). BW0-BW1 1 Slew rate control inputs. Slew rate of analog output waveform can be controlled by BW0-BW1. It is controllable for trade-off between lowering EMI and output speed. “00”: slowest slew rate. ………. “11”: fastest slew rate 5 55,58,61 62 63 64 1,2,13, 15, 16 VDDC VSSC VSSD VDDD NC 19 ， IORN, IOGN, IOBN 51 8 54,57,60 Ω Ω 71 44 VDDA IORP, IOGP, IOBP QQ : 52 53,56,59 Ground of VDDA. Voltage Reference Input for DACs or Voltage Reference Output. Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1uF ceramic capacitor must be connected between COMP and VDDA. Analog power supply (1.8V) for Voltage reference circuit. Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. Differential Red, Green, and Blue Current Output. These RGB video outputs are specified to directly drive a doubly terminated 75 load. If the complementary outputs are not required, these outputs should be tied to ground. Analog power supply (1.8V) for three DACs. Ground of VDDC. Ground of VDDD. Digital power supply (1.8V) for logic circuit. Reserved. 58 5 VSSA RSET COMP 66 4 34 1 49 50 51 18 NOTES 1. IORP, IOGP, and IOBP vs. BW0-BW1 (pulse output) Te l: IORP, IOGP, and IOBP 司 ， BW[1:0]=11 技 有 限 公 BW[1:0]=10 讯 科 BW[1:0]=01 深 圳 市 金 合 BW[1:0]=00 2. When EN_DET is high and an output driver is active, the continuing presence of the load is verified by comparing the dc level at the output to an internal reference. If the load is removed then the voltage on the output pin (REDP, GREENP or BLUEP) will become twice as high for standard termination, or even higher for active termination. 6 廖 R CMOS, 330 MHz Triple 10-Bit High Speed Video DAC CMOS, 330 MHz Triple 10-Bit High Speed Video DAC (1) Plug-out RLoad=75ohm REDP 75 ohm 19 ， 廖 R 75 ohm (2) Plug-in 51 8 RLoad=37.5ohm 71 44 REDP QQ : 75 ohm 75 ohm 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 TYPICAL CONNECTION DIAGRAM 7