K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM TM Revision History History 1. Initial document. Draft Date September. 1997 Remark Preliminary 0.1 1. Changed speed bin from 167MHz to 150MHz 2. Changed DC Parameters; ICC : from 400mA to 450mA , ISB : from 60mA to 20mA ISB2 : from 50mA to 85mA November. 1997 Preliminary 0.2 1. Changed speed bin from 150MHz to 167MHz 2. Changed Power from 3.3V to 2.5V 3. Changed N.C pins to Power and ZZ Pin #14, #16, #64, #66 4. Changed some control pin names. from CEN to CKE, from BWEx to BWx 5. Modify absolute maximum ratings VDD ; from 4.0V to 3.6V, VIN ; from 4.6V to 3.6V 6. Changed DC parameters ISB ; from 20mA to 80mA, ISB2 ; from 85mA to 10mA VOL ; from 0.4V to 0.2V, VOH ; from 2.4V to 2.0V VIL ; from 0.8V to 0.7V, VIH ; from 2.0V to 1.7V 7. ADD the sleep mode timing and characteristics CKE controlled timing and CS controlled timing March. 11. 1998 Preliminary 0.3 1. Removed speed bin 167MHz 2.Changed AC parameters tHZOE ; from 4.0 to 3.5 , t HZC;from 4.0 to 3.5 at -75 tHZOE ; from 5.0 to 3.5 , t HZC;from 5.0 to 3.5 , tCL/H; 4.0 to 3.0 at -10 3.Modify Sleep Mode Waveform. Changed Sleep Mode Electrical Characteristics . tPDS ;from Max 2cycle to Min 2cycle tPUS ; from Max 2cycle to Min 2cycle April. 11. 1998 Preliminary 0.4 1.Modify from ADV to ADV at timing. 2.ADD the Trade Mark( NtRAMTM) June. 02. 1998 Preliminary 0.5 1. Changed DC parameters ISB1; from 10mA to 20mA, ISB2 ; from 10mA to 20mA Aug. 19. 1998 Preliminary 0.6 1. Changed tCD,tOE from 4.0ns to 4.2ns at -75. Sep. 28. 1998 Preliminary 0.7 1. Changed DC condition at Icc and parameters ICC ; from 420mA to 320mA at -67 , from 370mA to 300mA at -75 from 300mA to 250mA at -10. ISB ; from 70mA to 60mA at -67 , from 60mA to 50mA at -75 from 50mA to 40mA at -10. Nov. 10. 1998 Preliminary 0.8 1.Changed VOL Max value from 0.2V to 0.4V . Dec. 23. 1998 Preliminary 0.9 1. Add 119BGA(7x17 Ball Grid Array Package) . Mar. 03. 1999 Preliminary 1.0 1. Final spec release April. 01. 1999 Final 2.0 1. Add tCYC 167Mhz. Oct. 30. 1999 Final Rev. No. 0.0 The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM TM Revision History Rev. No. 3.0 History 1. Remove 119BGA package . Draft Date Nov. 19. 1999 Remark Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -2- November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM 256Kx36 & 512Kx18-Bit Pipelined NtRAMTM FEATURES GENERAL DESCRIPTION • 2.5V ±5% Power Supply. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no data contention . • Α interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • TTL-Level Three-State Outputs. •100-TQFP-1420A . The K7N803645M and K7N801845M are 9,437,184 bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N803645M and K7N801845M are implemented with SAMSUNG′s high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce. FAST ACCESS TIMES PARAMETER Symbol -16 -15 -13 -10 Unit Cycle Time tCYC 6.0 6.7 7.5 10 ns Clock Access Time tCD 3.5 3.8 4.2 5.0 ns Output Enable Access Time tOE 3.5 3.8 4.2 5.0 ns LOGIC BLOCK DIAGRAM LBO A [0:17]or A [0:18] CKE ADDRESS REGISTER A2~A17 or A2~A18 CONTROL LOGIC CLK BURST ADDRESS COUNTER A0~A1 ADV WE BWx (x=a,b,c,d or a,b) CONTROL REGISTER CS1 CS2 CS2 WRITE ADDRESS REGISTER K A′0~A′1 WRITE ADDRESS REGISTER 256Kx36 , 512Kx18 MEMORY ARRAY K DATA-IN REGISTER K DATA-IN REGISTER CONTROL LOGIC K OUTPUT REGISTER BUFFER OE ZZ 36 or 18 DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung, and its architecture and functionalities are supported by NEC and Toshiba. -3- November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM A6 A7 CS1 CS2 BWd BWc BWb BWa CS2 VDD VSS CLK WE CKE OE ADV N.C. A17 A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A4 A3 A2 A1 A0 N.C. N.C. VSS VDD N.C. N.C. A10 A11 A12 A13 A14 A15 A16 K7N803645M(256Kx36) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 VDD VDD VDD VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS VDD VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa PIN NAME SYMBOL PIN NAME A0 - A 17 Address Inputs ADV WE CLK CKE CS1 CS2 CS2 BWx OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. 32,33,34,35,36,37, 44,45,46,47,48,49, 50,81,82,83,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 SYMBOL PIN NAME TQFP PIN NO. VDD VSS N.C. Power Supply(+2.5V) Ground No Connect 14,15,16,41,65,66,91 17,40,67,90 38,39,42,43,84 DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~P d Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 VDDQ Output Power Supply (+2.5V) Output Ground 4,11,20,27,54,61,70,77 VSSQ 5,10,21,26,55,60,71,76 Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM. 2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -4- November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM A7 CS1 CS2 N.C. N.C. BWb BWa CS2 VDD VSS CLK WE CKE OE ADV N.C. A18 A8 A9 98 97 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 96 A6 99 100 Pin TQFP (20mm x 14mm) 45 46 47 48 49 50 A13 A14 A15 A16 A17 44 A11 A12 43 40 VSS N.C. 39 N.C. 42 38 N.C. N.C. 37 A0 41 36 A1 VDD 35 A2 33 A4 34 32 A3 31 K7N801845M(512Kx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb8 DQb7 VSSQ VDDQ DQb6 DQb5 VDD VDD VDD VSS DQb4 DQb3 VDDQ VSSQ DQb2 DQb1 DQb0 N.C. VSSQ VDDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 N.C. N.C. VDDQ VSSQ N.C. DQa0 DQa1 DQa2 VSSQ VDDQ DQa3 DQa4 VSS VDD VDD ZZ DQa5 DQa6 VDDQ VSSQ DQa7 DQa8 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A0 - A 18 Address Inputs ADV WE CLK CKE CS1 CS2 CS2 BWx OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37, 44,45,46,47,48,49,50, 80,81,82,83,99,100 85 88 89 87 98 97 92 93,94 86 64 31 PIN NAME TQFP PIN NO. VDD VSS N.C. Power Supply(+2.5V) Ground No Connect 14,15,16,41,65,66,91 17,40,67,90 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,84,95,96 DQa0~a8 DQb0~b8 Data Inputs/Outputs 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 VDDQ Output Power Supply (+2.5V) Output Ground 4,11,20,27,54,61,70,77 VSSQ 5,10,21,26,55,60,71,76 Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM. 2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -5- November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM FUNCTION DESCRIPTION The K7N803645M and K7N801845M are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2) are active . Output Enable(OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipelined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst, LBO=High) Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 BQ TABLE LBO PIN Case 4 A0 0 1 0 1 A1 1 1 0 0 A0 1 0 1 0 (Linear Burst, LBO=Low) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. -6- November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM STATE DIAGRAM FOR NtRAMTM WRITE READ READ BEGIN READ BEGIN WRITE DS RE AD I WR ST BUR TE BURST R W D R EA IT E DS BURST READ BURST WRITE COMMAND DS W RI DESELECT ST RE A DS DS BURST TE BU R D DS WRITE BURST ACTION DESELECT READ BEGIN READ WRITE BEGIN WRITE BURST BEGIN READ BEGIN WRITE CONTINUE DESELECT Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) -7- November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS 1 CS2 CS2 ADV WE BWx OE CKE CLK ADDRESS ACCESSED OPERATION H X X L X X X L ↑ N/A Not Selected X L X L X X X L ↑ N/A Not Selected X X H L X X X L ↑ N/A Not Selected X X X H X X X L ↑ N/A Not Selected Continue L H L L H X L L ↑ External Address Begin Burst Read Cycle X X X H X X L L ↑ Next Address Continue Burst Read Cycle L H L L H X H L ↑ External Address NOP/Dummy Read X X X H X X H L ↑ Next Address Dummy Read L H L L L L X L ↑ External Address Begin Burst Write Cycle X X X H X L X L ↑ Next Address Continue Burst Write Cycle L H L L L H X L ↑ N/A NOP/Write Abort X X X H X H X L ↑ Next Address Write Abort X X X X X X X H ↑ Current Address Ignore Clock Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by (↑). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE (x36) WE BWa BWb BWc BWd OPERATION H X X X X READ L L H H H WRITE BYTE a L H L H H WRITE BYTE b L H H L H WRITE BYTE c L H H H L WRITE BYTE d L L L L L WRITE ALL BYTEs L H H H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). WRITE TRUTH TABLE(x18) WE BWa BWb OPERATION H X X READ L L H WRITE BYTE a L H L WRITE BYTE b L L L WRITE ALL BYTEs L H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). -8- November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM ASYNCHRONOUS TRUTH TABLE Operation ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Read Notes 1. X means "Don ′t Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on V DD Supply Relative to VSS VDD -0.3 to 3.6 V Voltage on Any Other Pin Relative to VSS VIN -0.3 to 3.6 V Power Dissipation Storage Temperature PD 1.4 W TSTG -65 to 150 °C Operating Temperature TOPR 0 to 70 °C Storage Temperature Range Under Bias TBIAS -10 to 85 °C *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS(0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT VDD 2.375 2.5 2.625 V VDDQ 2.375 2.5 2.625 V VSS 0 0 0 V TEST CONDI- MIN MAX UNIT *Note : VDD and V DDQ must be supplied with identical vlotage levels. CAPACITANCE*(TA=25°C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN VIN=0V - 6 pF COUT VOUT=0V - 8 pF *Note : Sampled not 100% tested. -9- November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM DC ELECTRICAL CHARACTERISTICS(VDD=2.5V ±5%, TA=0°C to +70°C) PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD -2 +2 µA Output Leakage Current IOL Output Disabled, -2 +2 µA Operating Current ICC -16 - 350 VDD=Max IOUT=0mA -15 - 320 Cycle Time ≥ tCYC Min -13 - 300 -10 - 250 -16 - 70 -15 - 60 -13 - 50 -10 - 40 - 20 mA f=Max, All Inputs≤VIL or ≥VIH - 20 mA - 0.4 V Device deselected, IOUT=0mA, ISB ZZ≤VIL, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V Standby Current ISB1 ISB2 Device deselected, I OUT=0mA, ZZ ≤0.2V, f=0, All Inputs=fixed (V DD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZ≥VDD-0.2V, mA NOTES 1,2 mA Output Low Voltage VOL IOL=1.0mA Output High Voltage VOH IOH=-1.0mA 2.0 - V Input Low Voltage VIL -0.3* 0.7 V Input High Voltage VIH 1.7 VDD+0.3** V 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V VIH VSS VSS-0.8V 20% tCYC(MIN) TEST CONDITIONS (TA=0 to 70°C, VDD=2.5V ±5%, unless otherwise specified) PARAMETER VALUE Input Pulse Level 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80%) 1.0V/ns Input and Output Timing Reference Levels 1.25V Output Load See Fig. 1 - 10 - November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) Output Load(A) Dout RL=50Ω +2.5V VL=1.25V 30pF* Zo=50Ω 1667Ω Dout 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS (VDD=2.5V ±5%, TA=0 to 70°C) PARAMETER SYMBOL -16 -15 -13 -10 MIN MAX MIN MAX MIN MAX MIN MAX UNIT Cycle Time tCYC 6.0 - 6.7 - 7.5 - 10.0 - ns Clock Access Time tCD - 3.5 - 3.8 - 4.2 - 5.0 ns Output Enable to Data Valid tOE - 3.5 - 3.8 - 4.2 - 5.0 ns Clock High to Output Low-Z tLZC 1.5 - 1.5 - 1.5 - 1.5 - ns Output Hold from Clock High tOH 1.5 - 1.5 - 1.5 - 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 2.7 - 3.0 - 3.5 - 3.5 ns Clock High to Output High-Z tHZC - 2.7 - 3.0 - 3.5 - 3.5 ns Clock High Pulse Width tCH 2.2 - 2.5 - 3.0 - 3.0 - ns Clock Low Pulse Width tCL 2.2 - 2.5 - 3.0 - 3.0 - ns Address Setup to Clock High tAS 1.5 - 1.5 - 1.5 - 1.5 - ns CKE Setup to Clock High tCES 1.5 - 1.5 - 1.5 - 1.5 - ns Data Setup to Clock High tDS 1.5 - 1.5 - 1.5 - 1.5 - ns Write Setup to Clock High (WE, BWX) tWS 1.5 - 1.5 - 1.5 - 1.5 - ns Address Advance Setup to Clock High tADVS 1.5 - 1.5 - 1.5 - 1.5 - ns Chip Select Setup to Clock High tCSS 1.5 - 1.5 - 1.5 - 1.5 - ns Address Hold from Clock High tAH 0.5 - 0.5 - 0.5 - 0.5 - ns CKE Hold from Clock High tCEH 0.5 - 0.5 - 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.5 - 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High (WE, BWEX) tWH 0.5 - 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - 0.5 - 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given voltage and temperature tLZC is more than t HZC. The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions (0°C,2.625V) than tHZC, which is a Max. parameter(worst case at 70°C,2.375V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. - 11 - November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS (VDD,VDDQ=2.5V ±5%) DESCRIPTION CONDITIONS SYMBOL ZZ ≥ VIH Current during SLEEP MODE MIN ISB2 MAX UNITS 10 mA ZZ active to input ignored tPDS 2 cycle ZZ inactive to input sampled tPUS 2 cycle ZZ active to SLEEP current tZZI ZZ inactive to exit SLEEP current tRZZI 2 cycle 0 SLEEP MODE WAVEFORM K tPDS ZZ setup cycle t PUS ZZ recovery cycle ZZ tZZI Isupply ISB2 t RZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z DON′T CARE - 12 - November 1999 Rev 3.0 - 13 - Data Out OE ADV CS WRITE Address CKE Clock A1 tADVH tCSH tWH tAH tLZOE tOE Q1-1 A2 tHZOE tCEH Q2-1 tCD tOH tCYC Q2-2 tCL NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tADVS tCSS tWS tAS tCES tCH Q2-3 A3 TIMING WAVEFORM OF READ CYCLE Q2-4 Q3-1 Q3-2 Q3-3 Undefined Don′t Care Q3-4 tHZC K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM November 1999 Rev 3.0 - 14 - Data Out Data In OE ADV CS WRITE Address CKE Clock Q0-4 tHZOE D1-1 A2 tCYC tCL D2-1 D2-2 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Q0-3 A1 tCES tCEH tCH D2-3 A3 TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 tDS D3-2 tDH D3-3 Undefined Don′t Care D3-4 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM November 1999 Rev 3.0 - 15 - Data In Data Out OE ADV CS WRITE Address CKE Clock tOE tLZOE A2 Q1 A3 tDS D2 tDH Q3 A4 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L A1 tCES tCEH A5 Q4 A6 D5 A7 TIMING WAVEFORM OF SINGLE READ/WRITE tCH Q6 tCYC tCL A8 Q7 A9 Undefined Don′t Care K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM November 1999 Rev 3.0 - 16 - Data In A1 tCES tCEH tCD tLZC A2 Q1 tHZC A3 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Data Out OE ADV CS WRITE Address CKE Clock tDS A4 D2 TIMING WAVEFORM OF CKE OPERATION tDH tCH Q3 tCYC tCL A5 Q4 A6 Undefined Don′t Care K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM November 1999 Rev 3.0 - 17 - Data In Data Out OE ADV CS WRITE Address CKE Clock A1 tCEH tOE tLZOE A2 Q1 Q2 tHZC A3 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tCES D3 tDS tDH A4 tCD tLZC TIMING WAVEFORM OF CS OPERATION Q4 A5 tCH tCYC tCL D5 Undefined Don′t Care K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM November 1999 Rev 3.0 K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 0~8° 22.00 ±0.30 0.127 +- 0.10 0.05 20.00 ±0.20 16.00 ±0.30 14.00 ±0.20 0.10 MAX (0.83) 0.50 #1 0.65 ±0.10 (0.58) 0.30 ±0.10 0.10 MAX 1.40 ±0.10 1.60 MAX 0.50 ±0.10 - 18 - 0.05 MIN November 1999 Rev 3.0