INTERSIL KAD5514P

KAD5514P
®
Data Sheet
September 10, 2009
FN6804.2
14-Bit, 250/210/170/125MSPS ADC
Features
The KAD5514P is a family of low-power, high-performance
14-bit, analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard
CMOS process, the family supports sampling rates of up to
250MSPS. The KAD5514P is part of a pin-compatible
portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging
from 125MSPS to 500MSPS.
• Programmable Gain, Offset and Skew Control
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
• Nap and Sleep Modes
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5514P is available in 72- and 48-contact
QFN packages with an exposed paddle. Operating from a
1.8V supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
• Programmable Built-in Test Patterns
Pin-Compatible Family
• 950MHz Analog Input Bandwidth
• 60fs Clock Jitter
• Over-Range Indicator
• Selectable Clock Divider: ÷1, ÷2 or ÷4
• Clock Phase Selection
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
• Single-Supply 1.8V Operation
• Pb-Free (RoHS Compliant)
Applications
• Power Amplifier Linearization
RESOLUTION
SPEED
(MSPS)
KAD5514P-25
14
250
KAD5514P-21
14
210
KAD5514P-17
14
170
KAD5514P-12
14
125
KAD5512P-50
12
500
Key Specifications
KAD5512P-25,
KAD5514P-25
12
250
• SNR = 69.4dBFS for fIN = 105MHz (-1dBFS)
KAD5512P-21,
KAD5514P-21
12
210
KAD5512P-17,
KAD5514P-17
12
170
KAD5512P-12,
KAD5514P-12
12
125
KAD5510P-50
10
500
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
• WiMAX and Microwave Receivers
• SFDR = 82.2dBc for fIN = 105MHz (-1dBFS)
CLKP
OVDD
AVDD
CLKDIV
• Total Power Consumption
- 429/345mW @ 250/125MSPS (SDR Mode)
- 390/309mW @ 250/125MSPS (DDR Mode)
CLKOUTP
CLOCK
GENERATION
CLKN
CLKOUTN
D[13:0]P
14-BIT
250 MSPS
ADC
VINN
VCM
+
–
1
AVSS
1.25V
SPI
CONTROL
CSB
SCLK
SDIO
SDO
SHA
D[13:0]N
DIGITAL
ERROR
CORRECTION
ORP
ORN
LVDS/CMOS
DRIVERS
OUTFMT
OUTMODE
OVSS
VINP
NAPSLP
MODEL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
KAD5514P
Ordering Information
PART NUMBER
PART MARKING
SPEED
(MSPS)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
KAD5514P-25Q72 (Note 1)
KAD5514P-25 Q72EP-I
250
-40 to +85
72 Ld QFN
L72.10X10D
KAD5514P-21Q72 (Note 1)
KAD5514P-21 Q72EP-I
210
-40 to +85
72 Ld QFN
L72.10X10D
KAD5514P-17Q72 (Note 1)
KAD5514P-17 Q72EP-I
170
-40 to +85
72 Ld QFN
L72.10X10D
KAD5514P-12Q72 (Note 1)
KAD5512P-17 Q72EP-I
125
-40 to +85
72 Ld QFN
L72.10X10D
KAD5514P-25Q48 (Note 2)
KAD5512P-25 Q48EP-I
250
-40 to +85
48 Ld QFN
L48.7X7E
KAD5514P-21Q48 (Note 2)
KAD5514P-21 Q48EP-I
210
-40 to +85
48 Ld QFN
L48.7X7E
KAD5514P-17Q48 (Note 2)
KAD5514P-17 Q48EP-I
170
-40 to +85
48 Ld QFN
L48.7X7E
KAD5514P-12Q48 (Note 2)
KAD5514P-12 Q48EP-I
125
-40 to +85
48 Ld QFN
L48.7X7E
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
2
FN6804.2
September 10, 2009
KAD5514P
Table of Contents
Pin-Compatible Family...................................................... 1
Serial Peripheral Interface ............................................. 22
Key Specifications ............................................................ 1
Switching Specifications .................................................. 8
SPI Physical Interface ................................................... 23
SPI Configuration .......................................................... 24
Device Information ........................................................ 24
Indexed Device Configuration/Control .......................... 24
Global Device Configuration/Control............................. 25
Device Test ................................................................... 26
SPI Memory Map .......................................................... 27
Pinout/Package Information............................................. 9
Equivalent Circuits ......................................................... 29
Pin Descriptions - 72QFN ................................................ 9
Pin Descriptions - 48QFN .............................................. 12
72 Pin/48 Pin Package Options ..................................... 30
Electrical Specifications ....................................................4
Digital Specifications ........................................................ 6
Timing Diagrams ............................................................... 7
Typical Performance Curves ...........................................14
Theory of Operation ........................................................ 17
Functional Description ...................................................
Power-On Calibration ....................................................
User-Initiated Reset .......................................................
Analog Input ..................................................................
Clock Input.....................................................................
Jitter ...............................................................................
Voltage Reference .........................................................
Digital Outputs ...............................................................
Over-Range Indicator ....................................................
Power Dissipation ..........................................................
Nap/Sleep ......................................................................
Data Format...................................................................
3
17
17
18
19
19
20
20
20
20
20
21
21
ADC Evaluation Platform ............................................... 30
Layout Considerations................................................... 30
Split Ground and Power Planes ....................................
Clock Input Considerations ...........................................
Exposed Paddle ............................................................
Bypass and Filtering......................................................
LVDS Outputs ...............................................................
LVCMOS Outputs .........................................................
Unused Inputs ...............................................................
30
30
30
30
30
30
30
Definitions.................................................................... 31
Revision History ............................................................. 32
Package Outline Drawing ................................................. 34
FN6804.2
September 10, 2009
KAD5514P
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS. . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
48 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate
(per speed grade).
KAD5514P-25
(Note 7)
PARAMETER
SYMBOL
CONDITIONS
KAD5514P-21
(Note 7)
KAD5514P-17
(Note 7)
KAD5514P-12
(Note 7)
MIN
TYP
MAX MIN
TYP
MAX MIN
TYP
MAX MIN
TYP
MAX UNITS
1.4
1.47
1.54
1.47
1.54
1.47
1.54
1.47
1.54
DC SPECIFICATIONS
Analog Input
Full-Scale Analog
Input Range
VFS
Differential
1.4
1.4
1.4
VP-P
Input Resistance
RIN
Differential
500
500
500
500
Ω
Input Capacitance
CIN
Differential
2.6
2.6
2.6
2.6
pF
Full Scale Range
Temp. Drift
AVTC
Full Temp
90
90
90
90
ppm/°C
Input Offset Voltage
VOS
Gain Error
EG
Common-Mode Output
Voltage
-10
±2
10
-10
±0.6
VCM
435
535
±2
10
-10
±0.6
635
435
535
±2
10
-10
±0.6
635
435
535
±2
10
±0.6
635
435
535
mV
%
635
mV
Clock Inputs
Inputs Common Mode
Voltage
0.9
0.9
0.9
0.9
V
CLKP,CLKN Input
Swing
1.8
1.8
1.8
1.8
V
Power Requirements
1.8V Analog Supply
Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital Supply
Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog Supply
Current
IAVDD
170
180
157
166
145
153
129
137
mA
1.8V Digital Supply
Current (Note 4) (SDR)
I
OVDD
3mA LVDS
68
76
66
74
64
72
62
70
mA
1.8V Digital Supply
Current (Note 4) (DDR)
I
OVDD
3mA LVDS
46
44
43
42
mA
Power Supply
Rejection Ratio
PSRR
30MHz,
200mVP-P signal
on AVDD
-36
-36
-36
-36
dB
4
FN6804.2
September 10, 2009
KAD5514P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate
(per speed grade). (Continued)
KAD5514P-25
(Note 7)
PARAMETER
SYMBOL
CONDITIONS
MIN
KAD5514P-21
(Note 7)
KAD5514P-17
(Note 7)
KAD5514P-12
(Note 7)
TYP
MAX MIN
TYP
MAX MIN
TYP
MAX MIN
TYP
MAX UNITS
463
402
433
378
406
345
376
Total Power Dissipation
Normal Mode (SDR)
PD
3mA LVDS
429
Normal Mode (DDR)
PD
3mA LVDS
390
Nap Mode
PD
Sleep Mode
PD
363
339
309
mW
mW
148
163
142
157
136
151
129
143
mW
CSB at logic high
2
6
2
6
2
6
2
6
mW
Nap Mode Wakeup
Time (Note 5)
Sample Clock
Running
1
1
1
1
µs
Sleep Mode Wakeup
Time
(Note 5)
Sample Clock
Running
1
1
1
1
ms
AC SPECIFICATIONS
Differential
Nonlinearity
DNL
Integral Nonlinearity
INL
Minimum Conversion
Rate (Note 6)
fS MIN
Maximum Conversion
Rate
fS MAX
Signal-to-Noise Ratio
SNR
-1.0
Effective Number of
Bits
Spurious-Free
Dynamic Range
1.0
-1.0
±3.5
±0.3
250
fIN = 10MHz
SINAD
1.0
±5.0
LSB
40
125
70.6
68.1
70.4
68.4
LSB
MSPS
MSPS
70.9
dBFS
70.7
dBFS
69.4
70.0
70.1
dBFS
fIN = 364MHz
67.6
68.1
68.9
68.7
dBFS
fIN = 695MHz
64.9
65.1
66.3
65.7
dBFS
fIN = 995MHz
62.6
62.9
64.1
63.4
dBFS
69.4
66.4
69.1
70.2
66.9
70.2
70.5
67.6
70.1
67.6
70.7
dBFS
70.3
dBFS
fIN = 190MHz
68.4
69.1
69.4
69.7
dBFS
fIN = 364MHz
66.7
67.0
67.6
67.6
dBFS
fIN = 695MHz
59.0
58.9
60.1
59.9
dBFS
fIN = 995MHz
48.2
48.2
49.1
50.4
dBFS
fIN = 10MHz
11.2
11.4
11.4
11.5
Bits
fIN = 105MHz
11.4
Bits
fIN = 190MHz
11.1
11.2
11.2
11.3
Bits
fIN = 364MHz
10.8
10.8
10.9
10.9
Bits
fIN = 695MHz
9.5
9.5
9.7
9.7
Bits
fIN = 995MHz
7.7
7.7
7.9
8.1
Bits
fIN = 10MHz
89.9
86.7
87.2
84.9
dBc
fIN = 105MHz
5
±0.3
40
170
70.2
-1.0
±3.5
70.2
67.4
1.0
68.9
fIN = 105MHz
SFDR
±0.3
fIN = 190MHz
fIN = 10MHz
ENOB
210
69.4
-1.0
40
69.5
66.9
1.0
±3.5
40
fIN = 105MHz
Signal-to-Noise and
Distortion
±0.3
10.8
70.0
11.2
82.2
10.9
70.0
11.4
85.2
11.0
70.0
11.4
82.0
11.0
81.7
dBc
fIN = 190MHz
80.2
79.6
79.2
70.0
80.2
dBc
fIN = 364MHz
75.5
75.6
75.1
75.5
dBc
fIN = 695MHz
60.4
60.7
61.3
61.4
dBc
fIN = 995MHz
47.9
48.5
48.7
50.1
dBc
FN6804.2
September 10, 2009
KAD5514P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate
(per speed grade). (Continued)
KAD5514P-25
(Note 7)
PARAMETER
SYMBOL
CONDITIONS
fIN = 70MHz
MIN
TYP
KAD5514P-21
(Note 7)
MAX MIN
MAX MIN
TYP
-92.3
KAD5514P-12
(Note 7)
MAX MIN
-94.5
TYP
MAX UNITS
-94.9
dBFS
dBFS
Intermodulation
Distortion
IMD
-91.4
-86.9
-91.7
-85.7
Word Error Rate
WER
10-12
10-12
10-12
10-12
Full Power Bandwidth
FPBW
950
950
950
950
fIN = 170MHz
-89.2
TYP
KAD5514P-17
(Note 7)
MHz
NOTES:
4. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.
5. See Nap /Sleep Mode description on page 21 for more detail.
6. The DLL Range setting must be changed for low speed operation. See the “Serial Peripheral Interface” on page 22 for more detail.
7. Parameters with MIN and/or MAX limits are 100% production tested at their worst case temperature extreme (+85°C).
Digital Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0
1
10
µA
-25
-12
-5
µA
INPUTS
Input Current High
(SDIO, RESETN)
IIH
VIN = 1.8V
Input Current Low
(SDIO, RESETN)
IIL
VIN = 0V
Input Voltage High
(SDIO, RESETN)
VIH
Input Voltage Low
(SDIO, RESETN)
VIL
Input Current High (OUTMODE,
NAPSLP, CLKDIV, OUTFMT)
(Note 8)
IIH
15
Input Current Low (OUTMODE,
NAPSLP, CLKDIV, OUTFMT)
IIL
-40
Input Capacitance
1.17
CDI
V
.63
V
25
40
µA
25
-15
µA
3
pF
LVDS OUTPUTS
Differential Output Voltage
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
620
950
965
mVP-P
980
mV
Output Rise Time
tR
500
ps
Output Fall Time
tF
500
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
6
FN6804.2
September 10, 2009
KAD5514P
Timing Diagrams
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
tCPD
LATENCY = L CYCLES
CLKOUTN
CLKOUTP
LATENCY = L CYCLES
CLKOUTN
CLKOUTP
tDC
D[12/10/8/6/4/2/0]N
tDC
tPD
D[12/10/8/6/4/2/0]P
ODD BITS EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS
N-L
N-L
N-L + 1
N-L + 1
N-L + 2
N-L + 2
EVEN BITS
N
tPD
D[13/0]P
D[13/0]N
DATA
N-L
FIGURE 1A. DDR
DATA
N-L + 1
DATA
N
FIGURE 1B. SDR
FIGURE 1. LVDS TIMING DIAGRAMS (See “Digital Outputs” on page 20)
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
tCPD
LATENCY = L CYCLES
CLKOUT
CLKOUT
tDC
tDC
tPD
D[12/10/8/6/4/2/0]
LATENCY = L CYCLES
ODD BITS
N-L
tPD
EVEN BITS ODD BITS
N-L
N-L + 1
EVEN BITS ODD BITS EVEN BITS
N-L + 1
N-L + 2
N-L + 2
FIGURE 2A. DDR
EVEN BITS
N
D[13/0]
DATA
N-L
DATA
N-L + 1
DATA
N
FIGURE 2B. SDR
FIGURE 2. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 20)
7
FN6804.2
September 10, 2009
KAD5514P
Switching Specifications
PARAMETER
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
ADC OUTPUT
Aperture Delay
tA
375
ps
RMS Aperture Jitter
jA
60
fs
DDR, Rising Edge
tDC
-260
-50
120
ps
DDR, Falling Edge
tDC
-160
10
230
ps
SDR, Falling Edge
tDC
-260
-40
230
ps
DDR, Rising Edge
Output Clock to Data
Propagation Delay, CMOS Mode
DDR, Falling Edge
(Note 9)
tDC
-220
-10
200
ps
tDC
-310
-90
110
ps
SDR, Falling Edge
tDC
-310
-50
200
ps
Output Clock to Data
Propagation Delay, LVDS Mode
(Note 9)
Latency (Pipeline Delay)
Overvoltage Recovery
L
8.5
cycles
tOVR
1
cycles
SPI INTERFACE (Notes 10, 11)
SCLK Period
Write Operation
tCLK
16
cycles
(Note 10)
Read Operation
tCLK
66
cycles
SCLK Duty Cycle (tHI/tCLK or
tLO/tCLK)
Read or Write
CSB↓ to SCLK↑ Setup Time
Read or Write
tS
1
cycles
CSB↑ after SCLK↑ Hold Time
Read or Write
tH
3
cycles
Data Valid to SCLK↑ Setup Time Write
tDSW
1
cycles
Data Valid after SCLK↑ Hold
Time
Write
tDHW
3
cycles
Data Valid after SCLK↓ Time
Read
tDVR
Data Invalid after SCLK↑ Time
Read
tDHR
3
cycles
Sleep Mode CSB↓ to SCLK↑
Setup Time (Note 12)
Read or Write in Sleep Mode
tS
150
µs
25
50
75
16.5
%
cycles
NOTES:
8. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
depending on desired function.
9. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
applications. Contact factory for more info if needed.
10. SPI Interface timing is directly proportional to the ADC sample period (4ns at 250Msps).
11. The SPI may operate asynchronously with respect to the ADC sample clock.
12. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup
time (4ns min).
8
FN6804.2
September 10, 2009
KAD5514P
Pinout/Package Information
Pin Descriptions - 72QFN
LVDS [LVCMOS] FUNCTION
SDR MODE
DDR MODE COMMENTS
PIN NUMBER
LVDS [LVCMOS] NAME
1, 6, 12, 19, 24, 71
AVDD
1.8V Analog Supply
2-5, 13, 14, 17, 18
DNC
Do Not Connect
7, 8, 11, 72
AVSS
Analog Ground
9, 10
VINN, VINP
15
VCM
16
CLKDIV
Tri-Level Clock Divider Control
20, 21
CLKP, CLKN
Clock Input True, Complement
22
OUTMODE
Tri-Level Output Mode (LVDS, LVCMOS)
23
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
25
RESETN
Power On Reset (Active Low, see page 18)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
28
D0N
[NC]
LVDS Bit 0 (LSB) Output Complement
[NC in LVCMOS]
DDR Logical Bits 1, 0 (LVDS)
29
D0P
[D0]
LVDS Bit 0 (LSB) Output True
[ LVCMOS Bit 0]
DDR Logical Bits 1, 0 (LVDS or
CMOS)
30
D1N
[NC]
LVDS Bit 1 Output Complement
[NC in LVCMOS]
NC in DDR
31
D1P
[D1]
LVDS Bit 1 Output True
[ LVCMOS Bit 1]
NC in DDR
32
D2N
[NC]
LVDS Bit 2 Output Complement
[NC in LVCMOS]
DDR Logical Bits 3,2 (LVDS)
33
D2P
[D2]
LVDS Bit 2 Output True
[ LVCMOS Bit 2]
DDR Logical Bits 3,2 (LVDS or CMOS)
34
D3N
[NC]
LVDS Bit 3 Output Complement
[NC in LVCMOS]
NC in DDR
35
D3P
[D3]
LVDS Bit 3 Output True
[ LVCMOS Bit 3]
NC in DDR
37
D4N
[NC]
LVDS Bit 4 Output Complement
[NC in LVCMOS]
DDR Logical Bits 5,4 (LVDS)
38
D4P
[D4]
LVDS Bit 4 Output True
[ LVCMOS Bit 4]
DDR Logical Bits 5,4 (LVDS or CMOS)
39
D5N
[NC]
LVDS Bit 5 Output Complement
[NC in LVCMOS]
NC in DDR
40
D5P
[D5]
LVDS Bit 5 Output True
[ LVCMOS Bit 5]
NC in DDR
41
D6N
[NC]
LVDS Bit 6 Output Complement
[NC in LVCMOS]
DDR Logical Bits 7,6 (LVDS)
42
D6P
[D6]
LVDS Bit 6 Output True
[ LVCMOS Bit 6]
DDR Logical Bits 7,6 (LVDS or CMOS)
43
D7N
[NC]
LVDS Bit 7 Output Complement
[NC in LVCMOS]
NC in DDR
44
D7P
[D7]
LVDS Bit 7 Output True
[ LVCMOS Bit 7]
NC in DDR
9
Analog Input Negative, Positive
Common Mode Output
FN6804.2
September 10, 2009
KAD5514P
Pin Descriptions - 72QFN
LVDS [LVCMOS] FUNCTION
SDR MODE
DDR MODE COMMENTS
PIN NUMBER
LVDS [LVCMOS] NAME
46
RLVDS
47
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
48
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[ LVCMOS CLKOUT]
49
D8N
[NC]
LVDS Bit 8 Output Complement
[NC in LVCMOS]
DDR Logical Bits 9,8 (LVDS)
50
D8P
[D8]
LVDS Bit 8 Output True
[ LVCMOS Bit 8]
DDR Logical Bits 9,8 (LVDS or CMOS)
51
D9N
[NC]
LVDS Bit 9 Output Complement
[NC in LVCMOS]
NC in DDR
52
D9P
[D9]
LVDS Bit 9 Output True
[ LVCMOS Bit 9]
NC in DDR
53
D10N
[NC]
LVDS Bit 10 Output Complement
[NC in LVCMOS]
DDR Logical Bits 11,10 (LVDS)
54
D10P
[D10]
LVDS Bit 10 Output True
[ LVCMOS Bit 10]
DDR Logical Bits 11,10 (LVDS or
CMOS)
57
D11N
[NC]
LVDS Bit 11 Output Complement
[NC in LVCMOS]
NC in DDR
58
D11P
[D11]
LVDS Bit 11 Output True
[ LVCMOS Bit 11]
NC in DDR
59
D12N
[NC]
LVDS Bit 12 Output Complement
[NC in LVCMOS]
DDR Logical Bits 13,12 (LVDS)
60
D12P
[D10]
LVDS Bit 12 Output True
[ LVCMOS Bit 10]
DDR Logical Bits 13,12 (LVDS or
CMOS)
61
D13N
[NC]
LVDS Bit 13 (MSB) Output Complement
[NC in LVCMOS]
NC in DDR
62
D13P
[D13]
LVDS Bit 13 (MSB) Output True
[ LVCMOS Bit 11]
NC in DDR
63
ORN
[NC]
LVDS Over Range Complement
[NC in LVCMOS]
64
ORP
[OR]
LVDS Over Range True
[ LVCMOS Over Range]
66
SDO
SPI Serial Data Output (4.7kΩ pull-up to
OVDD is required)
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
70
OUTFMT
Exposed Paddle
AVSS
LVDS Bias Resistor
Tri-Level Output Data Format (Two’s Comp.,
Gray Code, Offset Binary)
Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
10
FN6804.2
September 10, 2009
KAD5514P
Pinout
AVSS
AVDD
OUTFMT
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D13P
D13N
D12P
D12N
D11P
D11N
OVDD
OVSS
KAD5514
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD
1
54 D10P
DNC
2
53 D10N
DNC
3
52 D9P
DNC
4
51 D9N
DNC
5
50 D8P
AVDD
6
49 D8N
AVSS
7
48 CLKOUTP
AVSS
8
47 CLKOUTN
VINN
9
46 RLVDS
VINP
10
45 OVSS
AVSS
11
44 D7P
AVDD
12
43 D7N
DNC
13
42 D6P
DNC
14
41 D6N
VCM
15
40 D5P
CLKDIV
16
39 D5N
DNC
17
DNC
18
Connect Thermal Pad to AVSS
38 D4P
28
29
30
31
32
33
34
35
36
D2N
D2P
D3N
D3P
OVDD
NAPSLP
27
D1P
OUTMODE
26
D1N
CLKN
25
D0P
CLKP
24
D0N
23
OVDD
22
OVSS
21
RESETN
20
AVDD
19
AVDD
37 D4N
FIGURE 3. PIN CONFIGURATION
11
FN6804.2
September 10, 2009
KAD5514P
?
Pin Descriptions—48QFN
PIN NUMBER
LVDS [LVCMOS] NAME
1, 9, 13, 17, 47
AVDD
1.8V Analog Supply
2-4, 11
DNC
Do Not Connect
5, 8, 12, 48
AVSS
Analog Ground
6, 7
VINN, VINP
10
VCM
14, 15
CLKP, CLKN
16
NAPSLP
Tri-Level Power Control (Nap, Sleep Modes)
18
RESETN
Power-on Reset (Active Low, see “User-Initiated Reset” on page 18)
19, 29, 42
OVSS
Output Ground
20, 37
OVDD
1.8V Output Supply
21
D0N
[NC]
LVDS DDR Logical Bits 1,0 Output Complement
[NC in LVCMOS]
22
D0P
[D0]
LVDS DDR Logical Bits 1,0 Output True
[CMOS DDR Logical Bits 1,0 in LVCMOS]
23
D1N
[NC]
LVDS DDR Logical Bits 3,2 Output Complement
[NC in LVCMOS]
24
D1P
[D1]
LVDS DDR Logical Bits 3,2 Output True
[CMOS DDR Logical Bits 3,2 in LVCMOS]
25
D2N
[NC]
LVDS DDR Logical Bits 5,4 Output Complement
[NC in LVCMOS]
26
D2P
[D2]
LVDS DDR Logical Bits 5,4 Output True
[CMOS DDR Logical Bits 5,4 in LVCMOS]
27
D3N
[NC]
LVDS DDR Logical Bits 7,6 Output Complement
[NC in LVCMOS]
28
D3P
[D3]
LVDS DDR Logical Bits 7,6 Output True
[CMOS DDR Logical Bits 7,6 in LVCMOS]
30
RLVDS
31
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
32
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[ LVCMOS CLKOUT]
33
D4N
[NC]
LVDS DDR Logical Bits 9,8 Output Complement
[NC in LVCMOS]
34
D4P
[D4]
LVDS DDR Logical Bits 9,8 Output True
[CMOS DDR Logical Bits 9,8 in LVCMOS]
35
D5N
[NC]
LVDS DDR Logical Bits 11,10 Output Complement
[NC in LVCMOS]
36
D5P
[D5]
LVDS DDR Logical Bits 11,10 Output True
[CMOS DDR Logical Bits 11,10 in LVCMOS]
38
D6N
[NC]
LVDS DDR Logical Bits 13,12 Output Complement
[NC in LVCMOS]
39
D6P
[D6]
LVDS DDR Logical Bits 13,12 Output True
[CMOS DDR Logical Bits 13,12 in LVCMOS]
40
ORN
[NC]
LVDS Over Range Complement
[NC in LVCMOS]
12
LVDS [LVCMOS] FUNCTION
Analog Input Negative, Positive
Common Mode Output
Clock Input True, Complement
LVDS Bias Resistor
FN6804.2
September 10, 2009
KAD5514P
Pin Descriptions—48QFN
PIN NUMBER
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
41
ORP
[OR]
LVDS Over Range True
[LVCMOS Over Range]
43
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
44
CSB
SPI Chip Select (active low)
45
SCLK
SPI Clock
46
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
Pinout
AVSS
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D6P
D6N
OVDD
KAD5514P
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
AVDD
1
36 D5P
DNC
2
35 D5N
DNC
3
34 D4P
DNC
4
33 D4N
AVSS
5
32 CLKOUTP
VINN
6
31 CLKOUTN
VINP
7
30 RLVDS
AVSS
8
29 OVSS
AVDD
9
28 D3P
VCM
10
27 D3N
DNC
11
AVSS
12
26 D2P
Connect Thermal Pad to AVSS
13
14
15
16
17
18
19
20
21
22
23
24
AVDD
CLKP
CLKN
NAPSLP
AVDD
RESETN
OVSS
OVDD
D0N
D0P
D1N
D1P
25 D2N
FIGURE 4. 48 QFN PIN CONFIGURATION
13
FN6804.2
September 10, 2009
KAD5514P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise
noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade).
-50
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
SFDR @ 125MSPS
85
80
75
SNR @ 125MSPS
70
65
SNR @ 250MSPS
60
55
50
SFDR @ 250MSPS
0M
200M
400M
600M
800M
-55
HD3 @ 125MSPS
-65
-70
HD2 @ 125MSPS
-75
HD2 @ 250MSPS
-80
-85
-90
-95
-100
0M
1G
HD3 @ 250MSPS
-60
200M
INPUT FREQUENCY (Hz)
FIGURE 5. SNR AND SFDR vs fIN
90
-20
SFDRFS (dBFS)
SNR AND SFDR
80
70
60 SNRFS (dBFS)
50
SFDR (dBc)
40
30
SNR (dBc)
20
10
0
-60
-50
-40
-30
-20
-10
-30
-90
-100
-110
HD3 (dBFS)
-50
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
80
75
SNR
65
160
190
220
SAMPLE RATE (MSPS)
FIGURE 9. SNR AND SFDR vs fSAMPLE
14
-40
-30
-20
FIGURE 8. HD2 AND HD3 vs AIN
85
130
0
-60 HD3 (dBc)
-70
HD2 (dBFS)
-80
INPUT AMPLITUDE (dBFS)
SFDR
100
-10
-50
-120
-60
0
95
60
70
1G
-40
FIGURE 7. SNR AND SFDR vs AIN
70
800M
HD2 (dBc)
INPUT AMPLITUDE (dBFS)
90
600M
FIGURE 6. HD2 AND HD3 vs fIN
HD2 AND HD3 MAGNITUDE
100
400M
INPUT FREQUENCY (Hz)
250
-60
-70
HD3
-80
-90
-100
HD2
-110
-120
70
100
130
160
190
SAMPLE RATE (MSPS)
220
250
FIGURE 10. HD2 AND HD3 vs fSAMPLE
FN6804.2
September 10, 2009
KAD5514P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise
noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade). (Continued)
0.5
500
0.4
400
0.3
SDR
0.2
350
DNL (LSBs)
TOTAL POWER (mW)
450
DDR
300
250
200
0.1
0.0
-0.1
150
-0.2
100
-0.3
50
-0.4
0
40
70
100
130
160
190
220
-0.5
0
250
2048
4096
6144
FIGURE 12. DIFFERENTIAL NONLINEARITY
FIGURE 11. POWER vs fSAMPLE IN 3mA LVDS MODE
90
SNR (dBFS) AND SFDR (dBc)
3
INL (LSBs)
2
1
0
-1
-2
-3
0
2048
4096
6144
85
SFDR
80
75
70
SNR
65
60
55
50
300
8192 10240 12288 14336 16384
CODE
FIGURE 13. INTEGRAL NONLINEARITY
400
500
600
700
INPUT COMMON MODE (mV)
800
FIGURE 14. SNR AND SFDR vs VCM
0
210000
AIN = -1.0dBFS
SNR = 69.4dBFS
SFDR = 91.8dBc
SINAD = 69.4dBFS
-20
AMPLITUDE (dBFS)
180000
NUMBER OF HITS
8192 10240 12288 14336 16384
CODE
SAMPLE RATE (MSPS)
150000
120000
90000
60000
-40
-60
-80
-100
30000
0
8203 8205 8207 8209 8211 8213 8215 8217 8219 8221 8223
CODE
FIGURE 15. NOISE HISTOGRAM
15
-120
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
120M
FIGURE 16. SINGLE-TONE SPECTRUM @ 10MHz
FN6804.2
September 10, 2009
KAD5514P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise
noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade). (Continued)
0
0
AIN = -1.0dBFS
SNR = 69.1dBFS
SFDR = 82.7dBc
SINAD = 68.9dBFS
-40
-60
-80
-60
-80
-120
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
120M
AIN = -1.0dBFS
SNR = 64.8dBFS
SFDR = 69.2dBc
SINAD = 63.6dBFS
-40
-60
-80
100M
120M
AIN = -1.0dBFS
SNR = 60.3dBFS
SFDR = 47.0dBc
SINAD = 47.5dBFS
-40
-60
-80
-100
-100
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
-120
0M
120M
FIGURE 19. SINGLE-TONE SPECTRUM @ 495MHz
20M
40M
60M
80M
FREQUENCY (Hz)
100M
120M
FIGURE 20. SINGLE-TONE SPECTRUM @ 995MHz
0
0
IMD = -91.4dBFS
IMD = -89.2dBFS
-20
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
40M
60M
80M
FREQUENCY (Hz)
-20
AMPLITUDE (dBFS)
-20
-40
-60
-80
-40
-60
-80
-100
-100
-120
20M
0
0
-120
0M
FIGURE 18. SINGLE-TONE SPECTRUM @ 190MHz
FIGURE 17. SINGLE-TONE SPECTRUM @ 105MHz
AMPLITUDE (dBFS)
-40
-100
-100
-120
AIN = -1.0dBFS
SNR = 68.3dBFS
SFDR = 77.2dBc
SINAD = 67.7dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-20
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
FIGURE 21. TWO-TONE SPECTRUM @ 70MHz
16
120M
-120
0M
20M
40M
60M
80M
100M
120M
FREQUENCY (Hz)
FIGURE 22. TWO-TONE SPECTRUM @ 170MHz
FN6804.2
September 10, 2009
KAD5514P
Theory of Operation
Power-On Calibration
Functional Description
The KAD5514P is based upon a 12-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 23). The input voltage is
captured by a Sample-Hold Amplifier (SHA) and converted
to a unit of charge. Proprietary charge-domain techniques
are used to successively compare the input to a series of
reference charges. Decisions made during the successive
approximation operations determine the digital code for each
input value. The converter pipeline requires six samples to
produce a result. Digital error correction is also applied,
resulting in a total latency of seven and one half clock cycles.
This is evident to the user as a time lag between the start of
a conversion and the data being available on the digital
outputs.
The KAD5514P family operates by simultaneously sampling
the input signal with two ADC cores in parallel and summing
the digital result. Since the input signal is correlated between
the two cores and noise is not, an increase in SNR is
achieved. As a result of this architecture, indexed SPI
operations must be executed on each core in series. Refer
to “Indexed Device Configuration/Control” on page 24 for
more details.
The ADC performs a self-calibration at start-up. An internal
power-on-reset (POR) circuit detects the supply voltage
ramps and initiates the calibration when the analog and
digital supply voltages are above a threshold. The following
conditions must be adhered to for the power-on calibration to
execute successfully:
• A frequency-stable conversion clock must be applied to
the CLKP/CLKN pins
• DNC pins (especially 3, 4 and 18) must not be pulled up or
down
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the
event that the above conditions cannot be met at power-up.
The SDO pin requires an external 4.7kΩ pull-up to OVDD. If
the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high, which
starts the calibration sequence. If a subsequent
user-initiated reset is required, the RESETN pin should be
connected to an open-drain driver with a drive strength of
less than 0.5mA.
CLOCK
GENERATION
INP
SHA
INN
1.25V
+
–
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 23. ADC CORE BLOCK DIAGRAM
17
FN6804.2
September 10, 2009
KAD5514P
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 24. The over-range output
(OR) is set high once RESETN is pulled low, and remains in
that state until calibration is complete. The OR output returns
to normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range to
observe the transition. If the input is in an over-range
condition the OR pin will stay high, and it will not be possible
to detect the end of the calibration cycle.
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 250MSPS
the nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
CLKN
CLKP
CALIBRATION
TIME
A supply voltage variation of less than 100mV will generally
result in an SNR change of less than 0.5dBFS and SFDR
change of less than 3dBc. In situations where the sample
rate is not constant, best results will be obtained if the device
is calibrated at the highest sample rate. Reducing the
sample rate by less than 80MSPS will typically result in an
SNR change of less than 0.5dBFS and an SFDR change of
less than 3dBc.
Figures 25 and 26 show the effect of temperature on SNR
and SFDR performance with calibration performed at 40°C,+25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single calibration at
-40°C, +25°C and +85°C. Best performance is typically
achieved by a user-initiated calibration at the operating
conditions, as stated earlier. However, it can be seen that
performance drift with temperature is not a very strong
function of the temperature at which the calibration is
performed. Full-rated performance will be achieved after
power-up calibration regardless of the operating conditions.
RESETN
ORP
CALIBRATION
COMPLETE
CLKOUTP
SNR CHANGE (dBfs)
3
CALIBRATION
BEGINS
CAL DONE AT
+85°C
2
1
0
-1
-2
-3
FIGURE 24. CALIBRATION TIMING
-4
-40
CAL DONE AT
+25°C
CAL DONE AT
-40°C
-15
10
User-Initiated Reset
35
60
85
TEMPERATURE (°C)
The performance of the KAD5514P changes with variations
in temperature, supply voltage or sample rate. The extent of
these changes may necessitate recalibration, depending on
system performance requirements. Best performance will be
achieved by recalibrating the ADC under the environmental
conditions at which it will operate.
FIGURE 25. SNR PERFORMANCE vs TEMPERATURE
15
SFDR CHANGE (dBc)
Recalibration of the ADC can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with a drive strength of less than
0.5mA is recommended, RESETN has an internal high
impedance pull-up to OVDD. As is the case during power-on
reset, the SDO, RESETN and DNC pins must be in the
proper state for the calibration to successfully execute.
10
CAL DONE AT
-40°C
5
0
-5
CAL DONE AT
+85°C
-10
-15
-40
-15
10
35
TEMPERATURE (°C)
CAL DONE AT
+25°C
60
85
FIGURE 26. SFDR PERFORMANCE vs TEMPERATURE
18
FN6804.2
September 10, 2009
KAD5514P
Analog Input
Ω
348O
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit ADC. The ideal
full-scale input voltage is 1.45V, centered at the VCM voltage
of 0.535V as shown in Figure 27.
Ω
69.8O
CM
KAD5514P
VCM
25O
Ω
Ω
69.8O
Ω
49.9O
Ω
348O
1.4
217O
Ω
Ω
100O
0.22µF
1.8
Ω
25O
Ω
100O
0.1µF
INN
1.0
INP
0.725V
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
VCM
0.6
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance will
result in faster settling and improved performance. Therefore
a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
0.535V
0.2
FIGURE 27. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as shown in
Figures 28 through 30. An RF transformer will give the best
noise and distortion performance for wideband and/or high
intermediate frequency (IF) inputs. Two different transformer
input schemes are shown in Figures 28 and 29.
ADT1-1WT
ADT1-1WT
1000pF
A differential amplifier, as shown in Figure 30, can be used in
applications that require dc-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 44 on
page 29). Driving these inputs with a high level (up to
1.8VP-P on each input) sine or square wave will provide the
lowest jitter performance. A transformer with 4:1 impedance
ratio will provide increased drive levels.
KAD5514P
VCM
0.1µF
The recommended drive circuit is shown in Figure 31. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may
impact SNR performance. The clock inputs are internally
self-biased to AVDD/2 to facilitate AC coupling.
FIGURE 28. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
200pF
TC4-1W
200pF
ADTL1-12
CLKP
1000pF
Ω
200O
ADTL1-12
0.1µF
1000pF
CLKN
KAD5514P
1000pF
VCM
200pF
FIGURE 31. RECOMMENDED CLOCK DRIVE
FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT
FOR HIGH IF APPLICATIONS
This dual transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance. The differential input resistance of the
KAD5514P is 500Ω.
A selectable 2x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
The SHA design uses a switched capacitor input stage
(see Figure 43), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
19
FN6804.2
September 10, 2009
KAD5514P
operations. The full-scale range of each A/D is proportional
to the reference voltage. The voltage reference is internally
bypassed and is not accessible to the user.
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
Digital Outputs
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 22.
A delay-locked loop (DLL) generates internal clock signals
for various stages within the charge pipeline. If the frequency
of the input clock changes, the DLL may take up to 52µs to
regain lock at 250MSPS. The lock time is inversely
proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The
slow range can be used for sample rates between 40MSPS
and 100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and
is illustrated in Figure 32.
1
SNR = 20 log 10 ⎛ --------------------⎞
⎝ 2πf t ⎠
(EQ. 1)
IN J
95
tj = 0.1ps
90
14 BITS
SNR (dB)
85
80
tj = 1ps
75
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
tj = 10ps
10 BITS
tj = 100ps
10M
100M
INPUT FREQUENCY (Hz)
1G
FIGURE 32. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
20
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in the “Serial Peripheral Interface” on
page 22.
55
50
1M
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
12 BITS
70
60
The 48 Ld QFN package option contains seven LVDS data
output pin pairs, and therefore can only support DDR mode.
TABLE 2. OUTMODE PIN SETTINGS
100
65
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or single
data rate (SDR) formats. The even numbered data output
pins are active in DDR mode in the 72 pin package option.
When CLKOUT is low the MSB and all odd logical bits are
output, while on the high phase the LSB and all even logical
bits are presented (this is true in both the 72 pin and 48 pin
package options). Figures 1 and 2 on page page 7show the
timing relationships for LVDS/CMOS and DDR/SDR modes.
An external resistor creates the bias for the LVDS drivers. A
10kΩ, 1% resistor must be connected from the RLVDS pin to
OVSS.
Over-Range Indicator
The over-range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary mode).
The output code does not wrap around during an over-range
condition. The OR bit is updated at the sample rate.
Power Dissipation
The power dissipated by the KAD5514P is primarily
dependent on the sample rate and the output modes: LVDS
vs CMOS and DDR vs SDR. There is a static bias in the
analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation changes to a lesser degree in LVDS mode, but is
more strongly related to the clock frequency in CMOS mode.
FN6804.2
September 10, 2009
KAD5514P
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power
saving modes are available: Nap, and Sleep. Nap mode
reduces power dissipation to less than 163mW and recovers
to normal operation in approximately 1µs. Sleep mode
reduces power dissipation to less than 6mW but requires
approximately 1ms to recover from a sleep command.
Wake-up time from sleep mode is dependent on the state of
CSB; in a typical application CSB would be held high during
sleep, requiring a user to wait 150µs max after CSB is
asserted (brought low) prior to writing ‘001x’ to SPI
Register 25. The device would be fully powered up, in
normal mode 1ms after this command is written.
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data format is
selected via the OUTFMT pin as shown in Table 4.
TABLE 4. OUTFMT PIN SETTINGS
OUTFMT PIN
MODE
AVSS
Offset Binary
Float
Two’s Complement
AVDD
Gray Code
The data format can also be controlled through the SPI port,
which overrides the OUTFMT pin setting. Details on this are
contained in the “Serial Peripheral Interface” on page 22.
• Wait 150us
• Write ‘001x’ to Register 25
• Wait 1ms until ADC fully powered on
In an application where CSB was kept low in sleep mode, the
150µs CSB setup time is not required as the SPI registers are
powered on when CSB is low, the chip power dissipation
increases by ~ 15mW in this case. The 1ms wake-up time
after the write of a ‘001x’ to register 25 still applies. It is
generally recommended to keep CSB high in sleep mode to
avoid any unintentional SPI activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input clock
should remain running and at a fixed frequency during Nap
or Sleep, and CSB should be high. Recovery time from Nap
mode will increase if the clock is stopped, since the internal
DLL can take up to 52µs to regain lock at 250MSPS.
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
TABLE 3. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
21
The power-down mode can also be controlled through the
SPI port, which overrides the NAPSLP pin setting. Details on
this are contained in the “Serial Peripheral Interface” on
page 22. This is an indexed function when controlled from
the SPI, but a global function when driven from the pin.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF
(all ones). Two’s complement coding simply complements
the MSB of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows
this operation.
BINARY
13
12
11
••••
1
0
••••
GRAY CODE
13
12
11
••••
1
0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 34.
FN6804.2
September 10, 2009
KAD5514P
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
GRAY CODE
13
12
••••
11
1
0
INPUT
TWO’S
VOLTAGE OFFSET BINARY COMPLEMENT
–Full Scale
000 00 000 00 00 00
GRAY CODE
100 00 000 00 00 00 000 00 000 00 00 00
–Full Scale 000 00 000 00 00 01 100 00 000 00 00 01 000 00 000 00 00 01
+ 1LSB
••••
13
12
••••
11
100 00 000 00 00 00
000 00 000 00 00 00
110 00 000 00 00 00
+Full Scale
– 1LSB
111 11 111 11 11 10
011 11 111 11 11 10
100 00 000 00 00 01
+Full Scale
111 11 111 11 11 11
011 11 111 111 11 1
100 00 000 00 00 00
Serial Peripheral Interface
••••
BINARY
Mid–Scale
1
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK)
serial data input (SDI), and serial data input/output (SDIO).
The maximum SCLK rate is equal to the ADC sample rate
(fSAMPLE) divided by 16 for write operations and fSAMPLE
divided by 66 for reads. At fSAMPLE = 250MHz, maximum
SCLK is 15.63MHz for writing and 3.79MHz for read
operations. There is no minimum SCLK rate.
0
FIGURE 34. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is
shown in Table 5.
The following sections describe various registers that are
used to configure the SPI or adjust performance or functional
parameters. Many registers in the available address space
(0x00 to 0xFF) are not defined in this document. Additionally,
within a defined register there may be certain bits or bit
combinations that are reserved. Undefined registers and
undefined values within defined registers are reserved and
should not be selected. Setting any reserved register or value
may produce indeterminate results.
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D2
D3
D3
D2
D1D
0
D5
D6
D7
FIGURE 35. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D4
FIGURE 36. LSB-FIRST ADDRESSING
22
FN6804.2
September 10, 2009
KAD5514P
SPI Physical Interface
In MSB-first mode the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
The serial clock pin (SCLK) provides synchronization for the
data transfer. By default, all data is presented on the serial
data input/output (SDIO) pin in three-wire mode. The state of
the SDIO pin is set automatically in the communication
protocol (described in the following). A dedicated serial data
output pin (SDO) can be activated by setting 0x00[7] high to
allow operation in four-wire mode.
In the default mode the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits,
W1 and W0, determine the number of data bytes to be read
or written (see Table 6). The lower 13 bits contain the first
address for the data transfer. This relationship is illustrated in
Figure 37, and timing values are given in the “Switching
Specifications” on page 8.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5514P functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an
unaddressed device is asserted in four-wire mode.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from
the ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active.
Stalling of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or
more, CSB is allowed stall in the middle of the
instruction/address bytes or before the first data byte. If CSB
transitions to a high state after that point the state machine
will reset and terminate the data transfer.
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in three-wire mode). If
multiple slave devices are selected for reading at the same
time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command,
SCLK must be static low before the CSB transition. Data can
be presented in MSB-first order or LSB-first order. The
default is MSB-first, but this can be changed by setting
0x00[6] high. Figures 35 and 36 show the appropriate bit
ordering for the MSB-first and LSB-first modes, respectively.
tDSW
CSB
tDHW
tS
TABLE 6. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
tCLK
tHI
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 37. WRITE TIMING
CSB
tS
tDSW
t
tDHW HI
tLO
tCLK
tH
tDHR
tDVR
SCLK
WRITING A READ COMMAND
SDIO
R/W W1
W0 A12 A11 A10 A9
A2
A1 A0
READING DATA(3 WIRE MODE)
D7
D6
SDO
D7
D3 D2
D1 D0
(4 WIRE MODE)
D3 D2 D1 D0
SPI READ
FIGURE 38. READ TIMING
23
FN6804.2
September 10, 2009
KAD5514P
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 39. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 40. N-BYTE TRANSFER
Figures 38 and 39 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation for a
3-byte transfer can be inferred from these diagrams.
Bits 7:0 Burst End Address
SPI Configuration
Device Information
ADDRESS 0X00: CHIP_PORT_CONFIG
ADDRESS 0X08: CHIP_ID
Bit ordering and SPI reset are controlled by this register. Bit
order can be selected as MSB to LSB (MSB first) or LSB to
MSB (LSB first) to accommodate various microcontrollers.
Bit 7 SDO Active
This register value determines the ending address of the
burst data.
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number,
respectively, can be read from these two registers.
Indexed Device Configuration/Control
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial
data as arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode
can improve throughput by eliminating redundant
addressing. In three-wire SPI mode the burst is ended by
pulling the CSB pin high. If the device is operated in two-wire
mode the CSB pin is not available. In that case, setting the
burst_end address determines the end of the transfer.
During a write operation, the user must be cautious to
transmit the correct number of bytes based on the starting
and ending addresses.
24
ADDRESS 0X10: DEVICE_INDEX_A
A common SPI map, which can accommodate
single-channel or multi-channel devices, is used for all
Intersil ADC products. Certain configuration commands
(identified as Indexed in the SPI map) can be executed on a
per-converter basis. This register determines which
converter is being addressed for an Indexed command. It is
important to note that only a single converter can be
addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed. Error code ‘AD’ is returned if any indexed
register is read from without properly setting
device_index_A.
ADDRESS 0X20: OFFSET_COARSE
ADDRESS 0X21: OFFSET_FINE
The input offset of each ADC core can be adjusted in fine
and coarse steps. Both adjustments are made via an 8-bit
word as detailed in Table 7.
FN6804.2
September 10, 2009
KAD5514P
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented
value back to the same register.
TABLE 7. OFFSET ADJUSTMENTS
0x20[7:0]
0x21[7:0]
PARAMETER
COARSE OFFSET
FINE OFFSET
Steps
255
255
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
+Full Scale (0xFF)
+133LSB (+47mV)
+5LSB (+1.75mV)
Nominal Step Size
1.04LSB (0.37mV)
0.04LSB (0.014mV)
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to “Nap/Sleep” on
page 21). This functionality can be overridden and controlled
through the SPI. This is an indexed function when controlled
from the SPI, but a global function when driven from the pin.
This register is not changed by a Soft Reset.
TABLE 10. POWER DOWN CONTROL
0x25[2:0]
VALUE
POWER DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
Global Device Configuration/Control
ADDRESS 0X24: GAIN_FINE
ADDRESS 0X71: PHASE_SLIP
Gain of each ADC core can be adjusted in coarse, medium
and fine steps. Coarse gain is a 4-bit adjustment while
medium and fine are 8-bit. Multiple Coarse Gain Bits can be
set for a total adjustment range of ± 4.2%. (‘0011’ =~ -4.2%
and ‘1100’ =~ +4.2%) It is recommended to use one of the
coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%,
4.2%) and fine-tune the gain using the registers at 23h and
24h.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented
value back to the same register.
When using the clock divider, it’s not possible to determine
the synchronization of the incoming and divided clock
phases. This is particularly important when multiple ADCs
are used in a time-interleaved system. The phase slip
feature allows the rising edge of the divided clock to be
advanced by one input clock cycle when in CLK/4 mode, as
shown in Figure 41. Execution of a phase_slip command is
accomplished by first writing a ‘0’ to bit 0 at address 71h
followed by writing a ‘1’ to bit 0 at address 71h (32 sclk
cycles).
CLK = CLKP - CLKN
CLK
1.00ns
TABLE 8. COARSE GAIN ADJUSTMENT
0x22[3:0]
NOMINAL COARSE GAIN ADJUST
(%)
Bit3
+2.8
Bit2
+1.4
Bit1
-2.8
Bit0
-1.4
CLK÷4
4.00ns
CLK÷4
SLIP ONCE
CLK÷4
SLIP TWICE
FIGURE 41. PHASE SLIP: CLK ÷ 4 MODE, fCLOCK = 1000MHz
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
0x23[7:0]
0x24[7:0]
PARAMETER
MEDIUM GAIN
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
25
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5514P has a selectable clock divider that can be
set to divide by four, two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input”
on page 19). This functionality can be overridden and
controlled through the SPI, as shown in Table 11. This
register is not changed by a Soft Reset.
FN6804.2
September 10, 2009
KAD5514P
TABLE 11. CLOCK DIVIDER SELECTION
0x72[2:0]
VALUE
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5514P can present output data in two physical formats:
LVDS or LVCMOS. Additionally, the drive strength in LVDS
mode can be set high (3mA) or low (2mA). By default, the
tri-level OUTMODE pin selects the mode and drive level (refer
to “Digital Outputs” on page 20). This functionality can be
overridden and controlled through the SPI, as shown in
Table 12.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 21). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
This register is not changed by a Soft Reset.
TABLE 12. OUTPUT MODE CONTROL
0x93[7:5]
VALUE
OUTPUT MODE
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
TABLE 13. OUTPUT FORMAT CONTROL
0x93[2:0]
VALUE
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or
slow.
26
Bit 4 DDR Enable
Setting this bit enables Double Data-Rate mode.
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 14 shows
the allowable sample rate ranges for the slow and fast
settings.
TABLE 14. DLL RANGES
DLL RANGE
MIN
MAX
UNIT
Slow
40
100
MSPS
Fast
80
fS MAX
MSPS
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency
range of the DLL clock generator. The method of setting
these options is different from the other registers.
READ
OUTPUT_MODE_B
0x74
READ
CONFIG_STATUS
0x75
WRITE TO
0x74
DESIRED
VALUE
FIGURE 42. SETTING OUTPUT_MODE_B REGISTER
The procedure for setting output_mode_B is shown in
Figure 42. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with the
desired value for output_mode_B and write that XOR result
to the register.
Device Test
The KAD5514P can produce preset or user defined patterns
on the digital outputs to facilitate in-situ testing. A static word
can be placed on the output bus, or two different words can
alternate. In the alternate mode, the values defined as
Word 1 and Word 2 (as shown in Table 15) are set on the
output bus on alternating clock phases. The test mode is
enabled asynchronously to the sample clock, therefore
several sample clock cycles may elapse before the data is
present on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode) determine
the test pattern in combination with registers 0xC2 through
0xC5. Refer to Table 16.
FN6804.2
September 10, 2009
KAD5514P
ADDRESS 0XC2: USER_PATT1_LSB
TABLE 15. OUTPUT TEST MODES
0xC0[3:0]
VALUE
ADDRESS 0XC3: USER_PATT1_MSB
OUTPUT TEST
MODE
WORD 1
WORD 2
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
0000
Off
0001
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
ADDRESS 0XC3: USER_PATT2_MSB
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
0111
One/Zero
0xFFFF
0x0000
1000
User Pattern
user_patt1
user_patt2
ADDRESS 0XC2: USER_PATT2_LSB
SPI Memory Map
Indexed Device Config/Control
Info
SPI Config
TABLE 16. SPI MEMORY MAP
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
00
port_config
SDO
Active
01
reserved
Reserved
02
burst_end
Burst end address [7:0]
03-07
reserved
Reserved
Bit 6
Bit 5
LSB First
Soft
Reset
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Def. Value
(Hex)
Indexed/
Global
Mirror
(bit5)
Mirror
(bit6)
Mirror
(bit7)
00h
G
00h
G
08
chip_id
Chip ID #
Read only
G
09
chip_version
Chip Version #
Read only
G
00h
I
10
device_index_A
11-1F
reserved
Reserved
20
offset_coarse
Coarse Offset
cal. value
I
21
offset_fine
Fine Offset
cal. value
I
cal. value
I
cal. value
I
cal. value
I
00h
NOT
affected by
Soft Reset
I
22
gain_coarse
23
gain_medium
24
gain_fine
25
modes
26-5F
reserved
Reserved
ADC01
Reserved
ADC00
Coarse Gain
Medium Gain
Fine Gain
Reserved
Power-Down Mode [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
other codes = reserved
Reserved
27
FN6804.2
September 10, 2009
KAD5514P
TABLE 16. SPI MEMORY MAP (Continued)
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 0
(LSB)
Def. Value
(Hex)
Indexed/
Global
Next
Clock
Edge
00h
G
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
other codes = reserved
00h
NOT
affected by
Soft Reset
G
Output Format [2:0]
000 = Pin Control
001 = Twos Complement
010 = Gray Code
100 = Offset Binary
other codes = reserved
00h
NOT
affected by
Soft Reset
G
Bit 2
Bit 1
reserved
Reserved
70
reserved
Reserved
71
phase_slip
72
clock_divide
73
output_mode_A
74
output_mode_B
DLL Range
0 = fast
1 = slow
DDR
Enable
(Note 13)
00h
NOT
affected by
Soft Reset
G
75
config_status
XOR
Result
XOR
Result
Read Only
G
76-BF
reserved
C0
test_io
00h
G
Device Test
Global Device Config/Control
60-6F
Reserved
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
other codes = reserved
Reserved
Output Test Mode [3:0]
User Test Mode [1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
0 = Off
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checker Board
5 = reserved
6 = reserved
7 = One/Zero Word
Toggle
8 = User Input
9-15 = reserved
C1
Reserved
00h
G
C2
user_patt1_lsb
B7
B6
B5
B4
Reserved
B3
B2
B1
B0
00h
G
C3
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C4
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C5
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C6-FF
reserved
Reserved
NOTE:
13. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal pull-up..
28
FN6804.2
September 10, 2009
KAD5514P
Equivalent Circuits
AVDD
TO
CLOCKPHASE
GENERATION
AVDD
CLKP
AVDD
CSAMP
1.6pF
TO
CHARGE
PIPELINE
Φ
F3
INP
Φ2
F
Φ1
F
Ω
1000O
CSAMP
1.6pF
AVDD
TO
CHARGE
PIPELINE
Φ3
F
INN
Φ2
F
Φ
F1
AVDD
11kO
Ω
CLKN
FIGURE 44. CLOCK INPUTS
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
Ω
75kO
AVDD
Ω
18kO
AVDD 11kO
Ω
FIGURE 43. ANALOG INPUTS
AVDD
Ω
18kO
Ω
75kO
OVDD
TO
SENSE
LOGIC
Ω
280O
INPUT
OVDD
OVDD
20kΩ
Ω
INPUT
Ω
75kO
Ω
75kO
TO
LOGIC
280Ω
FIGURE 45. TRI-LEVEL DIGITAL INPUTS
FIGURE 46. DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
OVDD
D[13:0]P
OVDD
OVDD
D[13:0]N
DATA
DATA
D[13:0]
DATA
2mA OR
3mA
FIGURE 47. LVDS OUTPUTS
29
FIGURE 48. CMOS OUTPUTS
FN6804.2
September 10, 2009
KAD5514P
Equivalent Circuits
(Continued)
AVDD
VCM
+
–
0.535V
FIGURE 49. VCM_OUT OUTPUT
72 Pin/48 Pin Package Options
The KAD5514 is available in both 72 pin and 48 pin
packages. The 48 pin package option supports LVDS DDR
only. A reduced set of pin selectable functions are available
in the 48 pin package due to the reduced pinout;
(OUTMODE, OUTFMT, and CLKDIV pins are not available).
Table 17 shows the default state for these functions for the
48 pin package. Note that these functions are available
through the SPI, allowing a user to set these modes as they
desire, offering the same flexibility as the 72 pin package
option. DC and AC performance of the ADC is equivalent for
both package options.
.
TABLE 17. 48 PIN SPI - ADDRESSABLE FUNCTIONS
FUNCTION
DESCRIPTION
DEFAULT STATE
CLKDIV
Clock Divider
Divide by 1
OUTMODE
Output Driver
Mode
LVDS, 3mA (DDR)
OUTFMT
Data Coding
Two’s Complement
ADC Evaluation Platform
Intersil offers an ADC Evaluation platform which can be used
to evaluate any of the KADxxxxx ADC family. The platform
consists of a FPGA based data capture motherboard and a
family of ADC daughtercards. This USB based platform
allows a user to quickly evaluate the ADC’s performance at a
user’s specific application frequency requirements. More
information is available at
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. Many complex board
designs benefit from isolating the analog and digital
sections. Analog supply and ground planes should be laid
out under signal and clock inputs. Locate the digital planes
30
under outputs and logic pins. Grounds should be joined
under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for
the analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to
analog ground (AVSS) and should be connected to a large
copper plane using numerous vias for optimal thermal
performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series
resistance. Tantalum is a good choice. For best
performance, keep ceramic bypass capacitors very close to
device pins. Longer traces will increase inductance, resulting
in diminished dynamic performance and accuracy. Make
sure that connections to ground are direct and low
impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
direct and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO)
which will not be operated do not require connection to
ensure optimal ADC performance. These inputs can be left
floating if they are not used. Tri-level inputs (NAPSLP,
OUTMODE, OUTFMT, CLKDIV) accept a floating input as a
valid state, and therefore should be biased according to the
desired functionality.
FN6804.2
September 10, 2009
KAD5514P
Definitions
Analog Input Bandwidth is the analog input frequency at
which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
Aperture Delay or Sampling Delay is the time required
after the rise of the clock input for the sampling switch to
open, at which time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a
set of samples.
Clock Duty Cycle is the ratio of the time the clock wave is at
logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any
code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In
dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages
that cause the lowest and highest code transitions to the
full-scale voltage less 2 LSB. It is typically expressed in
percent.
Integral Non-Linearity (INL) is the maximum deviation of
the ADC’s transfer function from a best fit line determined by
a least squares curve fit of that transfer function, measured
in units of LSBs.
Least Significant Bit (LSB) is the bit that has the smallest
value or weight in a digital word. Its value in terms of input
voltage is VFS/(2N - 1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will
never appear at the ADC output. These codes cannot be
reached with any input value.
Most Significant Bit (MSB) is the bit that has the largest
value or weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output
pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the
observed magnitude of a spur in the ADC FFT, caused by an
AC signal superimposed on the power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the
RMS signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio of
the RMS signal amplitude to the RMS sum of all other
spectral components below one-half the sampling frequency,
excluding harmonics and DC.
SNR and SINAD are either given in units of dB when the
power of the fundamental is used as the reference, or dBFS
(dB to full-scale) when the converter’s full-scale input power
is used as the reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the
RMS signal amplitude to the RMS value of the largest
spurious spectral component. The largest spurious spectral
component may or may not be a harmonic.
31
FN6804.2
September 10, 2009
KAD5514P
Revision History
DATE
REVISION
CHANGE
7/30/08
Rev 0a
10/23/08
FN6804.0
Converted to intersil template. Assigned file number FN6804. Rev 0 - first release (as preliminary datasheet) with new
file number.
Preliminary Datasheet Update
11/13/08
FN6804.0
Applied Intersil Standards
1/15/09
FN6804.0
P1; revised Key Specs
P2; added Part Marking column to Order Info
P4; moved Thermal Resistance to Thermal Info table and added Theta JA note 3 per packaging
P4-8; revisions throughout spec tables. Added notes 9 and 10 to Switching Specs.
P9; revised function for Pin 22 OUTMODE, Pin 23 NAPSLP and Pin 16 CLKDIV
P11; revised function for Pin 16 NAPSLP
P13-15; Added Typical Performance curves
P17; added Figs 25-26
P17; User Initiated Reset - revised 2nd sentence of 1st paragraph
P18; Serial Peripheral Interface- 1st paragraph; revised 4th sentence
P19; revised Nap/Sleep; revised 3rd sentence of 1st paragraph
P21; Serial Peripheral Interface- added 3rd sentence to 4th paragraph
P23; Address 0x24: Gain_Fine; added 2 sentences to end of 1st paragraph.
Revised Table 8
P24; removed Figure (PHASE SLIP: CLK÷2 MODE, fCLOCK = 500MHz)
Address 0x71: Phase_slip; added sentence to end of paragraph
P27; Changed AVDD to OVDD in Fig 46
P27; revised Fig 45
P27; Table 16; revised Bits7:4, Addr C0
Throughout; formatted graphics to Intersil standards
2/25/09
FN6804.1
Corrected 48 QFN pin description table on page 11 to show OVDD pins from “20, 27” to “20, 37”.
Changed “odd” bits N in Figure 1A - DDR to “even” bits N, Replaced POD L48.7x7E due to changed dimension from
“9.80 sq” to “6.80” sq. in land pattern
8/17/09
FN6804.2
1) Added nap mode, sleep mode wake up times to spec table
2) Added CSB,SCLK Setup time specs for nap, sleep modes
3) Added section showing 72pin/48pin package feature differences and default state for clkdiv,outmode,outfmt page 30
4) Changed SPI setup time specs wording in spec table
5) Added ‘Reserved’ to SPI memory map at address 25H
6) Renumbered Notes
7) Added test platform link on page 30
8) Added ddr enable note13 for 48 pin/72 pin options
9) Changed pin description table for 72/48 pin option, added DDR notes
10) changed multi device note in spi physical interface section to show 3-wire application.page 23
11) Update digital output section for ddr operation page 20
12) change to fig25and fig26 and description in text
13) Added connect note for thermal pad
14) Formatted Figures 25 and 26 with Intersil Standards,
15) Change to SPI interface section in spec table, timing in cycles now, added write, read specific timing specs.
16) Updated SPI timing diagrams, Figures 37, 38
17) Updated wakeup time description in “Nap/Sleep” on page 21.
18) Removed calibration note in spec table
19) Changed label in fig 46
20) Updated cal paragraph in user initiated reset section per DC.
8/24/09
FN6804.2
1) Changed tDHR spec needs from 1.5 to 3 cycles.
2) Moved 20k ohm label in fig 46 closer to resistor connected to ovdd
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
32
FN6804.2
September 10, 2009
KAD5514P
Package Outline Drawing
L48.7x7E
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 2/09
7.00
PIN 1
INDEX AREA
PIN 1
INDEX AREA
4X 5.50
A
6
B
37
6
48
1
36
44X 0.50
Exp. DAP
5.60 Sq.
7.00
(4X)
12
25
0.15
24
13
48X 0.25
48X 0.40
TOP VIEW
4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
C
0.10 C
0.08 C
SEATING PLANE
SIDE VIEW
44X 0.50
6.80 Sq
C
0 . 2 REF
5
48X 0.25
5.60 Sq
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
48X 0.60
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
33
FN6804.2
September 10, 2009
KAD5514P
Package Outline Drawing
L72.10x10D
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 11/08
10.00
A
4X 8.50
PIN 1
INDEX AREA
B
55
6
72
1
54
68X 0.50
Exp. DAP
6.00 Sq.
10.00
18
37
(4X)
PIN 1
INDEX AREA
6
0.15
36
19
72X 0.24
72X 0.40
TOP VIEW
4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
C
0.10 C
0.08 C
SEATING PLANE
68X 0.50
SIDE VIEW
72X 0.24
9.80 Sq
6.00 Sq
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
72X 0.60
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
34
FN6804.2
September 10, 2009