TECHNICAL DATA KK0066 DOT MATRIX LCD CONTROLLER &DRIVER The KK0066 is a dot matrix liquid crystal display controller & driver LSI that displays alphanumeric, characters and symbols. It drives dot matrix LCD under microcomputer control. All functions needed for dot matrix LCD drive are internally provided on one chip. FEATURES FUNCTION • Internal Memory - Character Generator ROM: 8320 bits - Character Generator RAM: 512 bit - Display Data RAM: 80 x 8 bits for 80 digits • Internal automatic reset circuit at power ON • Internal oscillation circuit • Power Supply Voltage: +5V ± 10% • LCD Driving Voltage for display: 0 ~ -5V(V5) • Duty factor selection (selected by programs) 1/8 duty: 5 x 7 dots format 1 line, 1/11 duty: 5 x 10 dots format 1 line 1/16 duty: 5 x 7 dots format 2 line • Bare chip available • Pin-to-Pin replacement for KS0066, HD44780, SED1278 • Character type dot matrix LCD driver & controller • Internal driver: 16 common and 40 segment signal output • Display character format: 5 x 7 dots + cursor, 5 x 10 dots + cursor • Easy interface with a 4-bit or 8-bit MPU • Display character pattern: 5 x 7 dots format: 192 kinds, 5 x 10 dots format: 32 kinds • The special character pattern can be programmable by Character Generator RAM directly • A customer character pattern can be programmable by mask option • Wide range of instruction function: Display clear, Cursor home, Display ON/OFF, Display shift Cursor ON/OFF, Display character blink, Cursor shift ODERING INFORMATION Type KK0066 - 00 KK0066 - 01 CGROM English Numberal English Japanese Numberal KK0066 - XX Cyrillic Custom font (XX – ROM code) ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit Power Supply Voltage VDD - 0.3 ~ 7.0 V Driver Supply Voltage V1 ~ V 5 VDD - 13.5 ~ VDD + 0.3 V VI -0.3 ~VDD + 0.3 Input Voltage Operating Temperature Storage Temperature Ta Tstg V - 20 ~ + 75 o - 55 ~ + 125 o C C Notes: Must keep the relation of VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 1 KK0066 BLOCK DIAGRAM Power supply for LCD Drive V1 Par allel/ Ser ial Data conversion Circuit V2 V3 V4 V5 5 5 Busy Flag Char acter Gener ator ROM 8320 bits Cursor Blink Control Circuit Char acter Gener ator RAM 512 bits DB0~DB3 4 DB4~DB7 4 8 8 I/ O Buffer SEG1 8 Segment to 40 - bit 40 - bit SEG40 Shif t 40 L at ch 40 Sign al 40 Dr iver Regist er Cir cuit 7 R/ W RS E 8 Data Register 7 8 Instruction Register 8 7 Instruction Decoder 7 Display Data RAM 80 x 8 bits D 7 Address Counter 7 OSC1 OSC2 Timing Gener ation Circuit 16 - bit Shift 16 Register COM1 to Common COM16 Sign al 16 Driver CLK1 CLK2 M V DD V SS 2 KK0066 ELECTRICAL CHARACTERISTICS (Ta = 25oC, VDD = +5V, VSS = 0V unless otherwise specified) Characteristic Symbo l Operating Voltage VDD Operating Current (*1) IDD HIGH Input Voltage VIH LOW Input Voltage HIGH Output Voltage LOW Output Voltage Driver Voltage Descending Test Condition VOL VCOM Internal oscillation or external clock fOSC = 270KHz VDD E, DB0 ~ DB7, R/W, RS -0.3 0.6 OSC1 -0.2 1.0 IOH = -0.205 mA DB0 ~ DB7 2.4 IOH = -40µA CLK1, CLK2, M, D 0.9VDD IOL = 1.2mA DB0 ~ DB7 0.4 IOL = 40µA CLK1, CLK2, M, D 0.1VD IO = ± 0.1mA COM1 ~ COM16 1.0 SEG1 ~ SEG40 1.0 V -250 µA 125 250 350 46 50 55 KH z % 0.2 µs 0.2 µs KH z Freque ncy(*1) Duty fEC tF LCD Driving Voltage (*2) VLCD1 VLCD2 VDD – V5 1/5 bias 1/4 bias OSC1, OSC2 V1 ~ V5 V -125 -50 Rf = 91KΩ ± 2% V µA RS, R/W, DB0 ~ DB7 OSC1 V 1 VCC = 5V (test pull up R) DUTY tR V D IIL fOSC2 0.6 VDD-1.0 Input LOW Current Ceramic Resonator Oscillation Frequency (*1) V OSC1 -1 fOSC1 5.5 VDD E Rise time Fall time Internal Clock Frequency(*1) Uni t 2.2 VIN =0V ~ VDD Clock Max 0.35 ILKG External Typ E, DB0 ~ DB7, R/W, RS VSEG Input Leakage Current Min 4.5 VIL VOH Applicable Terminals 190 270 350 245 250 255 4.6 10.0 3.0 10.0 V 3 KK0066 Notes: *1). Oscillation circuit Resistor circuit OSC1 External clock circuit OSC2 OSC1 OSC2 Rf Rf : 91k Ω +2% Frequency input open *2). Input the voltage listed in table below to V1 ~ V5 Duty 1/8, 1/11 1/16 Bias 1/4 1/5 Power supply V1 VDD – VLCD/4 VDD – VLCD/5 V2 VDD – VLCD/2 VDD – 2VLCD/5 V3 VDD – VLCD/2 VDD – 3VLCD/5 V4 VDD – 3VLCD/4 VDD – 4VLCD/5 V5 VDD – VLCD VDD – VLCD *VLCD is the LCD driving voltage, refer to the initial set of the instruction code. AC CHARACTERISTICS (VDD = 5V, VSS = 0V, Ta = 25oC) (1) Write mode (Writing data from MPU to KK0066) Characteristic Symbol Test pin Min E Cycle Time tC E 500 E Rise Time tR E 25 ns E Fall Time tF E 25 ns E Pulse Width (High, Low) tW E 220 ns R/W and RS Set-up Time tSU1 R/W, RS 40 ns R/W and RS Hold Time tH1 R/W, RS 10 ns Data Set-up Time tSU2 DB0 ~ DB7 60 ns Data Hold Time tH2 DB0 ~ DB7 10 ns RS V IH1 V IH1 VIL1 VI L1 t SU1 Typ Max Unit ns t H1 R/ W VIL1 VIL1 t H1 tW VIL1 E tR t SU2 t H2 V IH1 DB0 ~ DB7 V IH1 Valid Data VI L1 V IL1 tC 4 KK0066 (2) Read mode (Reading data from KK0066 to MPU) Characteristic Symbol Test pin Min Typ Max Unit E Cycle Time tC E 500 E Rise Time tR E 25 ns E Fall Time tF E 25 ns E Pulse Width (High, Low) tW E 220 ns R/W and RS Set-up Time tSU1 R/W, RS 40 ns R/W and RS Hold Time tH1 R/W, RS 10 ns Data Output Delay Time tD DB0 ~ DB7 Data Hold Time tH2 DB0 ~ DB7 ns 120 20 ns ns (3) Interface mode with IZ0065 Characteristic Symbol Test pin Min Clock Pulse Width High tWCKH CLK 800 ns Clock Pulse Width Low tWCKL CLK 800 ns Data Set-up Time tSU D 300 ns Data Hold Time tDH D 300 ns Clock Set-up Time tCSU CLK 500 ns M Delay Time tDM M -1000 0.9VDD Typ Max 1000 Unit ns 0.9V DD CLK1 t WCKH t WCKH t CSU CLK2 0.9VDD 0.9V DD 0.1V DD 0.1V DD t WCK1 t CSU D M 0.1V DD 0.9VDD 0.1VDD t SU 0.9V DD 0.1V DD t DM 0.9V DD t DM 5 KK0066 TERMINAL DESCRIPTION Pin INP/ OUT VDD VSS Name Operating Voltage Power V1 – V5 DESCRIPTION INTERFACE For logical circuit (+5V ± 10%) Power 0V(GND) Supply Negative Supply Voltage Bias voltage level for LCD driving SEG1– SEG40 Output Segment output Segment signal output for LCD driving LCD COM1– COM16 Output Common output Common signal output for LCD driving LCD OSC1 Input Oscillator Both pin connected to Rf resistor or ceramic resonator for internal oscillator circuit. In case of external frequency use only, the frequency is input to OSC1 terminal. Resistor or OSC2 Output CLK1 Data latch clock Clock output terminal for the serially transferred data to be latched to the driver. Data shift clock Clock output terminal used when D terminal data output shifts the inside of the driver. M Alternated signal for LCD driver output The alternating signal to convert LCD drive waveform to AC. D Display data interface Character pattern data, which is corresponding to each common signal, is supplied to driver serially. CLK2 E Output Input R/W RS DB0 – DB7 Input/O utput IZ0065 Selection Low Non selection Start anable signal to read or write the data Read/Write R/W signal input is used to select the read/write mode Data interface Resonator High Enable Register select Ceramic MPU High Read mode Low Write mode Register selection input High Data register read and write) (for Low Instruction register (for write), Busy flag, address counter (for read) Used for data transfer between the MPU and KK0066. These terminals are for data bus with bidirectional three-state. Initial 4 bit (DB0-DB3) are not used during 4 bit operation (DB7 can be used as a busy flag) 6 KK0066 CONTROL AND DISPLAY COMMANDS Command RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Executi on time (fOSC=2 50KHz) DISPLAY CLEAR RETURN HOME ENTRY MODE SET L L L L L L L L L H 1.64 ms L L L L L L L L H X 1.64 ms L L L L L L L H I/D SH 40µs Remark Cursor move to first digit *I/D: set cursor move direction I/D H L Increase Decrease *SH: Specifies shift of display SH H L DISPLAY ON/OFF L L L L L L H D C B 40µs Display is shifted Display is not shifted *Display D H L Display on Display off *Cursor C H L Cursor on Cursor off *Blinking SHIFT L L L L L H S/C R/L X X B H L SC H L Blinking on Blinking off 40µs R/L Display shift Cursor move H L Right shift Left shift 7 KK0066 Command RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SET FUNCTIO N L L L L H DL N F X X Executi on time (fOSC=2 50KHz) 40µs SET CG RAM ADDRESS SET DD RAM ADDRESS READ BUSY FLAG & ADDRESS L L L L L H WRITE DATA READ DATA H L Write Data 46µs H H Read Data 46µs H CG RAM address (corresponds to cursor address) 40µs 40µs DD RAM address L H BF Remark DL H L 8 bits interface 4 bits interface N H L 2 line display 1 line display F H L 5x10 dots 5x7 dots CG RAM Data is sent and received after this setting DD RAM Data is sent and received after this setting 0µs BF Address Counter used for Both DD & CG RAM address H L Busy Ready -Reads BF indication internal operating is being performed. -Reads address counter contents Write data DD or CG RAM Read data from DD or CG RAM Note: X – Don’t care. 8 KK0066 APPLICATION CIRCUIT COM1~ COM16 DL1 FCS SHL1 SC1 ~ SC40 IZ0065 DL2 DR1 DR2 CL1 CL2 LCD Panel DL1 FCS SHL1 SC1 ~ SC40 IZ0065 DL2 DR1 DR2 CL1 CL2 DL1 FCS SHL1 SC1 ~ SC40 IZ0065 DL2 DR1 CL1 DR2 CL2 SHL2 M VSS VDD V6 V5 V4 V3 V2 V1 VEE V1 SHL2 M VSS VDD V6 V5 V4 V3 V2 V1 VEE V1 V2 SHL2 M VSS VDD V6 V5 V4 V3 V2 V1 VEE V2 V3 VDD V3 VLCD (1/5 bia s) GNDor other voltage V5 V4 V5 V4 VDD CLK2 CLK1 M VSS OSC2 OSC1 D SEG1~ SEG40 KK0066 DB0 ~ DB7 To MPU When IZ0065 is externally connected to the KK0066, you can increase the number of display digits up to 80 characters. 9 KK0066 PAD DIAGRAM (0,0) KK0066 Chip size Pa d size Unit PAD DIAGRAM : 4000 x 4900 : 120 x 120 : µm The chip substrate is connected to VDD. PAD LOCATION Pad No. Pad Name X Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1 OSC2 V1 V2 -2221 -2041 -1804 -1624 -1444 -1264 -1084 -904 -724 -544 -364 -184 -4 176 35 536 716 896 1076 1256 1436 1616 1920 2100 2299 2299 2299 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1830 -1552 -1372 -1192 Pad No. Pad Name X 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 2299 2299 2299 2299 2299 2299 2299 2299 2299 2299 2299 2299 2299 2188 2008 1812 1632 1436 1256 961 781 601 421 241 61 -119 -299 Y -1012 -832 -862 -472 -292 -112 68 248 428 608 788 1090 1270 1830 1830 1830 1830 1830 1830 1830 1830 1830 1830 1830 1830 1830 1830 Pad No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pad Name COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 X -530 -710 -941 -1121 -1301 -1481 -1661 -1841 -2036 -2216 -2298 -2298 -2298 -2298 -2298 -2298 -2298 -2298 -2298 -2298 -2298 -2298 -2298 -2298 -2298 -2298 Y 1830 1830 1830 1830 1830 1830 1830 1830 1830 1830 1404 1224 1044 864 684 504 324 144 -36 -216 -396 -576 -756 -936 -1116 -1296 10