PRELIMINARY Preliminary PRELIMINARY CMOS SRAM KM681002B, KM681002BI Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Range. Revision History Rev No. History Rev. 0.0 Initial release with Design Target. Apr. 1st, 1997 Design Target Rev.1.0 Release to Preliminary Data Sheet. 1. Replace Design Target to Preliminary. Jun. 1st, 1997 Preliminary Rev.2.0 Release to Final Data Sheet. 2.1. Delete Preliminary 2.2. Delete 32-SOJ-300 package 2.3. Delete L-version. 2.4. Delete Data Retention Characteristics and Waveform. 2.5. Add Capacitive load of the test environment in A.C test load 2.6. Change D.C characteristics Previous spec. Changed spec. Items (8/10/12ns part) (8/10/12ns part) Icc 160/150/140mA 160/155/150mA Isb 30mA 50mA Feb. 25th, 1998 Final Draft Data Remark The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquart ers. -1- Rev 2.0 February 1998 PRELIMINARY Preliminary PRELIMINARY CMOS SRAM KM681002B, KM681002BI 128K x 8 Bit High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 8,10,12ns(Max.) • Low Power Dissipation Standby (TTL) : 50 mA(Max.) (CMOS) : 10 mA(Max.) Operating KM681002B - 8 : 160 mA(Max.) KM681002B - 10 : 155 mA(Max.) KM681002B - 12 : 150 mA(Max.) • Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Standard Pin Configuration KM681002BJ : 32-SOJ-400 KM681002BT: 32-TSOP2-400F The KM681002B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681002B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung ′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681002B is packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward. ORDERING INFORMATION KM681002B -8/10/12 Commercial Temp. KM681002BI -8/10/12 Industrial Temp. PIN CONFIGURATION (Top View) FUNCTIONAL BLOCK DIAGRAM Clk Gen. Pre-Charge Circuit A0 1 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CS 5 28 OE I/O1 6 27 I/O8 I/O2 7 26 I/O7 Vcc 8 Vss 9 A0 A2 A3 A4 A5 Row Select A1 Memory Array 256 Rows 512x8 Columns I/O3 10 A6 A7 I/O1~I/O8 Data Cont. I/O Circuit Column Select CLK Gen. SOJ/ 25 Vss 24 Vcc TSOP2 23 I/O6 I/O4 11 22 I/O5 WE 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 PIN FUNCTION A8 A9 A10 A11 A12 A13 A14 A15 A16 Pin Name A0 - A16 Pin Function Address Inputs CS WE Write Enable WE CS Chip Select OE Output Enable OE I/O1 ~ I/O8 -2- Data Inputs/Outputs VCC Power(+5.0V) VSS Ground N.C No Connection Rev 2.0 February 1998 PRELIMINARY Preliminary PRELIMINARY CMOS SRAM KM681002B, KM681002BI ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Rating Unit VIN, VOUT -0.5 to 7.0 V Voltage on V CC Supply Relative to V SS VCC -0.5 to 7.0 V Power Dissipation PD 1.0 W Voltage on Any Pin Relative to V SS TSTG -65 to 150 °C Commercial TA 0 to 70 °C Industrial TA -40 to 85 °C Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 - VCC + 0.5** V Input Low Voltage VIL -0.5* - 0.8 V NOTE: The above parameters are also guaranteed at industrial temperature range. * VIL(Min) = -2.0V a.c(Pulse Width≤6ns) for I≤20mA ** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤6ns) for I≤20mA DC AND OPERATING CHARACTERISTICS (TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified) Parameter Symbol Min Test Conditions Max Unit Input Leakage Current ILI VIN = VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA 8ns - 160 mA 10ns - 155 12ns - 150 Standby Current Output Low Voltage Level Output High Voltage Level ISB Min. Cycle, CS=VIH - 50 mA ISB1 f=0MHz, CS ≥VCC-0.2V, VIN≥VCC-0.2V or V IN≤0.2V - 10 mA VOL IOL=8mA - 0.4 V VOH IOH=-4mA 2.4 - V - 3.95 V VOH1* IOH1=-0.1mA NOTE: The above parameters are also guaranteed at industrial temperature range. * VCC=5.0V, Temp.=25°C CAPACITANCE *(TA=25°C, f=1.0MHz) Item Symbol Test Conditions MIN Max Unit Input/Output Capacitance CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 6 pF * NOTE : Capacitance is sampled and not 100% tested. -3- Rev 2.0 February 1998 PRELIMINARY Preliminary PRELIMINARY CMOS SRAM KM681002B, KM681002BI AC CHARACTERISTICS (TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below NOTE: The above test conditions are also applied at industrial temperature range. Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ Output Loads(A) +5.0V RL = 50Ω DOUT 480Ω VL = 1.5V ZO = 50Ω DOUT 30pF* 255Ω 5pF* * Including Scope and Jig Capacitance * Capacitive Load consists of all components of the test environment. READ CYCLE Parameter Symbol KM681002B-8 KM681002B-10 KM681002B-12 Min Max Min Max Min Max Unit Read Cycle Time tRC 8 - 10 - 12 - ns Address Access Time tAA - 8 - 10 - 12 ns Chip Select to Output tCO - 8 - 10 - 12 ns Output Enable to Valid Output tOE - 4 - 5 - 6 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 4 0 5 0 6 ns Output Disable to High-Z Output tOHZ 0 4 0 5 0 6 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - 0 - ns Chip Selection to Power DownTime tPD - 8 - 10 - 12 ns NOTE: The above parameters are also guaranteed at industrial temperature range. -4- Rev 2.0 February 1998 PRELIMINARY Preliminary PRELIMINARY CMOS SRAM KM681002B, KM681002BI WRITE CYCLE Parameter Symbol KM681002B-8 KM681002B-10 KM681002B-12 Min Max Min Max Min Max Unit Write Cycle Time tWC 8 - 10 - 12 - ns Chip Select to End of Write tCW 6 - 7 - 8 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 6 - 7 - 8 - ns Write Pulse Width( OE High) tWP 6 - 7 - 8 - ns Write Pulse Width( OE Low) tWP1 8 - 10 - 12 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 4 0 5 0 6 ns Data to Write Time Overlap tDW 4 - 5 - 6 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - 3 - ns NOTE: The above parameters are also guaranteed at industrial temperature range. TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Valid Data Previous Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOE tOHZ OE tOH tOLZ tLZ(4,5) Data out Valid Data VCC ICC Current ISB tPU tPD 50% 50% -5- Rev 2.0 February 1998 PRELIMINARY Preliminary PRELIMINARY CMOS SRAM KM681002B, KM681002BI NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL levels. 4. At any given temperature and voltage condition, t HZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tWR(5) tAW tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW (10) (9) High-Z(8) Data out -6- Rev 2.0 February 1998 PRELIMINARY Preliminary PRELIMINARY CMOS SRAM KM681002B, KM681002BI TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled) tWC Address tAW tWR(5) tCW(3) CS tAS(4) tWP(2) WE tDW High-Z Data in Data Valid tLZ High-Z tWHZ(6) High-Z(8) High-Z Data out tDH NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X X* Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC * NOTE : X means Don′t Care. -7- Rev 2.0 February 1998 PRELIMINARY Preliminary PRELIMINARY CMOS SRAM KM681002B, KM681002BI PACKAGE DIMENSIONS 32-SOJ-400 Units:millimeters/Inches #17 10.16 0.400 #32 11.18 ±0.12 0.440 ±0.005 9.40 ±0.25 0.370 ±0.010 0.20 #1 #16 0.008 0.69 0.027 MIN 21.36 MAX 0.841 20.95 ±0.12 0.825 ±0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 ( 0.95 ) 0.0375 +0.10 -0.05 +0.004 0.017 -0.002 0.43 0.71 1.27 0.050 +0.10 -0.05 +0.004 -0.002 3.76 MAX 0.148 0.10 MAX 0.004 +0.10 -0.05 0.028 +0.004 -0.002 32-TSOP2-400F 0~8° 0.25 ( 0.010 ) #17 0.45 ~0.75 0.018 ~ 0.030 11.76 ±0.20 0.463 ±0.008 #1 10.16 0.400 #32 ( 0.50 ) 0.020 #16 0.15 +0.10 -0.05 0.006 +0.004 -0.002 21.35 MAX 0.841 20.95 ±0.10 0.825 ±0.004 1.00 ±0.10 0.039 ±0.004 ( 0.95 ) 0.037 0.40 ±0.10 0.016 ±0.004 1.27 0.050 1.20 0.047MAX 0.10 MAX 0.004 MAX 0.05 0.002MIN -8- Rev 2.0 February 1998