KM68V1000B, KM68U1000B Family CMOS SRAM Document Title 128K x8 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial draft August 12, 1995 Preliminary 1.0 Finalize April 12, 1996 Final 2.0 Revise - Change datasheet format March 7, 1998 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. Revision 2.0 March 1998 KM68V1000B, KM68U1000B Family CMOS SRAM 128K x8 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology : Poly Load • Organization : 128Kx8 • Power Supply Voltage : KM68V1000B family : 3.0~3.6V KM68U1000B family : 2.7~3.3V • Low Data Retention Voltage : 2V(Min) • Three state output and TTL Compatible • Package Type : 32-SOP, 32-TSOP1-0820F/R The KM68V1000B and KM68U1000B families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range KM68V1000BL/L-L KM68U1000BL/L-L KM68V1000BLE/LE-L KM68U1000BLE/LE-L KM68V1000BLI/LI-L KM68U1000BLI/LI-L Commercial(0~70°C) 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V 3.0~3.6V 2.7~3.3V Extended(-25~85°C) Industrial(-40~85°C) Speed(ns) Standby (ISB1, Max) PKG Type Operating (ICC2, Max) 50/15µA 50/15µA 701)/100 100 701)/100 100 701)/100 100 100/20µA 50/15µA 40mA 32-SOP 32-TSOP1- R/F 100/20µA 50/15µA 1. The parameter is measured with 30pF test load. PIN DESCRIPTION N.C 1 32 A16 2 31 A14 3 30 A12 4 29 A7 5 28 A6 6 27 A5 7 26 A11 A9 A8 A13 WE VCC CS2 A15 A15 VCC CS2 NC A16 WE A14 A12 A13 A7 A6 A8 A5 A9 A4 A4 8 25 A11 A3 9 24 OE A2 10 23 A1 11 22 32-SOP A0 12 21 I/O1 13 20 I/O2 14 19 I/O3 15 18 VSS 16 17 A4 A10 A5 A6 CS1 A7 I/O8 A12 A14 I/O7 A16 NC I/O6 A15 I/O5 VCC CS2 I/O4 A13 WE A8 A9 A11 FUNCTIONAL BLOCK DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-TSOP Type 1 - Forward 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS1 A10 OE Clk gen. Precharge circuit. A4 A5 A6 A7 A12 A13 Row select Memory array 512 rows 256×8 columns A14 A15 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32-TSOP Type 1 - Reverse A16 I/O1 I/O8 Data cont I/O Circuit Column select Data cont A0 A1 A2 A3 A8 A9 A10 A11 Name CS1,CS2 Function Chip Select Inputs OE Output Enable Input WE Write Enable Input A0~A16 I/O1~I/O8 Address Inputs CS1 CS2 WE Control Logic OE Data Inputs/Outputs Vcc Power Vss Ground N.C No Connection SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Revision 2.0 March 1998 KM68V1000B, KM68U1000B Family CMOS SRAM PRODUCT LIST Commercial Temperarure Products (0~70°C) Part Name Function Extended Temperarure Products (-25~85°C) Industrial Temperarure Products (-40~85°C) Part Name Part Name Function Function KM68V1000BLG-7 KM68V1000BLG-10 KM68V1000BLT-7 KM68V1000BLT-10 KM68V1000BLR-7 KM68V1000BLR-10 32-SOP,70ns,3.3V,L 32-SOP,100ns,3.3V,L 32-TSOP F,70ns,3.3V,L 32-TSOP F,100ns,3.3V,L 32-TSOP R,70ns,3.3V,L 32-TSOP R,100ns,3.3V,L KM68V1000BLGE-7 KM68V1000BLGE-10 KM68V1000BLTE-7 KM68V1000BLTE-10 KM68V1000BLRE-7 KM68V1000BLRE-10 32-SOP,70ns,3.3V,L 32-SOP,100ns,3.3V,L 32-TSOP F,70ns,3.3V,L 32-TSOP F,100ns,3.3V,L 32-TSOP R,70ns,3.3V,L 32-TSOP R,100ns,3.3V,L KM68V1000BLGI-7 KM68V1000BLGI-10 KM68V1000BLTI-7 KM68V1000BLTI-10 KM68V1000BLRI-7 KM68V1000BLRI-10 32-SOP,70ns,3.3V,L 32-SOP,100ns,3.3V,L 32-TSOP F,70ns,3.3V,L 32-TSOP F,100ns,3.3V,L 32-TSOP R,70ns,3.3V,L 32-TSOP R,100ns,3.3V,L KM68V1000BLG-7L KM68V1000BLG-10L KM68V1000BLT-7L KM68V1000BLT-10L KM68V1000BLR-7L KM68V1000BLR-10L 32-SOP,70ns,3.3V,LL 32-SOP,100ns,3.3V,LL 32-TSOP F,70ns,3.3V,LL 32-TSOP F,100ns,3.3V,LL 32-TSOP R,70ns,3.3V,LL 32-TSOP R,100ns,3.3V,LL KM68V1000BLGE-7L KM68V1000BLGE-10L KM68V1000BLTE-7L KM68V1000BLTE-10L KM68V1000BLRE-7L KM68V1000BLRE-10L 32-SOP,70ns,3.3V,LL 32-SOP,100ns,3.3V,LL 32-TSOP F,70ns,3.3V,LL 32-TSOP F,100ns,3.3V,LL 32-TSOP R,70ns,3.3V,LL 32-TSOP R,100ns,3.3V,LL KM68V1000BLGI-7L KM68V1000BLGI-10L KM68V1000BLTI-7L KM68V1000BLTI-10L KM68V1000BLRI-7L KM68V1000BLRI-10L 32-SOP,70ns,3.3V,LL 32-SOP,100ns,3.3V,LL 32-TSOP F,70ns,3.3V,LL 32-TSOP F,100ns,3.3V,LL 32-TSOP R,70ns,3.3V,LL 32-TSOP R,100ns,3.3V,LL KM68U1000BLG-10 KM68U1000BLT-10 KM68U1000BLR-10 32-SOP,100ns,3.0V,L 32-TSOP F,100ns,3.0V,L 32-TSOP R,100ns,3.0V,L KM68U1000BLGE-10 KM68U1000BLTE-10 KM68U1000BLRE-10 32-SOP,100ns,3.0V,L 32-TSOP F,100ns,3.0V,L 32-TSOP R,100ns,3.0V,L KM68U1000BLGI-10 KM68U1000BLTI-10 KM68U1000BLRI-10 32-SOP,100ns,3.0V,L 32-TSOP F,100ns,3.0V,L 32-TSOP R,100ns,3.0V,L KM68U1000BLG-10L KM68U1000BLT-10L KM68U1000BLR-10L 32-SOP,100ns,3.0V,LL 32-TSOP F,100ns,3.0V,LL 32-TSOP R,100ns,3.0V,LL KM68U1000BLGE-10L KM68U1000BLTE-10L KM68U1000BLRE-10L 32-SOP,100ns,3.0V,LL 32-TSOP F,100ns,3.0V,LL 32-TSOP R,100ns,3.0V,LL KM68U1000BLGI-10L KM68U1000BLTI-10L KM68U1000BLRI-10L 32-SOP,100ns,3.0V,LL 32-TSOP F,100ns,3.0V,LL 32-TSOP R,100ns,3.0V,LL FUNCTIONAL DESCRIPTION CS1 CS2 OE WE I/O Pin Mode Power 1) 1) X High-Z Deselected Standby X1) High-Z Deselected Standby H X X1) L X1) 1) X L H H H High-Z Output Disabled Active L H L H Dout Read Active L H X1) L Din Write Active 1. X means don′t care(Must be in high or low status.) ABSOLUTE MAXIMUM RATINGS1) Item Symbol Ratings Unit Remark VIN,VOU -0.5 to VCC+0.5 V - Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V - Power Dissipation PD 0.7 W - TSTG -65 to 150 °C - 0 to 70 °C KM68V1000BL, KM68U1000BL -25 to 85 °C KM68V1000BLE, KM68U1000BLE -40 to 85 °C KM68V1000BLI, KM68U1000BLI 260°C, 10sec (Lead Only) - - Voltage on any pin relative to Vss Storage temperature Operating Temperature Soldering temperature and time TA TSOLDER 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Revision 2.0 March 1998 KM68V1000B, KM68U1000B Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Product Min Typ Max Unit Supply voltage Vcc KM68V1000B Family KM68U1000B Family 3.0 2.7 3.3 3.0 3.6 3.3 V Ground Vss All Family 0 0 0 V Input high voltage VIH KM68V1000B, KM68U1000B Family 2.2 - Vcc+0.32) V Input low voltage VIL KM68V1000B, KM68U1000B Family -0.33) - 0.4 V Note: 1. Commercial Product : TA=0 to 70°C, unless otherwise specified Extended Product : TA=-25 to 85°C, unless otherwise specified Industrial Product : TA=-40 to 85°C, unless otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width≤30ns 3. Undershoot : -3.0V in case of pulse width≤30ns 4. Overshoot and undershoot are sampled, not 100% tested CAPACITANCE1) (f=1MHz, TA=25°C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 6 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled not, 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS1=VIH or CS2=VIL or WE=VIL, Vio=Vss to Vcc -1 - 1 µA Operating power supply current ICC CS1=VIL,CS2=VIH,VIN=VIH or VIL, IIO=0mA - 2 5 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V - 3 5 mA Average operating current ICC2 Min cycle, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH - 30 40 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.2 - - V Standby Current(TTL) ISB CS1=VIH, CS2=VIL - - 0.3 mA Low Power Low Low Power - 1.0 0.5 50 15 µA Low Power Low Low Power - 1.0 0.5 100 20 µA Low Power Low Low Power - 1.0 0.5 50 15 µA Low Power Low Low Power - 1.0 0.5 50 15 µA KM68V1000BL/L-L Standby Current (CMOS) KM68V1000BLE/LE-L KM68V1000BLI/LI-L ISB1 KM68U1000BL/L-L KM68U1000BLE/LE-L KM68U1000BLI/LI-L CS1≥Vcc-0.2V CS2≥Vcc-0.2V or CS2≤0.2V Other input =0~Vcc Revision 2.0 March 1998 KM68V1000B, KM68U1000B Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level : 0.4 to 2.2V Input rising and falling time : 5ns Input and output reference voltage :1.5V Output load(see right) : CL=100pF+1TTL CL=30pF+1TTL AC CHARACTERISTICS CL1) 1. Including scope and jig capacitance (Commercial product :TA=0 to 70°C, Extended product :TA=-25 to 85°C, Industrial product : TA=-40 to 85°C KM68V1000B Family:Vcc=3.0~3.6V, KM68U1000B Family:Vcc=2.7~3.3V) Speed Bins Parameter List Read Write Symbol 70ns Units 100ns Min Max Min Max Read cycle time tRC 70 - 100 - ns Address access time tAA - 70 - 100 ns Chip select to output tCO - 70 - 100 ns Output enable to valid output tOE - 35 - 50 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 25 0 30 ns Output disable to high-Z output tOHZ 0 25 0 30 ns Output hold from address change tOH 10 - 15 - ns Write cycle time tWC 70 - 100 - ns Chip select to end of write tCW 60 - 80 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 60 - 80 - ns Write pulse width tWP 55 - 70 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 30 ns Data to write time overlap tDW 30 - 40 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Symbol Test Condition CS1 ≥Vcc-0.2V VDR KM68V1000BL/L-L KM68V1000BLE/LE-L KM68V1000BLI/LI-L Data retention current IDR KM68U1000BL/L-L Vcc=3.0V CS1≥Vcc-0.2V CS2≥Vcc-0.2V or CS2≤0.2V KM68U1000BLE/LE-L KM68U1000BLI/LI-L Data retention set-up time tSDR Recovery time tRDR Min Typ Max Unit V 2.0 - 3.6 Low Power Low Low Power - 1 0.5 30 15 Low Power Low Low Power - - 50 20 Low Power Low Low Power - - 25 10 Low Power Low Low Power - - 25 15 0 - - 5 - - 1) See data retention waveform µA ms 1. CS≥VCC-0.2V, CS2≥VCC-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled) Revision 2.0 March 1998 KM68V1000B, KM68U1000B Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VlL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. Revision 2.0 March 1998 KM68V1000B, KM68U1000B Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS1 tAW CS2 tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z Revision 2.0 March 1998 KM68V1000B, KM68U1000B Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS1 tAW CS2 tCW(2) tWP(1) WE tDW tDH Data Valid Data in High-Z Data out High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled tSDR VCC Data Retention Mode tRDR 3.0/2.7V1) 2.2V VDR CS1≥VCC - 0.2V CS1 GND CS2 controlled Data Retention Mode VCC 3.0/2.7V1) CS2 tSDR tRDR VDR 0.4V CS2≤0.2V GND 1. 3.0V for KM68V1000B Family , 2.7V for KM68U1000B Family Revision 2.0 March 1998 KM68V1000B, KM68U1000B Family CMOS SRAM PACKAGE DIMENSIONS Units : millimeter(inch) 32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8° #17 14.12±0.30 0.556±0.012 #1 11.43±0.20 0.450±0.008 #16 2.74±0.20 0.108±0.008 3.00 0.118 MAX 20.87 0.822 MAX 20.47±0.20 0.806±0.008 0.20 +0.10 -0.05 0.008+0.004 -0.002 13.34 0.525 #32 0.80±0.20 0.031±0.008 0.10 MAX 0.004 MAX ( 0.71 ) 0.028 +0.100 -0.050 +0.004 0.016 -0.002 0.41 1.27 0.050 0.05 0.002 MIN Revision 2.0 March 1998 KM68V1000B, KM68U1000B Family CMOS SRAM PACKAGE DIMENSIONS Units : millimeter(inch) 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 -0.05 0.008+0.004 -0.002 0.20 20.00±0.20 0.787±0.008 #1 #32 8.40 0.331 MAX 0.50 0.0197 #17 #16 0.25 0.010 TYP 0.25 ) 0.010 8.00 0.315 ( 1.00±0.10 0.039±0.004 1.20 0.047 MAX 18.40±0.10 0.724±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.10MAX 0.004MAX 0.15 0.50 ) 0.020 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820R) +0.10 -0.05 0.008+0.004 -0.002 0.20 20.00±0.20 0.787±0.008 #16 #17 0.50 0.0197 #1 0.25 ) 0.010 8.00 0.315 8.40 0.331 MAX ( #32 1.00±0.10 0.039±0.004 0.05 0.002 MIN 1.20 0.047 MAX 18.40±0.10 0.724±0.004 +0.10 -0.05 +0.004 0.006 -0.002 0.15 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.10 MAX 0.004 MAX 0.25 0.010 TYP 0.50 ) 0.020 Revision 2.0 March 1998