L9758 Multiple supply for engine control Features ■ Buck converter pre-regulated supply rated for a minimum of 2 A (RMS) ■ Optional Boost converter for low battery conditions ■ 5 V, 2% @ 1 A, VDD5 low dropout (LDO) regulator ■ Programmable 3.3 V or 2.6 V, 2% @ 1 A, VDDL LDO regulator with external pass transistor ■ Programmable microcontroller core voltage LDO regulator, VCORE 2% @ 1 A with external voltage divider and pass transistor PowerSO-36 ■ Battery voltage thresholding - IGN ■ Logic level thresholding - PSU_EN ■ Programmable 1 V or 1.5 V, 10% @ 10 mA, standby memory regulator (VKAM) Description ■ Programmable 3.3 V or 2.6 V, 10% @ 10 mA alternate standby regulator (VSTBY) ■ Four 5 V ± 7 mV @ 50 mA protected tracking regulators, one of them with selectable external voltage reference. The L9758 is a multiple output voltage regulator utilizing linear, switchmode (buck and boost) and tracking regulators to support high end automotive microcontrollers used in powertrain applications. ■ Independent reset signals, RST5 and RSTL for the VDD5, VDDL supplies. The L9758 provides two standby power regulators as well as controllable LDO regulators. ■ Independent standby voltage monitor STANDBY_OK ■ Two power supply enable signals for different voltage level signals The L9758 has power on reset functionality and controlled slew rate of the VDD5, VDDL and VCORE. Table 1. Device summary Order code Temperature range Package Packing L9758 -40 °C to +125 °C PowerSO-36 Tube November 2010 Doc ID 14273 Rev 3 1/29 www.st.com 1 Contents L9758 Contents 1 Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 5 2/29 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 General DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 BUCK pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Boost pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 VDD5 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 VDDL linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 VCORE linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 VKAM linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 VSTBY linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9 VSA, VSB, VSC, VSD tracking linear regulator . . . . . . . . . . . . . . . . . . . . 18 4.10 RST5 and RSTL reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11 IGN and PSU_EN inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 STBY_OK signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 General function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 Switching pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 VDD5, VDDL and VCORE linear regulators . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 Tracking regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 VKAM and VSTBY linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.6 RESET monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.7 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.8 Reference current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 14273 Rev 3 L9758 6 Contents Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2.1 Entry into run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 Low voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 High voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Doc ID 14273 Rev 3 3/29 List of tables L9758 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. 4/29 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Control pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 General DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 BUCK pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Boost pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDD5 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VDDL linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCORE linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VKAM linear regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VSTBY linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VSA, VSB, VSC, VSD tracking linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RST5 reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RSTL reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IGN and PSU_EN inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STBY_OK signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Doc ID 14273 Rev 3 L9758 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current reference generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PowerSO-36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 14273 Rev 3 5/29 Pins configuration 1 Pins configuration Figure 1. Table 2. 6/29 L9758 Pins connection (top view) GND 1 36 SW VBAT 2 35 FDBK VBAT_SW 3 34 VB BOOST 4 33 VDD5 RES_S 5 32 VDDL_DRV GND_S 6 31 VDDL_FDBK VCORE_FDBK VBAT_S 7 30 IGN 8 29 VCORE_DRV IGN_ON 9 28 VPROG3 PSU_EN 10 27 CORE_DIS VSD 11 26 VPROG1 VSC 12 25 VPROG2 VSB 13 24 VKAM VSA 14 23 VSTBY TRACK_REF 15 22 STBY_OK REF_SEL 16 21 RST5 VS_DIS 17 20 RSTL REXT 18 19 RST_TIM Pins description Pin # Name Description 1 GND Power ground 2 VBAT Battery power source 3 VBAT_SW 4 BOOST External boost transistor predriver output 5 RES_S Boost (+) current comparator input 6 GND_S Boost (-) current comparator input 7 VBAT_S Battery feedback for boost controller 8 IGN Ignition switch 9 IGN_ON Ignition state 10 PSU_EN Power supply enable 11 VSD Tracking regulator D 12 VSC Tracking regulator C 13 VSB Tracking regulator B 14 VSA Tracking regulator A 15 TRACK_REF Switched battery power source Tracking A voltage reference Doc ID 14273 Rev 3 L9758 Pins configuration Table 2. Pins description (continued) Pin # Name 16 REF_SEL 17 VS_DIS 18 REXT 19 RST_TIM 20 RSTL VDDL regulator reset output 21 RST5 VDD5 regulator reset output 22 STBY_OK Standby regulator monitor 23 VSTBY Standby regulator output 24 VKAM Standby memory regulator output 25 VPROG2 Standby regulator voltage selection (VSTBY) 26 VPROG1 Standby memory regulator voltage selection (VKAM) 27 CORE_DIS 28 VPROG3 29 VCORE_DRV 30 VCORE_FDBK 31 VDDL_FDBK VDDL feedback 32 VDDL_DRV VDDL external pass transistor predriver output 33 VDD5 VDD5 linear regulator output 34 VB Switching preregulator output 35 FDBK Switching voltage feedback 36 SW Buck regulator switch output Table 3. Description Tracking A voltage reference selection Sensor supply disable External current reference resistance Reset timer adjustment VDDL and VCORE disable VDDL voltage selection VCORE external pass transistor predriver output VCORE feedback Control pins description Pin name Logic level Description Low Enter in Stand-by Mode if also PSU_EN is low High Enter in Run Mode Low IGN is high High IGN is low Low Enter in Stand-by Mode if also IGN is low High Enter in Run Mode Low Enable VSB, VSC, VSD tracking regulators High Disable VSB, VSC, VSD tracking regulators Low Voltage reference for VSA tracking regulator is VDD5 High Voltage reference for VSA tracking regulator is VTRACK_REF IGN IGN_ON PSU_EN VS_DIS Ref_Sel Doc ID 14273 Rev 3 Type of I/O Pull down Open drain Pull down Pull down Pull down 7/29 Pins configuration L9758 Table 3. Control pins description (continued) Pin name Logic level Description Low VDDL output regulator out of range (under voltage) High VDDL output regulator fully operational Low VDD5 output regulator out of range (under voltage) High VDD5 output regulator fully operational Low VKAM regulator output programmed to 1V High VKAM regulator output programmed to 1.5V Low VSTBY regulator output programmed to 2.6V High VSTBY regulator output programmed to 3.3V Low VDLL regulator output programmed to 2.6V High VDLL regulator output programmed to 3.3V Low Enable VDLL and VCORE linear regulators High Disable VDLL and VCORE linear regulators Low VSTBY output regulator out of range (under voltage) High VSTBY output regulator fully operational RSTL RST5 VPROG1 Open collector Open collector Pull up VPROG2 Pull up VPROG3 Pull up CORE_DIS STBY_OK 8/29 Type of I/O Doc ID 14273 Rev 3 Pull down Open drain L9758 Functional block diagram 2 Functional block diagram Figure 2. Functional block diagram VPROG2 STBY_OK STBY Vreg VBAT STBY 2.6V/3.3V, 10mA VBAT VSTBY 1 µF Bandgap VPROG1 10 µF Charge Pump Buck Switchmode Power Supply GND_S 1.5V, 1.0A SOFT START VPROG3 Rtim CORE_DIS VDDL_DRV Linear Voltage Controller 2.5V / 3.5V, 1.0A RESET Logic VDDL Undervoltage VDD5 Undervoltage Power On Reset EN_REG 22 uF VDDL VDDL_FDBK VDDL Oscillator / Divider VCORE_FDBK VCORE_FDBK VCORE REXT RST_TIM 22 µF FDBK VCORE_DRV Linear Voltage Controller Open Drain 10K Band Gap Ref. 22 µH VB (5 MHz) 0.1 SMPS Osc. RES_S 1 µF SW 300µF VBAT_S BOOST VKAM 1V/1.5V, 10mA VBAT_SW 22 µH Boost Control VBAT RUN VKAM Vreg Linear Voltage Regulator 5V, 1.0A RSTL 22 uF 2.4K RST5 VDD5 5.1K VDD5 10µF TRACK_REF REF_SEL Tracking Regulator 50mA VSA Tracking Regulator 50mA VSB Tracking Regulator 50mA VSC Tracking Regulator 50mA VSD VSA Analog MUX 2.2µF VSB VS_DIS EN_REG 51K IGN 2.2µF VSD 2.2µF IGN_ON 100 nF PSU_EN 2.2µF VSC Power Up/Dn EN_REG GND SOFT START Doc ID 14273 Rev 3 9/29 Operating conditions L9758 3 Operating conditions 3.1 Absolute maximum ratings This part may be irreparably damaged if taken outside the specified absolute maximum ratings. Operation above the absolute maximum ratings may also cause a decrease in reliability. Table 4. Absolute maximum ratings Symbol Parameter Value Unit -0.3 to 40 V Ignition input voltage (with at least 10K external resistance) -2.0 to 40 V VI-digital Digital input voltages (PSU_EN, VS_EN, VPROG1, VPROG2, VPROG3, VDDL/VCORE_EN, REF_SEL) -0.3 to 7 V VI-analog Analog input voltages (REXT, TRACK_REF, RST_TIM VDDL_FDBK, VCORE_FDBK) -0.3 to 7 V VB Linear regulator supply (VB) -0.3 to 40 V VFDBK Switching feedback (FDBK) -0.3 to 40 V Buck regulator switch output (SW) -2 to 40 V Digital output voltages (IGN_ON, RSTL, RST5, BOOST, STBY_OK) -0.3 to 7 V VOR Regulator output voltages (VDD5, VSTBY, VKAM) -0.3 to 7 V VVSx Regulator output voltages (VSA, VSB, VSC, VSD) -3 to 40 V VCORE_DRV, VDDL_DRV External regulator predriver output (VCORE_DRV, VDDL_DRV) -0.3 to 15 V 0 to 4.2 A VBAT,VBAT_SW Battery supply voltage , VBAT_S VIGN VSW VO-digital ISMPS Switching preregulator current Top Operating temperature -40 to 125 °C Tstg Storage temperature -50 to 150 °C Max junction temperature 150 °C Max ESD (human body model) ±2 KV Tj VESD Warning: 10/29 Exceeding these values might destroy this part. This part is not guaranteed to function properly at these ratings. The CMOS inputs and outputs should never go above 5V + 0.3V or below GND - 0.3V without protection (series resistance). If this occurs, the device might be destroyed by latch-up and/or the output levels might not be controlled by the inputs. Unused inputs must be connected to GND and unused outputs should be left open and programmed to a low state. Unused I/O pins should be programmed as outputs, left open, and programmed to a low state. Doc ID 14273 Rev 3 L9758 3.2 Operating conditions Operating ranges Full specification parameters cannot be guaranteed outside the operating ranges. Once the condition is returned to within the specified operating ranges, the part will recover with no damage or degradation. Table 5. Operating ranges Symbol Parameter Value Unit 4 to 26.5 VBAT, VBAT_SW, VBAT_S VIGN 3.3 Battery supply voltage Ignition input voltage (with at least 10K external resistance) 4 to 40 (t < 400ms) V 4 to 26.5 V VI-digital Digital input voltages (PSU_EN,VS_EN,VPROG1, VPROG2, VPROG3, VDDL/VCORE_EN, REF_SEL) -0.3 to 5.3 V VI-analog Analog input voltages (REXT, TRACK_REF, RST_TIM VDDL_FDBK, VCORE_FDBK) -0.3 to 5.3 V 0 to 2.5 A IAVE Switching preregulator average current Top Operating temperature -40 to 125 °C Tj Junction temperature -40 to 150 °C Thermal data Table 6. Symbol Rth(j-case) Thermal data Parameter Thermal resistance junction-to-case Doc ID 14273 Rev 3 Value Unit 2 °C/W 11/29 Electrical characteristics 4 L9758 Electrical characteristics All voltage values are, if not otherwise stated, relative to ground.Current flow into a pin is positive. If not otherwise stated, all rise times are between 10% and 90%, fall times between 90% and 10% and delay times at 50% of the relevant steps. 4.1 General DC characteristics Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Table 7. General DC characteristics Symbol IBAT_SW_SB IQ_OFF Parameter Test condition Min. Typ. Max. Unit - - 120 µA Quiescent current at pin VBAT = 0 V; BAT_SW VBAT_SW = 12 V Supply current in OFF state IVBAT_SW + IVBAT VLVI_LOW Low voltage inhibit Low threshold 3.5 - 3.9 V VLVI_HIGH Low voltage inhibit High threshold 4.0 - 4.5 V VLVI_HYS Low voltage inhibit hysteresis - 0.3 - 1 V Linear Start-up voltage - 3.8 - 4.8 V Rext Voltage - 1.18 - 1.24 V VS_EN input threshold - 0.8 - 2 V VVDDL/VCORE_EN VDDL/VCORE_EN input threshold - 0.8 - 2 V VPROG1_LOW PROG1 input Low Voltage - - - 0.8 V VPROG2_LOW PROG2 input Low Voltage - - - 0.8 V VPROG3_LOW PROG3 input Low Voltage - - - 0.8 V Vddl Power-up enable - 1 - 2 V VST VREXT VTH_VSEN VDDL_ENUP 12/29 Doc ID 14273 Rev 3 L9758 4.2 Electrical characteristics BUCK pre-regulator Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V; unless otherwise specified. Table 8. Symbol BUCK pre-regulator Parameter Test condition Min. Typ. Max. Unit 300 - 450 kHz - - 0.25 Ω FSW Operating frequency Rext = 10.0 kOhm ±1% VBAT_SW = 13.5 V RdsON High side switch ON resistance VBAT_SW = 6.0V IST_MAX Average current during start-up VB = 3.0V 0.3 - 0.7 A VBREG Output voltage 7.0V < VBAT_SW < 18V 0.25A < IVBAT <2.0A 5.5 - 6.1 V Vb100 100% Duty Cycle operation threshold 6.2 - 7.8 V Vb100h 100% Duty Cycle operation threshold hysteresis 0.05 - 0.8 V Voltage sensed at VBAT_SW pin ΔVpre Load regulation ΔIVB = 0.1A –2A VBAT_SW = 13.5V - - 400 mV Vrpre Voltage ripple, p-p L = 22µH, C = 22µF X7R VBAT_SW = 13.5V - - 300 mV Start time L = 22µH, C = 22µF X7R - - 1.4 ms Minimum duty cycle - 10 - 18 % Efficiency VBAT_SW = 13.5 V IVB = 0.5A VBAT_SW = 13.5V IVB = 2A 70 70 - - % L Rs Output Inductance - 15 22 30 75 µH mΩ C ESR Output capacitance - 10 0 - 100 160 µF mΩ Power-up overvoltage VBAT_SW < 26.5V 0.25A < IVBAT <2.0A 15 - 200 mV SW rising and falling time 7.0V < VBAT_SW < 18V IVBAT <2.0A (20%, 80%) 10 - 150 µs Ts DCmin EFF Ov Tr_sw Tf_sw Doc ID 14273 Rev 3 13/29 Electrical characteristics 4.3 L9758 Boost pre-regulator Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Table 9. Symbol FSW VB_REG Boost pre-regulator Parameter Test condition Min. Typ. Max. Unit Operating frequency Rext = 10.0 kOhm ±1% VBAT_SW = 13.5 V 300 - 450 kHz Output voltage 4.0 V < VBAT_S < 7 V, 0.25 A < IVB < 2.0 A 8.5 - 10 V 7.0 - 8.3 V 7.0 - 8.3 V BoostONth Boost enable threshold Voltage sensed at VBAT_S pin BoostOFFth Boost disable threshold VBOOST_HY Boost operation threshold hysteresis Voltage sensed at VBAT_S pin 0.05 - 0.9 V ΔVBOOST Load regulation ΔIVB = 0.1 A–2 A VBAT_S = 4 V - - 600 mV L = 22 µH, C = 300 µF X7RX7R VBAT_S = 4 V - - 600 mV - - 0.2 V VR_VBOOST Voltage ripple, p-p VOLB Boost predriver low level voltage Isink = 1 mA VOHB Boost predriver low level voltage Isource = 200 µA 4.8 - - V TRB Boost predriver rise time Cl = 1 nF 50 - 180 ns TFB Boost predriver fall time Cl = 1 nF 20 - 100 ns L Rs Output inductance - 15 22 30 75 µH mΩ C ESR Output capacitance - 100 10 300 900 200 µF mΩ Sensing resistor - 40 50 - mΩ RSENSE 14/29 Doc ID 14273 Rev 3 L9758 4.4 Electrical characteristics VDD5 linear regulator Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Table 10. Symbol VDD5 VDD5 linear regulator Parameter Output voltage Test condition 5 mA < IDD5 < 1 A VBAT_SW => 5.7 V 5 mA < IDD5 < 800 mA VBAT_SW = 5.5 V 5 mA < IDD5 < 1 A VBAT_SW ≥ 4 V IDD5_LIM Current limit VDD5 = 4.75 V CDD5 ESR Output capacitor RRDD5 Min. Typ. Max. Unit 5.1 4.9 V 4.0 3.3 1200 - 2500 mA Ceramic or Tantalum C = 4.7µF 4.7 0 - 100 160 µF mΩ Ripple rejection F = 375 kHz 26 - - dB VDD5_MAX Maximum overshoot ΔVB/Δt < 70 V/ms VBAT_SW = 4V ⇒ 8 V - - 5.5 V ΔVDD5/Δt Output voltage slew rate 5 mA < IDD5 < 1 A VBAT_SW = 13.5 V at power-up 10 - 20 V/ms Load current - 5 - 1000 mA VDD5lineR Line regulation 6.0 V < VB < 7 V -25 - +25 mV VDD5loadR Load regulation 5 mA < IDD5 < 1 A -25 - +25 mV VDD5-Vddl Start up VDD5-Vddl during start up 0.5 - 3.1 mV IDD5 4.5 VDDL linear regulator Tamb = -40 °C to 125 °C, VBAT= VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Table 11. Symbol VDDL linear regulator Parameter Test condition 5 mA < IDDL < 1 A, VPROG3 = Open 4.0 V < VBAT_SW < 18 V VDDL Min. Typ. 3.23 Output voltage Max. 3.37 - 5 mA <IDDL < 1 A, VPROG3 = Low 4.0 V < VBAT_SW < 18 V Unit 2.55 V 2.65 CDDL ESR Output capacitor Ceramic or Tantalum 4.7 0 - 100 160 µF mΩ RRDDL Ripple rejection F= 375 kHz 26 - - dB Doc ID 14273 Rev 3 15/29 Electrical characteristics Table 11. L9758 VDDL linear regulator (continued) Symbol Parameter VDDL_MAX ΔVDDL/Δt IDDL Maximum overshoot Test condition Min. Typ. 5 mA <IDDL < 1 A, VPROG3 = Open 4.0 V < VBAT_SW < 18 V ΔVB/Δt < 70 V/ms Max. Unit 3.75 - - 5 mA < IDDL < 1 A, VPROG3 = Low 4.0 V < VBAT_SW < 18 V ΔVB/Δt < 70 V/ms V 3.6 Output voltage slew 5 mA <IDDL < 1 A VBAT_SW =13.5 V rate at power-up 5 - 25 V/ms Load current 5 - 1000 mA VDDLlineR Line regulation 5.5 V < VBAT_SW < 7 V -8 - +8 mV VDDLloadR Load regulation 5 mA < IDDL< 1 A -8 - +8 mV 4.6 VCORE linear regulator Tamb = -40 °C to 125 °C, VBAT= VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Table 12. VCORE linear regulator Symbol Parameter Test condition Min. Typ. Max. Unit VCORE Output voltage 5mA < ICORE < 1A 4.0V < VBAT_SW < 18V 1.47 - 1.53 V CddL ESR Output capacitor Ceramic or Tantalum 4.70 0 - 100 160 µF mΩ RRddL Ripple rejection F= 375 kHz 26 - - dB Maximum overshoot 5 mA < ICORE < 1 A 4.0 V < VBAT_SW < 18 V - - 1.7 V Output voltage slew 5 mA < ICORE < 1 A VBAT_SW=13.5 V rate at power-up 5 - 25 V/ms Load current - 5 - 1000 mA Range of programmability Using external resistor divider 1.05 1.5 2.8 V VCORE_FBK Feedback voltage - 0.98 - 1.02 V VCORElineR Line regulation 5.5 V < VBAT_SW < 7 V -25 - +25 mV VCOREloadR Load regulation 5 mA < ICORE < 1 A -25 - +25 mV VCORE_M ΔVCORE/Δt ICORE VCORE_PROG 16/29 Doc ID 14273 Rev 3 L9758 4.7 Electrical characteristics VKAM linear regulator Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Table 13. VKAM linear regulator Symbol Parameter Test condition Min. Typ. 0.9 Unit 1.1 VKAM Output voltage 0.1mA < IVKAM < 10mA, VPROG1 = Low 4.0V < VBAT < 18V 0.1mA < IVKAM < 10mA, VPROG1 =Open 4.0V < VBAT< 18V CVKAM ESR Output capacitor Ceramic 0.1 0 - RRVKAM Ripple rejection F=375 kHz 26 - VKAM_M Maximum overshoot (absolute value relative to GND) 0.1 mA < IVKAM < 10 mA, VPROG1 = Low 4 V < VBAT < 18 V 0.1 mA < IVKAM < 10 mA, VPROG1 =Open 4 V < VBAT< 18 V Iddkamsh Current limit IKAM 1.37 Max. - 1.65 4.7 20 V µF mΩ dB 1.2 V - - VKAM = 0.5 V 11 - 50 mA Load current - 0.1 - 10 mA VKAMlineR Line regulation 6 V < VBAT < 18 V -25 - +25 mV VKAMloadR Load regulation 0.1 mA < IKAM < 10 mA -25 - +25 mV 4.8 1.7 VSTBY linear regulator Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Table 14. VSTBY linear regulator Symbol Parameter Test condition Min. Typ. Max. Unit VSTBY Output voltage 0.1 mA < ISTBY < 10 mA, VPROG2 = Low 4 V < VBAT< 18 V 0.1 mA < ISTBY < 10 mA, VPROG2 = Open 4 V < VBAT< 18 V CSTBY ESR Output capacitor Ceramic 0.1 0 - 10 20 µF mΩ RRSTBY Ripple rejection F = 350 kHz 26 - - dB VSTBY_M Maximum overshoot (absolute value relative to GND) 0.1 mA < ISTBY < 10 mA, VPROG2 = Low 4 V < VBAT< 18 V 0.1 mA < ISTBY < 10 mA, VPROG2 = Open 4 V < VBAT< 18 V 2.47 3.13 2.73 - 3.47 V 3.05 - - 3.75 V ISTBYsh Current limit VSTBY = 0.5 V 11 - 50 mA ISTBY Load current - 0.1 - 10 mA VSTBYlineR Line regulation 6 V < VBAT <18 V -25 - +25 mV VSTBYloadR Load regulation 0.1 mA < ISTBY < 10 mA -25 - +25 mV Doc ID 14273 Rev 3 17/29 Electrical characteristics L9758 4.9 VSA, VSB, VSC, VSD tracking linear regulator Table 15. VSA, VSB, VSC, VSD tracking linear regulator Tamb = -40 °C to 125 °C, VBAT= VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Symbol Parameter Test condition Min. Typ. Max. Unit ΔVTRK Output voltage tracking accuracy 1 mA < It1 < 50 mA, 6 V < VBAT_SW < 18 V 1 mA < It1 < 5 0mA, 4 V < VBAT_SW < 6 V -7 -50 - 10 50 mV ITRKsh Current limit Vtck = 4.75 V 51 - 100 mA Output load capacitor Ceramic or Tantalum 1 0 - 16 3 µF mΩ Minimum output capacitor for stability Ceramic or Tantalum 1 0 - 3 µF Ω RRTRK Ripple rejection F= 375 kHz 26 - - dB Vdrop Dropout voltage Iload = 50mA - - 300 mV TTSD Thermal shutdown Vtck = 4.75V (current limitation) 165 - 185 °C THYST Thermal hysteresis Vtck = 4.75V (current limitation) 5 - 15 °C Load current - 1 - 50 mA CTRK ESR Ctckmin ESRmin ITRK 4.10 RST5 and RSTL reset signals Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Table 16. Symbol RST5 reset signals Parameter Test condition Min. Typ. Max. Unit -3.0 - - µA - - 0.4 0.4 V IRST5_H Reset “high” leakage VRST5 = 5.15 V current VRST5_L Reset “low” output voltage VDD5 = 4.5 V Ire = 5 mA VDD5 = 1.0 V Ire = 1 mA VFTH_RST5 Reset threshold decreasing ΔVDD5/Δt < 0 4.5 - VDD5– 0.2 V VRTH_RST5 Reset threshold increasing ΔVDD5/Δt > 0 4.5 - VDD5– 0.07 V VHY_RST5 Reset threshold hysteresis - 50 - - mV tACT_RST5 Reset activation out of tolerance duration - 15 - 25 µs tDEL_RST5 Reset delay 4.7 kΩ < Rext < 47 kΩ 1 - 10 ms tERR_RST5 Reset delay accuracy Rext ±1% -15 - +15 % 18/29 Doc ID 14273 Rev 3 L9758 Table 17. Electrical characteristics RSTL reset signals Symbol Parameter Min. Typ. Max. Unit IRSTL_H Reset “high” leakage current VDDL= 5.15 V -3.0 - - µA VRSTL_L Reset “low” output voltage VDDL=5.0V Ire=5mA VDDL=1.0V Ire=1mA - - 0.4 0.4 V VFTH_RSTL Reset threshold decreasing ΔVDDL/Δt < 0, VPROG3=Low 2.375 - VDDL– 0.05 V VRTH_RSTL Reset threshold increasing ΔVDDL/Δt < 0, VPROG3=Low 2.375 - VDDL– 0.02 V VFTH_RSTL_O Reset threshold decreasing ΔVDDL/Δt < 0, VPROG3=Open 3.13 - VDDL– 0.05 V VRTH_RSTL_O Reset threshold increasing ΔVDDL/Δt < 0, VPROG3=Open 3.13 - VDDL– 0.02 V VHY_RSTL Reset threshold hysteresis - 40 - - mV tACT_RSTL Reset activation out of tolerance duration 15 - 25 μs tDEL_RSTL Reset delay 1nF < CEXT< 10nF; 4.7kΩ < Rext < 47kΩ 1 - 10 ms tERR_RSTL Reset delay accuracy Rext ±1% -15 - +15 % 4.11 Test condition IGN and PSU_EN inputs Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V, unless otherwise specified. Table 18. IGN and PSU_EN inputs Symbol Parameter Min. Typ. Max. Unit VTH_IGN IGN input threshold threshold @ IGN pin 2 - 3.6 V VHYS_IGN IGN input threshold hysteresis - 0.2 - 1.4 V RPD_IGN IGN pull-down resistor - 300 - 1100 kΩ VTH_PSUEN PSU_EN input threshold - 0.9 - 0.55* VSTBY V VHYS_PSUEN PSU_EN input threshold hysteresis - 0.2 - 0.8 V RPD_PSUEN PSU pull-down resistor - 50 - 230 kΩ VOL_IGNON IGN_ON “low” output voltage Iol=1mA 0.4 V 50 kΩ RIGN_EXT Test condition IGN external input resistance 10 Doc ID 14273 Rev 3 19/29 Electrical characteristics L9758 4.12 STBY_OK signal Table 19. STBY_OK signal Tamb = -40°C to 125°C, VBAT= VBAT_SW = 5.5 to 26.5V, unless otherwise specified. Symbol Parameter Conditions ΔVSTBY/Δt <0 Min Max Units -8,5 -3,5 % Th_stbyok VstanbyOK threshold Tstbydly STBY_OK filter time 15 25 µs Tstbyok STBY_OK delay accuracy 10 60 µs 0.4 V Vol_stbyok 20/29 STBY_OK low output voltage VSTBY=1V Istbyok =1mA Doc ID 14273 Rev 3 L9758 Functional description 5 Functional description 5.1 General function The L9758 is equipped with 9 linear voltage regulator. A buck boost switch mode power supply as pre regulator for the 7 main regulators is used to reduce the power consumption in the system. Two standby regulators can be used to bias the system on off-mode. This to regulator’s are equipped with a independent bandgap voltage reference. The current consumption of these two linear regulators is specified with less than 120 µA in OFF state. I these standby function is not used the current consumption on the battery can be reduced by not connecting the VBAT. Under this condition the device enters immediately in the run mode, the pin PSU_REN will lost his function. The quiescent current on the VBAT_SW can be reduced to maximum 10 µA with 12 V battery voltage in off mode. The main regulators can be activated with the IGN input. With a external resistor higher than 10 kohm in series to the IGN pin a battery compliant signal can be used. In the function block diagram a resistor value of 51 kohm is mention and a 100 nF capacitor for noise robustness on IGN. 5.2 Switching pre-regulator The switching pre-regulator is a buck or a buck-boost current control mode regulator. The optional boost operation for low battery conditions can be selected connecting external logic level low side NCH FET and an external diode in series to the inductor. The external parts required to complete the switching regulator are an inductor, recirculation diode and input and output filtering capacitor. The compensation network is inside the device. With a constant switching frequency of 350 kHz, the pre-regulator controls the output voltage (the voltage at the VB and FDBK pins) to the limits stated in the electrical characteristics table varying the duty cycle. The 350 kHz are related to REXT = 10 kΩ (see Section 5.8). At low battery voltages, in buck configuration, the pre-regulator runs with the duty cycle up to 100%. In buck-boost configuration normally it runs at 350 kHz but for a limited range of input voltage it could enter in pulse skipping mode to control the output voltage. A soft start function is implemented reducing the current limitation during the power-up phase. 5.3 VDD5, VDDL and VCORE linear regulators The VDD5 output is a fully integrated low drop out regulator. The VDDL and VCORE supplies will be implemented via an external N-channel pass MOS, with the control being internal to the IC. If the pass MOS is not used, two low current (max 30mA) regulator are available connecting directly VDDL_FDBK to VDDL_DRV and VCORE_FDBK to VCORE_DRV with a resistor divider.The output of the pre-regulator is used as the source of these supplies. VDD5 is a fixed 5V nominal output, while VDDL and VCORE are programmable. Doc ID 14273 Rev 3 21/29 Functional description L9758 The VDDL voltage is selectable with the VPROG3 pin: 2.5V if connected to GND and 3.3V if is left open (an internal pull-up is present). VCORE voltage is programmable connecting an external resistor divider at the feedback pin (VCORE_FDBK). Once programmed to a value at power-up, this value cannot change during the power cycle. It is the intent that the system run at a single fixed value for VDDL and VCORE for the life of the product. All the linear regulators start with a controlled slew rate when the pre-regulated voltage reaches VDDL_ENUP threshold as indicated in the electrical characteristics table. All the linear regulator are short circuit protected with a limited current. 5.4 Tracking regulators Four low drop-out tracking regulators (VSA, VSB, VSC and VSD) are supplied by the output of the switching pre-regulator. They track the output voltage of the VDD5 linear regulator with the accuracy as specified in the electrical characteristic table. The VSA regulator also tracks an external voltage reference (TRACK_REF pin) and the tracking voltage is selected by the REF_SEL pin. If REF_SEL is tied High (5V) then VTRK_REF is tracked. If REF_SEL is left open then VDD5 is tracked. There is an internal pull-down on REF_SEL. The tracking supplies are intended to drive loads that are external to the ECU so they are short circuit protected with the current limited. The outputs of the tracking regulators also withstand short circuit to the battery. A short circuit to GND, continuous or intermittent on one tracking supply will not affect any other supply, including the preregulator output voltage VB. In addition to these requirements, all sensor supplies shall be capable of operating with up to a 15µF load on the supply line. This load may be present during initial startup, or be applied after the supply has been powered up. In either case, the application of this load shall not cause the tracking regulators to be permanently disabled. VSB, VSC and VSD regulators can be disabled with VS_EN pin. 5.5 VKAM and VSTBY linear regulators These two outputs are fully integrated low quiescent current low drop out regulators. The input VBAT is used as the source of these supplies. These outputs are operational during both standby and run mode; these are the only outputs operational during standby (VBAT not present). The VKAM regulator has two programmable levels: 1.0V (VPROG1 pin connected to GND) or 1.5V (if this pin is left open, an internal pull-up is present). The VSTBY regulator has two programmable levels: 2.6V (VPROG2 pin connected to GND) or 3.3V (if this pin is left open, an internal pull-up is present). The STBY_OK pin indicates when the VSTBY is out of range (voltage below the threshold indicated in the electrical characteristic table). Once driven low it should stay low for a minimal amount of time allowing external circuitry to latch. 22/29 Doc ID 14273 Rev 3 L9758 5.6 Functional description RESET monitors RST5 is the reset signal tied to the VDD5 supply. This is an open collector active low signal that pulls low when VDD5 is out of range. RSTL is the reset signal for the VDDL supply. This is an open collector active low signal that pulls low when VDDL is out of range. RST5 and RSTL are also driven low when STBY_OK pin is driven low, regardless of the status of VDD5 and VDDL. Reset Delay is the time duration from when the output (VDD5 or VDDL) is within range to when the reset pin (RST5 or RSTL) is released. RST5 and RSTL use separate timers. This delay is programmable via an external resistor connected to RST_TIM pin. A value of 4.7 kΩ corresponds to 1 ms and 47 kΩ to 10 ms. All values in between are linear approximated. The timer delay is common however the attack and release times are only dependant on the condition of the respective supplies (VDD5 or VDDL). 5.7 Thermal protection The tracking regulators incorporate thermal limit with shutdown. When the junction temperature reaches the shutdown threshold, if there is a tracking regulator in current limitation, it switches off and all the other regulators stay on. When the temperature decrease the regulator restarts. The over temperature shutdown has an hysteresis to avoid thermal pumping. Reference current The L9758 provides a DC voltage at the REXT pin. An external resistor to ground creates a reference current which is mirrored internally for use in the device. The reference current is used to supply all the analog blocks and to charge and discharge an integrated capacitor to generate a 5 MHz clock for the switching functionality. Figure 3. Current reference generator Iref Iref + - 5.8 Rext + - Vref The circuit is designed for a 10 kΩ resistor. For all affected parameters, this resistor value is mentioned in the electrical characteristics section. Doc ID 14273 Rev 3 23/29 Operating modes 6 L9758 Operating modes There are two modes of operation of the power supply: standby and run mode. However during RUN mode, there are three input voltage regions: low voltage, normal voltage and high voltage. A brief definition and description of each of these operating regions is described below. 6.1 Standby mode STANDBY mode is defined by the following conditions: ● VBAT is within the required voltage range ● VBAT_SW may or may not be present ● IGN is in the OFF state ● PSU_EN is not asserted by the microprocessor During standby mode, all functions are shutdown except the two standby supplies, VKAM and VSTBY, and the circuitry monitoring IGN and PSU_EN. During standby mode, current consumption is minimized. The standby functions are powered from VBAT. There is no currents drawn from VBAT_SW or any other input except those required to perform the standby functions. Outputs, other than IGN_ON are disabled, sourcing nor sinking current. 6.2 Run mode RUN mode is defined by the following conditions: ● VBAT is within the required range ● VBAT_SW is within the required range ● Either IGN is in the Run state and/or PSU_EN is in the active state During RUN mode, all functions can be enabled. All functions listed above, with the exception of the standby functions, are powered by VBAT_SW. If VBAT is not present, the circuit is fully running with the exception of PSU_EN and the standby functions (VKAM and VSTBY). In this condition the entry into the RUN MODE can only be performed by the IGN pin and the circuit is kept running until IGN pin is in pulled low. 6.2.1 Entry into run mode RUN mode is entered when at least one of the two signals IGN_SW or PSU_EN goes in the active state. These two signals may be applied in any order or simultaneously. When the IGN input is valid, the active low IGN_ON signal is asserted. The design of VDD5, VDDL and VCORE regulators limits the slew rate of the output voltages during the start-up as indicated in the electrical characteristic table and ensures that VDD5 is always greater than VDDL and VCORE. As indicated in Figure 4, the switching regulator starts first with soft start control or reduced current limitation. When the VB voltage reaches the VDDL_ENUP threshold all the linear regulator start with controlled slew-rate. The slew-rate control is done controlling the slew 24/29 Doc ID 14273 Rev 3 L9758 Operating modes rate of the common voltage reference so the slew is different for each regulator because all start together and reach the steady-state at the same time but with different voltage levels. 6.3 Power down The power down sequence starts when both IGN and PSU_EN signal are low. In this phase there is no control of the linear regulator output voltages. The falling slew-rate is defined from load currents and load capacitors. A voltage comparator controls VDDL voltage and ensures that the VDDL supply voltage will drop below 2V before initiating a new power-up sequence. Figure 4. Power up/down sequence IGN or PSU_EN Vth_Start VB Soft start VDD5 Slew rate control VDDL VCORE Inductor current Current limitation RST5 RSTL 6.4 Low voltage operation When L9758 is up and running it is fully operational with the VBAT and VBAT_SW pin voltages down to VLVI_LOW. When L9758 is up and running and the supply voltages are less than 5.5V and are greater or equal to VLVI_LOW if the boost option is used the device is fully operational. If only the buck regulator is used the L9758 operates as follow: ● Switching regulator runs at 100% duty cycle ● VKAM and VSTBY regulators are fully operational ● VDDL fully operational ● VCORE fully operational ● VDD5 out of range with output voltage no less than 3.2V ● Tracking regulators out of range with output voltages no less than 3.2V ● Reset monitor RST5 and RSTL fully operational, with reset at RST5 pin in allowed Doc ID 14273 Rev 3 25/29 Operating modes 6.5 L9758 High voltage operation The L9758 is fully operational during jump start when the battery is temporarily replaced with a higher voltage source to aid starting the engine (26.5V for 1 minute). The L9758 is fully operational during positive battery transient such as load dump (40V maximum voltage with durations of up to 400ms). 26/29 Doc ID 14273 Rev 3 L9758 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 5. PowerSO-36 mechanical data and package dimensions DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.60 0.10 0.30 a2 MAX. 0.1417 0.0039 0.0118 3.30 0.1299 a3 0 0.10 b 0.22 0.38 0.0087 0.0039 0.0150 c 0.23 0.32 0.0091 0.0126 D 15.80 16.00 0.6220 0.6299 D1 9.40 9.80 0.3701 0.3858 E 13.90 14.5 0.5472 0.5709 E1 10.90 11.10 0.4291 0.4370 2.90 0.1142 E2 E3 5.80 e 0.2283 0.65 e3 0 H 15.50 h 0.8 0.2441 0.0256 11.05 G L 6.20 OUTLINE AND MECHANICAL DATA 0.4350 0.10 0.0039 15.90 0.6102 0.6260 1.10 0.0433 1.10 0.0315 N 10˚ (max) s 8˚ (max) 0.0433 PowerSO-36 Note: “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions are "a3", "E" and "G". 0096119 C Doc ID 14273 Rev 3 27/29 Revision history 8 L9758 Revision history Table 20. 28/29 Document revision history Date Revision Changes 12-Dec-2007 1 Initial release. 17-Nov-2010 2 Updated Section 1: Pins configuration. Updated Figure 2: Functional block diagram. Updated Section 3: Operating conditions. Updated Table 7: General DC characteristics and Table 12: VCORE linear regulator. Added Section 5.1: General function. Updated Section 5.2: Switching pre-regulator, Section 5.6: RESET monitors and Section 5.8: Reference current. Updated Section 5.3: VDD5, VDDL and VCORE linear regulators on page 21. 23-Nov-2010 3 Update Table 10, Table 11, Table 12, Table 13 and Table 14. Doc ID 14273 Rev 3 L9758 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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