Ordering number : EN5760 CMOS IC LC7535M Electronic Volume/Loudness Control with Serial Data Control and High Voltage-Handling Capacity Overview Feature The LC7535M is an electronic volume and loudness control IC that provides volume, balance, and loudness functions with a minimal number of external components and that can be controlled electronically. • High voltage-handling capacity: ±16 V. Functions 3216A-MFP30S Package Dimensions unit: mm [LC7535M] • Volume: Provides 81 positions from 0 dB to –79 dB in 1-dB steps and –∞. A balance function can be implemented by controlling the left and right volume levels independently. • Loudness: A loudness function can be implemented by attaching external capacitors at the output tap provided at the –20-dB position in the 5-dB step volume control. • S (select) pin: Up to two LC7535M chips can be used on the same bus. • Serial data input: The LC7535M supports communication with the controller in the CCB format. SANYO: MFP30S • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage Maximum input voltage Allowable power dissipation Conditions Ratings Unit VDD max VEE ≤ VSS < VCC < VDD VSS to VSS + 18 V VEE max VEE ≤ VSS < VCC < VDD VSS – 18 to VSS V VCC max VEE ≤ VSS < VCC < VDD VSS to VSS + 7 V VIN max1 CL, DI, CE 0 to VCC + 0.3 V VIN max2 L5dBIN, R5dBIN, L1dBIN, R1dBIN VEE – 0.3 to VDD + 0.3 V VIN max3 S VCC – 0.3 to VDD + 0.3 Ta ≤ 75°C Pd max V 250 mW Operating temperature Topr –30 to +75 °C Storage temperature Tstg –40 to +125 °C Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Supply voltage Input high-level voltage Input low-level voltage Symbol Conditions Ratings min typ Unit max VDD VDD VCC + 4.5 16 V VEE VEE –16 0 V VCC VCC VIH1 CL, DI, CE 4.5 VIH2 S VIL1 CL, DI, CE VIL2 S VCC 5 5.5 V VCC V 0.8 × (VDD – VCC) + VCC VDD V VSS 0.2 VCC V 0.8 VCC 0.2 × (VDD – VCC) + VCC V Continued on next page. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 53098RM (OT) No. 5760-1/9 LC7535M Continued from preceding page. Parameter Symbol Conditions Ratings min typ Unit max Input voltage amplitude VIN L5dBIN, R5dBIN, L1dBIN, R1dBIN Input pulse width tøw CL 1 µs µs VEE Setup time tset up CL, DI, CE 1 Hold time thold CL, DI, CE 1 Operating frequency topg CL VDD Vp-p µs 500 kHz Electrical Characteristics at Ta = 25°C, VSS = 0 V Parameter Total harmonic distortion Crosstalk Output at maximum attenuation Output noise voltage Total resistance Output off leakage current Symbol THD CT VOmin VN Conditions Ratings min VIN = 1 Vrms, f = 1 kHz, With all tone control settings flat, VDD – VEE = 30 V VIN = 1 Vrms, f = 1 kHz, With all tone control settings flat, RG = 1 kΩ, VDD – VEE = 30 V VIN = 1 V rms, f = 1 kHz, with the volume set at –∞, VDD – VEE = 30 V With all tone control settings flat, Rg = 1 kΩ IHF-A, VDD – VEE = 30 V typ Unit max 0.002 % 70 dB –95 dB 2 10 µV Rvol1 5-dB volume control block 75 kΩ Rvol2 1-dB volume control block 20 kΩ IOFF L5dBIN, R5dBIN, LCT1, RCT1, LCT2, RCT2, L5dBOUT, R5dBOUT, L1dBIN, R1dBIN, L1dBOUT, R1dBOUT, LVM, RVM –10 +10 Input high-level current IIH CL, DI, CE : VIN = VCC Input low-level current IIL CL, DI, CE : VIN = VSS IDD VDD = 16 V 1 mA ICC VCC = 5.5 V 1 mA Current drain 10 µA –10 µA µA Equivalent Circuit No. 5760-2/9 LC7535M Sample Application Circuit Test Circuit Total Harmonic Distortion With an identical circuit for the right channel No. 5760-3/9 LC7535M Output Noise Voltage With an identical circuit for the right channel Crosstalk Pin Assignment No. 5760-4/9 LC7535M Pin Descriptions Pin No. 2 Pin Function Equivalent circuit L5dBIN • 5-dB step attenuator inputs These inputs must be driven by low-impedance circuits. 29 R5dBIN 3 LCT1 28 RCT1 4 LCT2 27 RCT2 5 L5dBOUT • Loudness circuit connections Connect the high-band compensation capacitors between the CT1 and 5dBIN pins, and connect the low band compensation capacitors between the CT2 and the VM pins. • 5-dB step attenuator outputs These outputs must be accepted by circuits with an impedance of between 47 kΩ and 1 MΩ. 26 R5dBOUT 7 L1dBIN • 1-dB step attenuator inputs These inputs must be driven by low-impedance circuits. 24 R1dBIN 8 L1dBOUT • 1-dB step attenuator outputs These outputs must be accepted by circuits with an impedance of between 47 kΩ and 1 MΩ. 23 R1dBOUT 9 LVM 22 RVM 12 S 17 CL 18 DI 19 CE 10 VEE 13 VDD 14 VSS 21 VCC 1, 6, 11, 15, 16, 20, 25, 30 NC • Common connections for the volume control circuit. The impedance of the printed circuit board pattern connected to these pins must be kept as low as possible. Since the LVM, RVM, and VSS pins are not connected internally, they must be connected externally as required by the various specifications. When a single-sided power supply is used, the capacitors between VM and VSS become the residual resistance when the volume control is set at its maximum attenuation. This means that care is required in selecting the values of these capacitors. • Selection input for the address code in the data format. If this pin is connected to VDD, data will be accepted when the address code is 9, and if connected to VCC, data will be accepted when the address code is 8. • Input pins for the serial data used to control the device. These inputs must have an amplitude of 0 to 5 V. In applications in which any of microcontroller CL, DI, or CE may go high in backup mode (when VDD = VCC = 0 V), the signal lines must have series resistors of at least 2 kΩ inserted. • Power supply connections. All these pins must be connected to the corresponding power supply voltage. When power is first applied, the VCC voltage must not rise before VDD. • Unconnected (NC) pins Do not connect any signals or devices to these pins. No. 5760-5/9 LC7535M Control System Timing and Data Format The stipulated serial data must be input to the CL, DI, and CE pins to control the LC7535M. The data consists of a total of 20 bits, of which 4 bits are address and 16 bits are data. Left channel 1-dB step control (identical to the right channel) Left channel 5-dB step control (identical to the right channel) Address code S pin Right channel 5-dB step control Loudness 1: On 0: Off Set state Right channel 1-dB step control Set state Dummy * Note *: To minimize switching noise, applications should input dummy data in the following sequence: –79 dB → dummy → –∞ No. 5760-6/9 LC7535M Loudness Characteristics Volume Step Characteristics Output level — dB Volume attenuation — dB VSS = VM = 0 V, loudness on Frequency, f — Hz Step — dB Volume control set to -20 dB Volume control set to 0 dB Frequency, f — Hz THD – Frequency Characteristics (2) Total harmonic distortion, THD — % Total harmonic distortion, THD — % THD – Frequency Characteristics (1) 80-kHz low-pass weighting Overall 80-kHz low-pass weighting Volume control set to -10 dB Volume control set to 0 dB Frequency, f — Hz No. 5760-7/9 LC7535M THD – Power-Supply Voltage Characteristics (2) Total harmonic distortion, THD — % 80-kHz low-pass weighting Flat overall Volume control set to –20 dB 80-kHz low-pass weighting Power-supply voltage, VDD – VEE — V Power-supply voltage, VDD – VEE — V THD – Input Level Characteristics (1) THD – Input Level Characteristics (2) 80-kHz low-pass weighting Flat overall Input level, VIN – dBV Total harmonic distortion, THD — % Total harmonic distortion, THD — % Total harmonic distortion, THD — % THD – Power-Supply Voltage Characteristics (1) 80-kHz low-pass weighting Volume control set to –20 dB Input level, VIN – dBV No. 5760-8/9 LC7535M 80-kHz low-pass weighting Flat overall Output level, VO – dBV THD – Output Level Characteristics (2) Total harmonic distortion, THD — % Total harmonic distortion, THD — % THD – Output Level Characteristics (1) 80-kHz low-pass weighting Volume control set to –20 dB Output level, VO – dBV Usage Notes • The state of the internal analog switches are undefined when power is first applied. Applications should apply external muting to the output signal until the control data has been set up. • To prevent the high-frequency digital signals transmitted over the CL, DI, and CE pin lines from entering the analog signal system, these lines should either be covered by the ground pattern or shielded cables should be used. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5760-9/9