SANYO LC75811E

Ordering number : EN5915A
CMOS IC
LC75811E, 75811W
1/8 to 1/10 Duty Dot Matrix LCD Display Controller/Driver
Overview
Package Dimensions
The LC75811E and LC75811W are 1/8 to 1/10 duty dot
matrix LCD display controller/drivers that supports the
display of characters, numbers, and symbols. In addition to
generating dot matrix LCD drive signals based on data
transferred serially from a microcontroller, the LC75811E
and LC75811W also provide on-chip character display ROM
and RAM to allow display systems to be implemented easily.
unit: mm
3174-QFP80E
[LC75811E]
Features
• Controls and drives a 5 × 7, 5 × 8, or 5 × 9 dot matrix LCD.
• Supports accessory display segment drive (up to 60
segments)
• Display technique: 1/8 duty 1/4 bias drive (5 × 7 dots)
1/9 duty 1/4 bias drive (5 × 8 dots)
1/10 duty 1/4 bias drive (5 × 9 dots)
• Display digits: 12 digits × 1 line (5 × 7 dots),
11 digits × 1 line (5 × 8 or 5 × 9 dots)
• Display control memory
CGROM: 240 characters (5 × 7, 5 × 8, or 5 × 9 dots)
CGRAM: 16 characters (5 × 7, 5 × 8, or 5 × 9 dots)
ADRAM: 12 × 5 bits
DCRAM: 48 × 8 bits
• Instruction function
Display on/off control
Display shift function
• Provides a backup function based on low power modes.
• Serial data input supports CCB format communication
with the system controller.
• Independent LCD drive block power supply VLCD
• Provides a RES pin for LSI internal initialization
• RC oscillator circuit
SANYO: QFP80E
unit: mm
3220-SQFP80
[LC75811W]
SANYO: SQFP80
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1098RM (OT) No. 5915-1/27
LC75811E, 75811W
Pin Assignments (Top View)
LC75811E
LC75811W
No. 5915-2/27
LC75811E, 75811W
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input voltage
Symbol
Output current
Allowable power dissipation
Ratings
Unit
VDD
–0.3 to +7.0
V
VLCD max
VLCD
–0.3 to +11.0
V
VIN1
CE, CL, DI, RES
VIN2
OSCI
VIN3
Output voltage
Conditions
VDD max
VLCD1, VLCD2, VLCD3
VOUT1
OSCO
VOUT2
S1 to S60, COM1 to COM10
IOUT1
S1 to S60
IOUT2
COM1 to COM10
Pd max
–0.3 to +7.0
V
–0.3 to VDD + 0.3
V
–0.3 to VLCD + 0.3
V
–0.3 to VDD + 0.3
V
–0.3 to VLCD + 0.3
V
300
µA
Ta = 85°C
3
mA
200
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Allowable Operating Ranges at Ta = –40 to 85°C, VSS = 0 V
Parameter
Supply voltage
Input voltage
Symbol
Conditions
Ratings
min
typ
max
Unit
VDD
VDD
2.7
6.0
V
VLCD
VLCD
4.5
10.0
V
VLCD1
VLCD1
3/4 VLCD
VLCD
V
VLCD2
VLCD2
2/4 VLCD
VLCD
V
VLCD3
VLCD3
1/4 VLCD
VLCD
V
VIH1
CE, CL, DI, RES
0.8 VDD
6.0
V
VIH2
OSCI
0.7 VDD
VDD
V
VIL1
CE, CL, DI, RES
0
0.2 VDD
V
VIL2
OSCI
0
0.3 VDD
Recommended external resistance
ROSC
OSCI, OSCO
Recommended external capacitance
COSC
OSCI, OSCO
Guaranteed oscillation range
fOSC
OSC
150
Input high level voltage
Input low level voltage
33
220
300
V
kΩ
pF
600
kHz
Data setup time
tds
CL, DI: Figure 2
160
ns
Data hold time
tdh
CL, DI: Figure 2
160
ns
CE wait time
tcp
CE, CL: Figure 2
160
ns
CE setup time
tcs
CE, CL: Figure 2
160
ns
CE hold time
tch
CE, CL: Figure 2
160
ns
High level clock pulse width
tøH
CL: Figure 2
160
ns
Low level clock pulse width
tøL
CL: Figure 2
160
ns
Minimum reset pulse width
tWRES
1
µs
RES: Figure 3
No. 5915-3/27
LC75811E, 75811W
Electrical Characteristics in the Allowable Operating Ranges
Parameter
Symbol
Conditions
Hysteresis
VH
CE, CL, DI, RES
Input high level current
IIH
CE, CL, DI, RES, OSCI: VI = 6.0 V
Input low level current
Output high level voltage
Output low level voltage
Output middle level voltage*1
Oscillator frequency
Current drain
IIL
Ratings
min
typ
Unit
max
0.1 VDD
CE, CL, DI, RES, OSCI: VI = 0 V
V
5.0
µA
–5.0
µA
VOH1
S1 to S60: IO = –20 µA
VLCD – 0.6
V
VOH2
COM1 to COM10: IO = –100 µA
VLCD – 0.6
V
VOH3
OSCO: IO = –500 µA
VOL1
S1 to S60: IO = 20 µA
0.6
VOL2
COM1 to COM10: IO = 100 µA
0.6
V
VOL3
OSCO: IO = 500 µA
1.0
V
VDD – 1.0
V
V
VMID1
S1 to S60: IO ±20 µA
2/4 VLCD – 0.6
2/4 VLCD + 0.6
V
VMID2
COM1 to COM10: IO = ±100 µA
3/4 VLCD – 0.6
3/4 VLCD + 0.6
V
VMID3
COM1 to COM10: IO = ±100 µA
1/4 VLCD – 0.6
1/4 VLCD + 0.6
fOSC
OSCI, OSCO: ROSC = 33 kΩ, COSC = 220 pF
IDD1
VDD: power saving mode
IDD2
VDD: VDD = 6.0 V, output open, fOSC = 300 kHz
ILCD1
VLCD: power saving mode
ILCD2
VLCD: VLCD = 10.0 V, output open, fOSC = 300 kHz
210
V
300
390
kHz
5
µA
450
900
µA
5
µA
400
µA
200
Note *1: Excluding the bias voltage generation divider resistor built into the VLCD1, VLCD2, and VLCD3. (See figure 1.)
To the common and segment drivers
Excluding these resistors
Figure 1
No. 5915-4/27
LC75811E, 75811W
• When CL is stopped at the low level
• When CL is stopped at the high level
Figure 2
Block Diagram
No. 5915-5/27
LC75811E, 75811W
Pin Functions
Pin No.
Pin
S1 to S58
LC75811E
1 to 58
Function
Active
I/O
Segment driver outputs.
The S59/COM10 and S60/COM9 pins can be used as common
driver outputs under the “set display technique” instruction.
—
O
OPEN
Common driver outputs.
—
O
OPEN
—
I
GND
—
O
OPEN
H
I
LC75811W
Handling when unused
79, 80
1 to 56
S59/COM10
59
57
S60/COM9
60
58
COM1 to COM8
68 to 61
66 to 59
OSCI
76
74
OSCO
75
73
CE
78
76
CL
79
77
DI
80
78
Oscillator connections. An oscillator circuit is formed by
connecting an external resistor and capacitor at these pins.
Serial data transfer inputs. These pins are connected to the
microcontroller.
CE: Chip enable
CL: Synchronization clock
DI: Transfer data
I
GND
—
I
L
I
GND
RES
77
75
Reset signal input.
• When RES is low (VSS):
• Display off
S1 to S58 = “L” (VSS).
S59/COM10 and S60/COM9 = “L” (VSS).
COM1 to COM8 = “L” (VSS).
• Serial data transfer is disabled.
• The OSCI/OSCO pin oscillator is stopped.
• When RES is high (VDD):
• Display on after a “display on/off control” (display on
state setting) instruction is executed.
• Serial data transfers are enabled.
• The OSCI/OSCO pin oscillator operates.
VLCD1
71
69
Used for applying the LCD drive 3/4 bias voltage externally.
—
I
OPEN
VLCD2
72
70
Used for applying the LCD drive 2/4 bias voltage externally.
—
I
OPEN
VLCD3
73
71
Used for applying the LCD drive 1/4 bias voltage externally.
—
I
OPEN
VDD
69
67
Logic block power supply connection. Provide a voltage of
between 2.7 and 6.0 V.
—
—
—
VLCD
70
68
LCD driver block power supply connection. Provide a voltage of
between 4.5 and 10.0 V.
—
—
—
VSS
74
72
Power supply connection. Connect to ground.
—
—
—
No. 5915-6/27
LC75811E, 75811W
Block Functions
• AC (address counter)
AC is a counter that provides the addresses used for DCRAM and ADRAM.
The address is automatically modified internally, and the LCD display state is retained.
• DCRAM (data control RAM)
DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are
converted to 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of
48 × 8 bits, and can hold 48 characters. The table below lists the correspondence between the 6-bit DCRAM address
loaded into AC and the display position on the LCD panel.
• When the DCRAM address loaded into AC is 00H.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
DCRAM address (hexadecimal)
00
01
02
03
04
05
06
07
08
09
0A
0B
However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
DCRAM address (hexadecimal)
01
02
03
04
05
06
07
08
09
0A
0B
0C
Display digit
DCRAM address (hexadecimal)
1
2
3
4
5
6
7
8
9
10
11
12
2F
00
01
02
03
04
05
06
07
08
09
0A
(Left shift)
(Right shift)
Note:*2. The DCRAM addresses are expressed in hexadecimal.
Least significant bit
Most significant bit
LSB
DCRAM address
DA0
MSB
DA1
DA2
DA3
Hexadecimal
DA4
DA5
Hexadecimal
Example: When the DCRAM address is 2EH.
DA0
DA1
DA2
DA3
DA4
DA5
0
1
1
1
0
1
Note:*3. 5 × 7 dots ... 12-digit display
5 × 8 dots ... 12-digit display
5 × 9 dots ... 12-digit display
5 × 7 dots
4 × 8 dots
3 × 9 dots
No. 5915-7/27
LC75811E, 75811W
• ADRAM (Additional data RAM)
ADRAM is RAM used to store the ADATA display data. ADRAM has a capacity of 12 × 5 bits, and the stored display
data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence between
the 4-bit ADRAM address loaded into AC and the display position on the LCD panel.
• When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 12)
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
ADRAM address (hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
B
However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below.
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
ADRAM address (hexadecimal)
1
2
3
4
5
6
7
8
9
A
B
0
Display digit
1
2
3
4
5
6
7
8
9
10
11
12
ADRAM address (hexadecimal)
B
0
1
2
3
4
5
6
7
8
9
A
(Left shift)
(Right shift)
Note: *4. The ADRAM addresses are expressed in hexadecimal.
Least significant bit
Most significant bit
LSB
ADRAM address
RA0
MSB
RA1
RA2
RA3
Hexadecimal
Example: When the ADRAM address is AH
RA0
RA1
RA2
RA3
0
1
0
1
Note: *5. 5 × 7 dots ... 12-digit display
5 × 8 dots ... 12-digit display
5 × 9 dots ... 12-digit display
5 dots
4 dots
3 dots
• CGROM (Character generator ROM)
CGROM is ROM used to generate the 240 kinds of 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns from the 8-bit
character codes. CGROM has a capacity of 240 × 45 bits. When a character code is written to DCRAM, the character
pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD corresponding to
the DCRAM address loaded into AC.
• CGRAM (Character generator RAM)
CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 × 7, 5 × 8,
or 5 × 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 × 45 bits.
No. 5915-8/27
LC75811E, 75811W
Reset Function
The LC75811E and LC75811W are reset when a low level is applied to the RES pin at power on and, in normal mode.
On a reset the LC75811E and LC75811W create a display with all LCD panels turned off. However, after a reset
applications must set the contents of DCRAM, ADRAM, and CGRAM before turning on display with a “display on/off
control” instruction since the contents of these memories are undefined. That is, applications must execute the following
instructions.
•
•
•
•
•
Set display technique
DCRAM data write
ADRAM data write (If ADRAM is used.)
CGRAM data write (If CGRAM is used.)
Set AC address
After executing the above instructions, applications must turn on the display with a “display on/off control” instruction.
Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off
control” instruction. (See the detailed instruction descriptions.)
Serial Data Transfer Format
• When CL is stopped at the low level
CCB address
8 bits
Instruction data
Up to 64 bits
• When CL is stopped at the high level
CCB address
8 bits
Instruction data
Up to 64 bits
• CCB address: 47H
• D0 to D63: Instruction data
The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When
transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set
of instruction data until the next instruction data transfer is significantly longer than the instruction execution time.
No. 5915-9/27
D41
D42
D43
D44 D45
D46
D47
D48
D49
D50
D51
X
D52
X
D53
X
X
X
X
X
X
X
X
D54
X
X
X
X
X
X
X
X
X
X
0
0
X
X
IM
X
0
0
X
X
0
0
IM
R/L
BU
X
1
1
1
1
0
0
0
1
1
0
0
1
1
0
D59 D60 D61 D62
0
A
M
SC
X
D58
RA0 RA1 RA2 RA3
A
M
DT1 DT2
D55 D56 D57
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
RA0 RA1 RA2 RA3
Notes:*6.The data format differs when the “DCRAM data write” instruction is executed in the increment mode (IM = 1).
(See detailed instruction descriptions .)
*7.The data format differs when the “ADRAM data write” instruction is executed in the increment mode (IM = 1).
(See detailed instruction descriptions.)
*8.The execution times listed here apply when fosc = 300 kHz. The execution times differ when the oscillator frequency fosc differs.
Example: When fosc = 210 kHz
300
27 µs × —— = 39 µs
210
*9.When the power saving mode (BU = 1) is set, the execution time is 27 µs (when fosc = 300 kHz).
X
X
CD41 CD42 CD43 CD44 CD45
X
CGRAM data write
X
AD1 AD2 AD3 AD4 AD5
ADRAM data write *7
DA0 DA1 DA2 DA3 DA4 DA5
DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12
D40
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5
CD1 CD2...CD40
D0 D1...D39
DCRAM data write *6
Set AC address
Display shift
Display on/off control
Set display technique
Instruction
Instruction Table
1
0
1
0
1
0
1
D63
X: don’t care
27 µs
27 µs
27 µs
27 µs
27 µs
0 µs/27 µs *9
0 µs
Execution time *8
LC75811E, 75811W
No. 5915-10/27
LC75811E, 75811W
Detailed Instruction Descriptions
• Set display technique ... <Sets the display technique>
Code
D56
D57
D58
D59
D60
D61
X
X
0
0
DT1 DT2
D62 D63
0
1
X: don’t care
DT1, DT2: Setting the display technique
DT1
DT2
0
0
1
0
Output pins
Display technique
S60/COM9
S59/COM10
1/8 duty, 1/4 bias drive
S60
S59
0
1/9 duty, 1/4 bias drive
COM9
S59
1
1/10 duty, 1/4 bias drive
COM9
COM10
Note: *10. Sn (n = 59, 60): Segment outputs
COMn (n = 9, 10): Common outputs
• Display on/off control ... <Turns the display on or off>
Code
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59 D60
X
X
X
X
M
A
SC
BU
DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12
0
D61
D62
D63
0
1
0
X: don’t care
M, A: Specifies the data to be turned on or off.
M
A
0
0
Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG1 to DG12 data.)
Display operating state
0
1
Only ADATA is turned on (The ADATA of display digits specified by the DG1 to DG12 data are turned on.)
1
0
Only MDATA is turned on (The MDATA of display digits specified by the DG1 to DG12 data are turned on.)
1
1
Both MDATA and ADATA are turned on (The MDATA and ADATA of display digits specified by the DG1 to DG12 data are turned on.)
Note: *11. MDATA, ADATA
5 × 7 dot matrix display
5 × 8 dot matrix display
5 × 9 dot matrix display
DG1 to DG12: Specifies the display digit
Display digit
Display digit data
1
2
3
4
5
6
7
8
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
9
10
11
12
DG9 DG10 DG11 DG12
For example, if DG1 to DG6 are 1, and DG7 to DG12 are 0, then display digits 1 to 6 will be turned on, and display digits 7
to 12 will be turned off (blanked).
No. 5915-11/27
LC75811E, 75811W
SC: Controls the common and segment output pins.
SC
Common and segment output pin states
0
Output of LCD drive waveforms
1
Fixed at the VSS level (all segments off)
Note: *12. When SC is 1, the S1 to S60 and COM1 to COM10 output pins are set to the VSS level, regardless of the M, A, and DG1 to DG12 data.
BU: Controls the normal mode and power saving mode.
BU
Mode
0
Normal mode
1
Power saving mode
(In this mode, the OSCI and OSCO pins oscillator is stopped, and the common and segment pins are set to the VSS level. In this mode,
instructions other than the “display on/off control” instruction cannot be executed. Thus applications must set the LSI to normal mode before
executing any of the other instructions.)
• Display shift ... <Shifts the display>
Code
D56
D57
D58
D59
D60
D61
M
A
R/L
X
0
0
D62 D63
1
1
X: don’t care
M, A: Specifies the data to be shifted
R/L: Shift direction specification
M
A
0
0
Neither MDATA nor ADATA is shifted
Shift operating state
R/L
0
Shift direction
Left shift
0
1
Only ADATA is shifted
1
Right shift
1
0
Only MDATA is shifted
1
1
Both MDATA and ADATA are shifted
• Set AC address... <Specifies the DCRAM and ADRAM address for AC>
Code
D48
D49
D50
D51
D52
D53
D54
D55
X
X
DA0 DA1 DA2 DA3 DA4 DA5
D56
D57
D58
D59
RA0 RA1 RA2 RA3
D60
D61
D62
D63
0
1
0
0
X: don’t care
DA0 to DA5: DCRAM address
DA0
DA1
DA2
DA3
DA4
LSB
Least significant bit
DA5
MSB
Most significant bit
RA0 to RA3: ADRAM address
RA0
RA1
LSB
Least significant bit
RA2
RA3
MSB
Most significant bit
This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC.
No. 5915-12/27
LC75811E, 75811W
• DCRAM data write ... <Specifies the DCRAM address and stores data at that address>
Code
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
X
X
IM
X
X
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5
D59 D60
X
0
D61
D62
D63
1
0
1
X: don’t care
DA0 to DA5: DCRAM address
DA0
DA1
DA2
DA3
DA4
LSB
Least significant bit
DA5
MSB
Most significant bit
AC0 to AC7: DCRAM data (character code)
AC0
AC1
AC2
AC3
AC4
AC5
AC6
LSB
Least significant bit
AC7
MSB
Most significant bit
This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a
5 × 7, 5 × 8, or 5 × 9 dot matrix display data using CGROM or CGRAM.
IM: Setting the method of writing data to DCRAM
IM
DCRAM data write method
0
Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.)
1
Increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.)
Notes: *13.
· DCRAM data write method when IM = 0
CCB address
CCB address
CCB address
CCB address
(1)
(1)
(1)
(1)
24 bits
24 bits
24 bits
24 bits
Instruction
execution time
Instruction
execution time
Instruction
execution time
DCRAM data
write finishes
DCRAM data
write finishes
DCRAM data
write finishes
Instruction
execution time
DCRAM data
write finishes
· DCRAM data write method when IM = 1 (Instructions other than the “DCRAM data write” instruction cannot be
executed.)
CCB address
CCB address
CCB address
CCB address
CCB address
CCB address
(1)
(2)
(2)
(2)
(2)
(3)
24 bits
8 bits
8 bits
8 bits
8 bits
16 bits
Instruction
execution
time
Instruction
execution
time
Instruction
execution time
Instruction
execution
time
Instruction
execution time
DCRAM data
write finishes
DCRAM data
write finishes
DCRAM data
write finishes
DCRAM data
write finishes
Instruction
execution time
DCRAM data
write finishes
DCRAM dat
write finishes
Instructions other than the “DCRAM data write” instruction cannot be executed.
A10721
No. 5915-13/27
LC75811E, 75811W
Data format at (1) (24 bits)
Code
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5
D54
D55
D56
D57
D58
X
X
IM
X
X
D59 D60
X
0
D61
D62
D63
1
0
1
X: don’t care
Data format at (2) (8 bits)
Code
D56
D57
D58
D59
D60
D61
D62 D63
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7
Data format at (3) (16 bits)
Code
D48
D49
D50
D51
D52
D53
D54
D55
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7
D56
D57
D58
D59
D60
D61
D62
D63
0
X
X
X
0
1
0
1
X: don’t care
• ADRAM data write ... <Specifies the ADRAM address and stores data at that address>
Code
D40
D41
D42
D43
D44
AD1 AD2 AD3 AD4 AD5
D45
D46
D47
X
X
X
D48
D49
D50
D51
RA0 RA1 RA2 RA3
D52
D53
D54
D55
D56
D57
D58
X
X
X
X
IM
X
X
D59 D60
X
0
D61
D62
D63
1
1
0
X: don’t care
RA0 to RA3: ADRAM address
RA0
RA1
LSB
Least significant bit
RA2
RA3
MSB
Most significant bit
AD1 to AD5: ADATA display data
In addition to the 5 × 7, 5 × 8, or 5 × 9 dot matrix display data (MDATA), this LSI supports direct display of the five
accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM.
The figure below shows the correspondence between the data and the display. When ADn = 1 (where n is an integer
between 1 and 5) the segment corresponding to that data will be turned on.
ADATA
(m is an integer between
0 and 11)
Corresponding output pin
AD1
S5m + 1 (m is an integer between 0 and 11)
AD2
S5m + 2
AD3
S5m + 3
AD4
S5m + 4
AD5
S5m + 5
No. 5915-14/27
LC75811E, 75811W
IM: Setting the method of writing data to ADRAM
IM
ADRAM data write method
0
Normal ADRAM data write (Specifies the ADRAM address and writes the ADRAM data.)
1
Increment mode ADRAM data write (Increments the ADRAM address by +1 each time data is written to ADRAM.)
Notes: *14.
· ADRAM data write method when IM = 0
CCB address
CCB address
CCB address
CCB address
(4)
(4)
(4)
(4)
24 bits
24 bits
24 bits
24 bits
Instruction
execution time
Instruction
execution time
Instruction
execution time
ADRAM data
write finishes
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
ADRAM data
write finishes
· ADRAM data write method when IM = 1 (Instructions other than the “ADRAM data write” instruction cannot be used.)
CCB address
CCB address
CCB address
CCB address
CCB address
(4)
(5)
(5)
(5)
24 bits
8 bits
8 bits
8 bits
Instruction
execution
time
Instruction
execution
time
Instruction
execution time
ADRAM data
write finishes
ADRAM data
write finishes
Instruction
execution time
ADRAM data
write finishes
CCB address
(5)
(6)
8 bits
16 bits
Instruction
execution
time
Instruction
execution time
ADRAM data
write finishes
ADRAM data
write finishes
ADRAM data
write finishes
Instructions other than the “ADRAM data write” instruction cannot be used.
Data format at (4) (24 bits)
Code
D40
D41
D42
D43
D44
AD1 AD2 AD3 AD4 AD5
D45
D46
D47
X
X
X
D48
D49
D50
D51
RA0 RA1 RA2 RA3
D52
D53
D54
D55
D56
D57
D58
X
X
X
X
IM
X
X
D59 D60
X
0
D61
D62
D63
1
1
0
X: don’t care
Data format at (5) (8 bits)
Code
D56
D57
D58
D59
D60
AD1 AD2 AD3 AD4 AD5
D61
X
D62 D63
X
X
X: don’t care
Data format at (6) (16 bits)
Code
D48
D49
D50
D51
D52
AD1 AD2 AD3 AD4 AD5
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
X
X
X
0
X
X
X
0
1
1
0
X: don’t care
No. 5915-15/27
LC75811E, 75811W
• CGRAM data write ... <Specifies the CGRAM address and stores data at that address>
Code
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
CD32
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
X
X
X
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
X
X
X
X
0
1
1
1
Code
Code
Code
X: don’t care
CA0 to CA7: CGRAM address
CA0
CA1
CA2
CA3
LSB
Least significant bit
CA4
CA5
CA6
CA7
MSB
Most significant bit
CD1 to CD45: CGRAM data (5 × 7, 5 × 8, or 5 × 9 dot matrix display data)
The bit CDn (where n is an integer between 1 and 45) corresponds to the 5 × 7, 5 × 8, or 5 × 9 dot matrix display data.
The figure below shows that correspondence. The dots for which the corresponding data CDn is 1 will be turned on.
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
CD32
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
Note:*15. CD1 to CD35: 5 × 7 dot matrix display data
CD1 to CD40: 5 × 8 dot matrix display data
CD1 to CD45: 5 × 9 dot matrix display data
No. 5915-16/27
LC75811E, 75811W
Notes on the Power On and Power Off Sequences
• At power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on
• At power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
Instruction
execution
Display state
Initial state settings
Display on
Display off
Display on/off control
instruction execution
(Turning the display on)
Display off
Display on/off control
instruction execution
(Turning the display off)
Initial state settings
• t1 ≥ 0
• t2 > 0
• t3 ≥ 0 (t2 > t3)
• tWRES.....1 µs min
• Set display technique
• DCRAM data write
• ADRAM data write (If ADRAM is used.)
• CGRAM data write (If CGRAM is used.)
• Set AC address
Figure 3
No. 5915-17/27
LC75811E, 75811W
1/8 Duty, 1/4 Bias Drive Technique
LCD driver output when all
LCD segments
corresponding to COM1 to
COM8 are turned off
LCD driver output when
only LCD segments
corresponding to COM1
are turned on
LCD driver output when
only LCD segments
corresponding to COM2
are turned on
LCD driver output when all
LCD segments
corresponding to COM1 to
COM8 are turned on
No. 5915-18/27
LC75811E, 75811W
1/9 Duty, 1/4 Bias Drive Technique
LCD driver output when all
LCD segments
corresponding to COM1 to
COM9 are turned off
LCD driver output when
only LCD segments
corresponding to COM1
are turned on
LCD driver output when
only LCD segments
corresponding to COM2
are turned on
LCD driver output when all
LCD segments
corresponding to COM1 to
COM9 are turned on
No. 5915-19/27
LC75811E, 75811W
1/10 Duty, 1/4 Bias Drive Technique
LCD driver output when all
LCD segments
corresponding to COM1 to
COM10 are turned off
LCD driver output when
only LCD segments
corresponding to COM1
are turned on
LCD driver output when
only LCD segments
corresponding to COM2
are turned on
LCD driver output when all
LCD segments
corresponding to COM1 to
COM10 are turned on
No. 5915-20/27
LC75811E, 75811W
Sample Application Circuit 1
1/8 Duty, 1/4 Bias Drive (For use with normal panels)
LCD panel
C ≥ 0.047 µF
From the
microcontroller
A10729
Sample Application Circuit 2
1/8 Duty, 1/4 Bias Drive (For use with large panels)
LCD panel
C ≥ 0.047 µF
10 kΩ ≥ R ≥ 1 kΩ
From the
microcontroller
A10730
No. 5915-21/27
LC75811E, 75811W
Sample Application Circuit 3
1/9 Duty, 1/4 Bias Drive (For use with normal panels)
LCD panel
C ≥ 0.047 µF
From the
microcontroller
Sample Application Circuit 4
1/9 Duty, 1/4 Bias Drive (For use with large panels)
LCD panel
C ≥ 0.047 µF
10 kΩ ≥ R ≥ 1 kΩ
From the
microcontroller
No. 5915-22/27
LC75811E, 75811W
Sample Application Circuit 5
1/10 Duty, 1/4 Bias Drive (For use with normal panels)
LCD panel
C ≥ 0.047 µF
From the
microcontroller
Sample Application Circuit 6
1/10 Duty, 1/4 Bias Drive (For use with large panels)
LCD panel
C ≥ 0.047 µF
10 kΩ ≥ R ≥ 1 kΩ
From the
microcontroller
No. 5915-23/27
LC75811E, 75811W
Sample Correspondence between Instructions and the Display (When the LC75811-8715 is used)
No.
Instruction (hexadecimal)
LSB
MSB
Display
Operation
D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63
Power application
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
The display is in the off state.
Set display technique
2
3
Initializes the IC.
(Initialization with the RES pin.)
0
8
DCRAM data write (increment mode)
0
2
0
0
1
A
DCRAM data write (increment mode)
3
5
DCRAM data write (increment mode)
1
4
DCRAM data write (increment mode)
E
4
DCRAM data write (increment mode)
9
5
DCRAM data write (increment mode)
F
4
DCRAM data write (increment mode)
0
2
DCRAM data write (increment mode)
C
4
DCRAM data write (increment mode)
3
5
DCRAM data write (increment mode)
9
4
DCRAM data write (increment mode)
0
2
DCRAM data write (increment mode)
0
2
DCRAM data write (increment mode)
C
4
DCRAM data write (increment mode)
3
4
DCRAM data write (increment mode)
7
3
DCRAM data write (increment mode)
5
3
DCRAM data write (increment mode)
8
3
DCRAM data write (increment mode)
1
3
DCRAM data write (increment mode)
1
3
0
A
Sets to 1/8 duty 1/4 bias display drive technique
Writes the display data “ ” to DCRAM address 00H
Writes the display data “S” to DCRAM address 01H
Writes the display data “A” to DCRAM address 02H
Writes the display data “N” to DCRAM address 03H
Writes the display data “Y” to DCRAM address 04H
Writes the display data “O” to DCRAM address 05H
Writes the display data “ ” to DCRAM address 06H
Writes the display data “L” to DCRAM address 07H
Writes the display data “S” to DCRAM address 08H
Writes the display data “I” to DCRAM address 09H
Writes the display data “ ” to DCRAM address 0AH
Writes the display data “ ” to DCRAM address 0BH
Writes the display data “L” to DCRAM address 0CH
Writes the display data “C” to DCRAM address 0DH
Writes the display data “7” to DCRAM address 0EH
Writes the display data “5” to DCRAM address 0FH
Writes the display data “8” to DCRAM address 10H
Writes the display data “1” to DCRAM address 11H
Writes the display data “1” to DCRAM address 12H
Continued on next page.
No. 5915-24/27
LC75811E, 75811W
Continued from preceding page.
No.
Instruction (hexadecimal)
LSB
MSB
Display
Operation
D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63
Set AC address
22
23
0
F
F
F
X
1
4
1
C
1
C
1
C
1
C
1
C
1
C
1
C
8
4
1
4
0
2
Display shift
Display shift
26
Display shift
27
Display shift
28
Display shift
29
Display shift
30
33
2
Display shift
25
32
Loads the DCRAM address 00H and the ADRAM
0
address 0H into AC
Display on/off control
24
31
0
S A N Y O
S A N Y O
A N Y O
N Y O
Y O
O
L S I
L S I
L
Shifts the display (MDATA only) to the left
L C
Shifts the display (MDATA only) to the left
L C 7
Shifts the display (MDATA only) to the left
L C 7 5
Shifts the display (MDATA only) to the left
L C 7 5 8
Shifts the display (MDATA only) to the left
L C 7 5 8 1
Shifts the display (MDATA only) to the left
L C 7 5 8 1 1
Shifts the display (MDATA only) to the left
L S I
L S I
L S I
L S I
L S I
L S I
Turns on the LCD for all digits (12 digits) in MDATA
Display on/off control
0
0
F
F
0
X
Display on/off control
F
X
Set AC address
0
0
Set to power saving mode, turns off the LCD for all digits
L S I
L C 7 5 8 1 1
S A N Y O
L S I
Turns on the LCD for all digits (12 digits) in MDATA
Loads the DCRAM address 00H and the ADRAM
address 0H into AC
Note: *16. This example above assumes the use of 12 digits 5 × 7 dot matrix LCD. CGRAM and ADRAM are not used.
X: don’t care
No. 5915-25/27
LC75811-8715 Character Font (Standard)
A10735
LC75811E, 75811W
No. 5915-26/27
LC75811E, 75811W
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of November, 1998. Specifications and information herein are
subject to change without notice.
PS No. 5915-27/27