Ordering number : EN5691 CMOS LSI LC7851E QPSK Demodulation and Audio Signal-Processing IC for Satellite Broadcast Reception Overview The LC7851E demodulates the QPSK (quadrature phase shift keying) modulated audio data broadcast by the Japanese BS and CS broadcast satellites and converts that data to an analog audio signal. This IC integrates on a single chip the audio system signal processing required for BS and CS receivers from QPSK demodulation to analog audio reproduction. The main functions provided by the LC7851E include QPSK demodulation, differential decoding conversion, descrambling, deinterleaving, and error correction. It also generates a PCM audio signal. The PCM audio signal is converted to an analog audio signal by on-chip digital filters and A/D converters. Features • QPSK demodulator, PCM decoder, digital filters, D/A converters, and operational amplifiers integrated on a single chip. • The number of required external components has been reduced and adjustment-free operation achieved in the QPSK demodulator by implementing that block as a digital circuit on a single chip. • CPU interface using an I2C bus • Interface circuits for CORTEC and SkyPort descramblers • Ten to 14 bit expansion of audio data during A mode broadcasts. • Data protection using majority control for the upper bits of the audio data during B mode broadcasts • Full complement of muting functions — Audio suppression provided (bit 16 of the postmajority decision control bits) — Non-audio signal suppression (bits 2 to 5 of the postmajority decision control bits) — Forced muting — Muting when not synchronized — Muting when large numbers of errors are detected (modifiable conditions) — Channel switching — Charged (pay-per-view) program flag muting — Mute detection output provided. • General-purpose ports (2 input ports and 8 output ports) • EIAJ digital audio interface output • 8× oversampling digital filters • Multi-bit D/A converter (with built-in output operational amplifiers) • 5 V single-voltage power supply • QFP (QIP) 64E package Package Dimensions unit: mm Functions • QPSK demodulation • Bit timing clock recovery • Differential decoding conversion and parallel-to-serial conversion • Frame synchronization (forward protection: 8 cycles, back protection: 3 cycles): Frame synchronized/not synchronized detection flag output provided. • Tenth-order M-series descrambling • Deinterleaving • BCH (63, 56) error correction and dual error detection: Single error detected flag output provided. • Support for both interpolation and previous data hold when a dual error is detected. Control bit majority judgment protection every 16 frames • Register data previous value hold when dual errors are detected using BCH(7,3) 3195-QFP64E [LC7851E] SANYO: QIP64E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 83097HA(OT) No. 5691-1/9 Bit timing clock recovery QPSK demodulator Differential conversion parallel-to-serial converter Sync detection and sync protection Scramble interface 1 Control bit extraction Descrambler CPU interface Error detection and correction Deinterleaving General-purpose ports Scramble interface 2 For-fee flag detection Range bit error correction Upper bit majority protection 10 to 14 bits expansion Digital audio interface output Audio switching Data interpolation and previous value hold Audio signal buffer amplifier D/A converter Digital de-emphasis filter 8× oversampling digital filters LC7851E Block Diagram No. 5691-2/9 LC7851E DVSS CVSS DVDD CVDD Pin Assignment VSS VDD PVSS PVDD DVSS VVDD VVSS AVDD AVSS DVDD AVSS Pin Functions Pin No. Pin I/O 1 BSTRI I Bit stream input Function 2 BSTRO O Bit stream output 3 P7 O General-purpose output port 4 P6 O General-purpose output port 5 P5 O General-purpose output port 6 P4 O General-purpose output port 7 P3 O General-purpose output port 8 P2 O General-purpose output port 9 P1 O General-purpose output port 10 P0 O General-purpose output port 11 CK5M O Filter adjustment clock output (5.7272 MHz) 12 DVDD I Digital system power supply 13 TSL I Output control for the state when reset by the PHCNT pin (Low: high-impedance, high: 50% duty pulse output) 14 AVSS I Internal A/D converter ground 15 QPSKI I QPSK modulated signal input 16 AVDD I Internal A/D converter power supply 17 VRM O Internal A/D converter reference (center) output 18 AVSS I Internal A/D converter ground 19 VRB O Internal A/D converter reference (low) output 20 VCADJ 21 VCIN I Internal VCO control input Connection for internal VCO adjustment external resistor Continued on next page. No. 5691-3/9 LC7851E Continued from preceding page. Pin No. Pin I/O 22 VVSS I Internal VCO ground Function 23 VVDD I Internal VCO power supply 24 (N.C) 25 PVDD I Phase comparator power supply 26 PHCNT O Phase comparator output 27 PVSS I Phase comparator ground 28 (N.C) 29 VDD I Oscillator circuit power supply 30 XI1 I Crystal oscillator (22.909088 MHz) input 31 XO1 O Crystal oscillator (22.909088 MHz) output 32 VSS I Oscillator circuit ground 33 DVSS I Digital system ground 34 DADO O Digital audio interface output 35 (N.C) 36 (N.C) 37 (N.C) 38 (N.C) 39 (N.C) 40 TEST1 I Test pin 41 TEST2 I Test pin 42 DVDD I Digital system power supply 43 CVSS I Internal D/A converter ground 44 AOUTL O Left channel audio data output 45 REFL O Internal D/A converter reference voltage: low 46 REFH O Internal D/A converter reference voltage: high 47 AOUTR O Right channel audio data output 48 CVDD I Internal D/A converter power supply 49 RST I Reset input 50 MUTI I Forced muting input 51 MUTO O Mute detection output (When muting detected: high) 52 MOD O Audio mode detection output (A mode: low, B mode: high) 53 LOIN O Frame synchronization detection output (When synchronized: low) 54 ERR O Error detection output (Error detected: high) 55 REQ O Host CPU readout request signal 56 SDA I/O I2C bus data I/O 57 SCL I I2C bus clock input 58 DVSS I Digital system ground 59 DSTRI2 I Data stream input 2/general-purpose I/O port 60 DSTRI1 I Data stream input 1/general-purpose I/O port 61 DSTRO O Data stream output (post-error correction data) 62 DASL I Descrambler interface switching 63 FRM O Frame synchronization signal 64 CK2M O Bit stream clock (2.048 MHz) Caution: All NC pins must be left open. No. 5691-4/9 LC7851E Pin Input and Output Circuit Diagrams • Output pins (Output pins other than P0 to P7, SDA, PHCNT, CK5M, VRM, VRB, REFH, REFL, AOUTR, and AOUTL) • Output pins: P0 to P7 These are n-channel open drain outputs. • Output pin: CK5M • Output pin: PHCNT • Input pins (Input pins other than QPSKI, SCL, SDA, DSTRI1, DSTRI2, and VCIN) • Input pins: SCL, DSTRI1, and DSTRI2 • I/O pin: SDA No. 5691-5/9 LC7851E Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Supply voltage VDD Input voltage VI1 Pins other than SCL and SDA VI2 SCL and SDA Output voltage Ratings VO Allowable power dissipation Pd max Unit –0.3 to +7.0 V –0.3 to VDD+0.3 V –0.3 to +5.3 V –0.3 to VDD +0.3 V Ta = –20 to +75°C 360 mW Operating temperature Topr –20 to +75 °C Storage temperature Tstg –40 to +125 °C Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Ratings min typ Supply voltage VDD 4.5 Input high-level voltage VIH 0.75 VDD Input low-level voltage QPSKI input voltage VIL 5.0 0 VQPSKI 0.7 0.9 Unit max 5.5 V VDD V 0.25 VDD V 1.1 V DC Characteristics at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Current drain Symbol Conditions Ratings min IDD 68 Unit max 98 mA IOH1 VOH = VDD – 0.4 V ; VOH = VDD – 0.4 V, CMOS output pins:PHCNT, LOIN, MOD, DSTRO, FRM, ERR, CK2M, BSTRO, MUTO, DADO, REQ, SYCKO IOH2 VOH = VCK5MH – 25 mV, CK5M IOL1 VOL = 0.4 V ; CMOS output pins: PHCNT, LOIN, MOD, DSTRO, FRM, ERR, CK2M, BSTRO, MUTO, DADO, REQ, SYCKO 1.0 mA IOL2 VOL = 0.4 V, open drain output Pin 1: P0 to P7 1.0 mA IOL3 VOL = 0.4 V, open drain output Pin 2: SDA 4.0 mA VOL = VCK5ML + 25 mV, CK5M 100 IOH = 30 µA, CK5M 236 Output high-level current Output low-level current 1 typ IOL4 1.0 mA –350 –100 µA 350 µA 354 mV 10 µA Output amplitude level VCK5M Input high-level current IIH VI = VDD, Schmitt inputs: TSL, RST, TEST1, TEST2, BSTRI, DSTRI1, DSTRI2, DASL, MUTI, SCL, SDA, P0 to P7 Input low-level current IIL VI = VSS, Schmitt inputs: TSL, RST, TEST1, TEST2, BSTRI, DSTRI1, DSTRI2, DASL, MUTI, SCL, SDA, P0 to P7 –10 µA Output load resistance RL AOUTL and AOUTR 5.0 kΩ 295 D/A Converter Characteristics at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Resolution Total harmonic distortion Symbol Conditions Ratings min typ Unit max RES 1 kHz 0 dB THD1 1 kHz A mode, FS - 18 dB * 0.08 16 % THD2 1 kHz B mode, FS - 18 dB * 0.05 % dB Signal-to-noise ratio S/N 1 kHz 0 dB * 105 Crosstalk C. T 1 kHz 0 dB * 95 Full scale output voltage VFS 2.8 3.0 Bits dB 3.2 Vp-p Note: *Values when measured in the Sanyo evaluation board and with a QPSK modulated signal (1 kHz sine wave) input. No. 5691-6/9 LC7851E I2C Bus Interface at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Symbol Ratings Conditions min typ Unit max SCL frequency fSCL Bus release time TBUF 4.7 µs Start hold time THD STA 4.0 µs SCL low time TLOW 4.7 µs SCL high time THIGH 4.0 µs Data hold time THD DAT 0 ns Data setup time TSU DAT 250 ns 100 Rise time TR 1000 Fall time TF 300 Stop setup time TSU STO 4.0 kHz ns ns µs S: Start condition P: Stop condition Descrambler Interface at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Symbol Ratings Conditions min typ Unit max Clock pulse width TCK2M BSTRO pin output delay time TBSDL 15 DSTRO pin output delay time TDSDL 15 BSTRI and DSTRI1 two-pin input setup time TBSST 244 ns 10 ns ns ns Reset Timing at Power on at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Symbol Reset time TRST Ratings Conditions min TSL pin high; The LC7851E must be used with the TSL pin (pin 13) high. The LC7851E must be reset with the following timing when power is first applied. typ max 200 Unit ms Pin I/O Circuit Pin 30 Pin 31 Recommended Crystal Oscillator Constants Supplier Oscillator element Cin/Cout Citizen Watch Co., Ltd. CSA-309 (22.909088 MHz) 5pF (Cin = Cout) No. 5691-7/9 LC7851E Application Circuit Diagram No. 5691-8/9 LC7851E ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. No. 5691-9/9