LD39300 Ultra low drop BICMOS voltage regulator Feature summary ■ 3A Guaranteed output current ■ Ultra low dropout voltage (200mV typ. @ 3A load, 40mV typ. @600mA load) ■ Very low quiescent current (1.2mA typ. @ 3A load, 1µA max @ 25°C in off mode) ■ Logic-controlled electronic shutdown ■ Current and thermal internal limit ■ ±1.5% Output voltage tolerance @ 25°C ■ Fixed and ADJ output voltages: 1.22V, 1.8V, 2.5V, 3.3V, ADJ. (*see order code) ■ Temperature range: -40 to 125°C ■ Fast dynamic response to line and load changes Description ■ Stable with ceramic capacitor (see paragraph 7.1, 7.2, 7.3) ■ Available in PPAK and DPAK The LD39300 is a fast ultra low drop linear regulator which operates from 2.5V to 6V input supply. A wide range of output options are available. The low drop voltage, low noise, and ultra low quiescent current make it suitable for low voltage microprocessor and memory applications. The device is developed on a BiCMOS process which allows low quiescent current operation independently of output load current. Typical application ■ Microprocessor power supply ■ DSPs power supply ■ Post regulators for switchin suppliers ■ High efficiency linear regulator DPAK PPAK Order codes Part numbers Output voltage DPAK PPAK LD39300DT12-R 1.22V LD39300DT18-R LD39300PT18-R 1.8V LD39300DT25-R LD39300PT25-R 2.5V LD39300DT33-R LD39300PT33-R 3.3V LD39300PT-R ADJ From 1.22 to 5.0V January 2007 Rev. 1 1/17 www.st.com 17 LD39300 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 LD39300 Diagram 1 Diagram Figure 1. Block diagram (*) Not present on ADJ Versions 3/17 Pin configuration LD39300 2 Pin configuration Figure 2. Pin connections (top view for DPAK and PPAK) DPAK PPAK Table 1. Pin description Pln N° Symbol PPAK Note DPAK VSENSE/N.C. For fixed versions: Not Connected on PPAK 5 ADJ For adjustable version: Error Amplifier Input pin for VO from 1.22 to 5.0V 2 1 VI LDO Input Voltage; VI from 2.5V to 6V, CI=1µF must be located at a distance of not more than 0.5’’ from input pin. 4 3 VO LDO Output Voltage pins, with minimum CO=4.7µF needed for stability (also refer to CO vs. ESR stability chart) 1 3 4/17 2 VINH Inhibit Input Voltage: ON MODE when VINH ≥ 2V, OFF MODE when VINH ≤0.3V (Do not leave floating, not internally pulled down/up) GND Common ground LD39300 3 Typical application circuits Typical application circuits (CI and CO Capacitors must be placed as close as possible to the IC pins) Figure 3. 1 Figure 4. LD39300 Fixed version with inhibit Inhibit Pin is not internally pulled down/up then it must not be left floating. Disable the device when connected to GND or to a positive voltage less than 0.3V LD39300 Adjustable version VO = VREF (1 + R1/R2) 2 Set R2 as close as possible to 4.7KΩ. 5/17 Typical application circuits Figure 5. LD39300 DPAK Figure 6. Timing diagram 6/17 LD39300 LD39300 Maximum ratings 4 Maximum ratings Table 2. Absolute maximum ratings Symbol VI VINH VO VADJ Parameter Value Unit -0.3 to 6.5 V INHIBIT Input voltage -0.3 to VI +0.3 (6.5V Max) V DC Output voltage -0.3 to VI +0.3 (6.5V Max) V ADJ Pin voltage -0.3 to VI +0.3 (6.5V Max) V DC Input voltage IO Output current Internally Limited mA PD Power dissipation Internally Limited mW TSTG Storage temperature range -50 to 150 °C TOP Operating junction temperature range -40 to 125 °C Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Table 3. Thermal Data Symbol Parameter RthJA Thermal resistance junction-ambient RthJC Thermal resistance junction-case PPAK DPAK Unit 100 100 °C/W 8 8 °C/W 7/17 Electrical characteristics LD39300 5 Electrical characteristics Table 4. Electrical characteristics (TJ = 25°C, VI = VO+1V, CI = 1µF, CO = 4.7µF, ILOAD = 10mA, VINH = 2V, unless otherwise specified) Symbol VI Parameter Parameter Operating input voltage VI = VO+1V, ILOAD = 10mA to 3A VO Output voltage tolerance VREF Reference voltage ∆VO Output voltage LINE regulation IQ Typ. Max. Unit 2.5 6 V -1.5 1.5 -3 3 % of VO(NOM) 1.22 V VI = VO+1V to 6V 0.04 % VI = VO+1V to 6V, TJ = -40 to 125°C 0.1 ILOAD = 10mA to 3A 0.06 ILOAD = 10mA to 3A, TJ = -40 to 125°C 0.2 0.4 ILOAD = 600mA, TJ=-40 to 125°C 40 80 ILOAD = 3A, TJ = -40 to 125°C 200 400 Quiescent current: ON MODE ILOAD = 10mA to 3A, VINH = 2V TJ = -40 to 125°C 1.2 2.5 Quiescent current: OFF MODE VINH = 0.3V 1 VINH = 0.3V, TJ = -40 to 125°C 5 Output voltage LOAD ∆VO/∆ILOAD regulation VDROP VI = VO+1V to 6V, ILOAD = 10mA to 3A TJ = -40 to 125°C Min. Dropout voltage (VI - VO) 0.2 % %/A mV mA µA Short Circuit Protection Short circuit protection RL = 0 Inhibit threshold LOW Inhibit threshold HIGH VI = 2.5 to 6V OFF TJ = -40 to 125°C TD-OFF Current limit ILOAD = 3A, VO = 3.3V 20 TD-ON Current limit ILOAD = 3A, VO = 3.3V 20 Inhibit input current (1) VI = 6V, VINH = 0 to 6V ±0.1 ISC 6 A Inhibit Input VINH IINH 0.3 V 2 µs ±1 µA AC Parameters SVR eN TSHDN Supply voltage rejection Output noise voltage f = 120Hz 65 f = 1kHz 55 dB BW = 10Hz to 100kHz, CO = 4.7µF, VO = 2.5V 100 Thermal shutdown OFF 170 Hysteresis 10 µVRMS °C 1. Guaranteed by design 8/17 VI = 4.5 ± 1V, VO = 3.3V, ILOAD = 10mA, LD39300 Typical performance characteristics 6 Typical performance characteristics Figure 7. (TJ = 25°C, VI = VO+1V, CI = 1µF, CO = 4.7µF, ILOAD = 10mA, VINH = VI, unless otherwise specified) Output voltage vs temperature Figure 8. Dropout voltage vs temperature Figure 9. Dropout voltage vs output current Figure 11. Quiescent current vs temperature Figure 10. Quiescent current vs temperature Figure 12. Short circuit current vs temperature 9/17 Typical performance characteristics LD39300 Figure 13. Output voltage vs input voltage Figure 14. Stability region vs CO & ESR Figure 15. Stability region vs CO & ESR (low ESR zoom area) Figure 16. Load transient (fall time) VI = 5V, VO = 3.3V, IO = 10mA to 3A, CI = 1µF, CO = 4.7µF Figure 17. Load transient (rise time) Figure 18. Line transient VI = 5V, VO = 3.3V, IO = 10mA to 3A, CI = 1µF, CO = 4.7µF VI = 3.5V to 5.5V, VO = 3.3V, ILOAD = 10mA, CO = 4.7µF 10/17 LD39300 Application notes 7 Application notes 7.1 External capacitors The LD39300 requires external capacitors for regulator stability. These capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance (see Figure 14. Figure 15.). The input/output capacitors must be located less than 1cm from the relative pins and connected directly to the input/output ground pins using traces which have no other currents flowing through them. Any good quality of Ceramic or Electrolytic capacitors can be used. 7.2 Input capacitor An input capacitor whose minimum value is 1µF is required with the LD39300 (amount of capacitance can be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin of the device and returned to a clean analog ground. Any good quality ceramic, tantalum or film capacitors can be used for this capacitor. 7.3 Output capacitor It is possible to use Ceramic or Tantalum capacitors but the output capacitor must meet the requirement for minimum amount of capacitance and E.S.R. (equivalent series resistance) value. A minimum capacitance of 4.7µF is a good choice to guarantee the stability of the regulator. Anyway, other CO values can be used according to the (Figure 14. Figure 15.) showing the allowable ESR range as a function of the output capacitance. This curve represents the stability region over the full temperature and IO range. 7.4 Thermal note The output capacitor must maintain its ESR in the stable region over the full operating temperature range to assure stability. Also, capacitors tolerance and variation with temperature must be kept in consideration in order to assure the minimum amount of capacitance at all times. 7.5 Inhibit input operation The inhibit pin can be used to turn OFF the regulator when pulled down, so drastically reducing the current consumption down to less than 1µA. When the inhibit feature is not used, this pin must be tied to VI to keep the regulator output ON at all times. To assure proper operation, the signal source used to drive the inhibit pin must be able to swing above and below the specified thresholds listed in the electrical characteristics section (VIH VIL). The inhibit pin must not be left floating because it is not internally pulled down/up. 11/17 Package mechanical data 8 LD39300 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 12/17 LD39300 Package mechanical data PPAK MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.4 0.6 0.015 0.023 B2 5.2 5.4 0.204 0.212 0.023 C 0.45 0.6 0.017 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 6.6 0.252 D1 E 5.1 6.4 0.201 0.260 E1 4.7 0.185 e 1.27 0.050 G 4.9 G1 2.38 2.7 0.093 0.106 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.6 L5 1 L6 5.25 1 1 2.8 0.193 0.206 0.031 0.023 0.039 0.039 0.039 0.110 0078180-E 13/17 Package mechanical data LD39300 DPAK MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 b4 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 6.6 0.252 D1 E 5.1 6.4 E1 0.200 4.7 e 0.260 0.185 2.28 0.090 e1 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L 1 0.039 (L1) 2.8 0.110 L2 0.8 0.031 L4 0.6 1 0.023 0.039 0068772-F 14/17 LD39300 Package mechanical data Tape & Reel DPAK-PPAK MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 330 13.0 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 MAX. 0.504 0.512 22.4 0.519 0.882 Ao 6.80 6.90 7.00 0.268 0.272 0.2.76 Bo 10.40 10.50 10.60 0.409 0.413 0.417 Ko 2.55 2.65 2.75 0.100 0.104 0.105 Po 3.9 4.0 4.1 0.153 0.157 0.161 P 7.9 8.0 8.1 0.311 0.315 0.319 15/17 Revision history LD39300 9 Revision history Table 5. Revision history Date Revision 26-Jan-2007 1 16/17 Changes Initial release. LD39300 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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