Ordering number : ENA1432 CMOS IC LE25FW418A 4M-bit (512K×8) Serial Flash Memory with High-Density Read Mode Overview The LE25FW418A is 512K×8bit Serial flash memory by 3.0V single power supply operation, and support serial peripheral interface (S.P.I.). There are three kinds of erase functions, Small Sector (4K bytes) erase, Sector (64K bytes) erase and Chip erase. Page program can program the arbitrary data from 1 byte to 256 byte. Program time is high speed, 1.5ms (Typ.). Moreover, The LE25FW418A makes the best use of the feature of the serial flash memory, and is stored in 8pin very small package. The LE25FW418A is best suited for applications that require re-programmable nonvolatile storage of program memory. LE25FW418A has also the High-Density read mode (hereafter, HD_READ mode) that is the most high-speed data transfer in the world as the flash memory with serial interface. About eight times the data-transfer velocity can be achieved without changing the clock frequency used in a usual serial flash memory by using this mode. For instance, it is possible to read with 400Mbit/s in the maximum by using the HD_READ mode of 50MHz though a standard serial flash memory read with 50Mbit/s or less. Features • Read/write operations enabled by single 3.0V power supply: 2.7 to 3.6V supply voltage range • Operating frequency : 50MHz • Temperature range : 0 to +70°C,-40 to 85°C(Planning) Continued on next page. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 61709 SY 20090428-S00004 No.A1432-1/27 LE25FW418A Continued from preceding page. • Serial interface : SPI mode 0, mode 3 supported • Sector size : 4K bytes/small sector, 64K bytes/sector • Small sector erase, sector erase, chip erase functions • Page program function (256 bytes/page) • High-Density read mode (HD_READ) • Block protect function • Highly reliable read/write Number of rewrite times : 100,000 times Small sector erase time : 25ms (typ.), 0.1s (max.) Sector erase time : 25ms (typ.), 0.5s (max.) Chip erase time : 250ms (typ.), 5s (max.) Page program time : 1.5ms/256 bytes (typ.), 2.5ms/256 bytes (max.) • Status functions Ready/busy information, protect information • Data retention period : 20 years • Package : LE25FW418ATT MSOP8 (225mil) Package Dimensions unit:mm (typ) 3276 5.2 5 0.5 4.4 6.3 8 4 0.35 0.125 0.08 (0.65) 1.27 0.85max 1 (0.7) SANYO : MSOP8(225mil) Figure 1 Pin Assignments CS 1 8 VDD SO (SIO3) 2 7 HOLD (SIO1) WP (SIO2) 3 6 SCK VSS 4 5 SI (SIO0) Top view No.A1432-2/27 LE25FW418A Figure 2 Block Diagram 4M Bit Flash EEPROM Cell Array XDECODER ADDRESS BUFFERS & LATCHES Y-DECODER I/O BUFFERS & DATA LATCHES CONTROL LOGIC SERIAL INTERFACE CS SCK SO SI WP (SIO0) (SIO3) (SIO2) HOLD (SIO1) Table 1 Pin Description Symbol *( ) HD_READ mode Pin Name Description Serial clock This pin controls the data input/output timing. SI Serial data input To input data or addresses serially from MSB to LSB (Least Significant Bit). (SIO0) (Serial data I/O0) (To input data or addresses and to output data serially in the HD_READ mode) SO Serial data output To output data serially from MSB to LSB. (SIO3) (Serial data I/O3) (To input data or addresses and to output data serially in the HD_READ mode) SCK CS Chip select The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. WP Write-protect To write-protect the block protect bits (BP0, BP1, BP2) and the status register write protect bit (SRWP) of the status register in co-operation with the status register write protect bit (SRWP). (SIO2) (Serial data I/O2) HOLD Hold To pause any serial communications with the device without deselecting the device. (SIO1) (Serial data I/O1) (To input data or addresses and to output data serially in the HD_READ mode) VDD Power supply This pin supplies the 2.7 to 3.6V supply voltage. VSS Ground This pin supplies the 0V supply voltage. (To input data or addresses and to output data serially in the HD_READ mode) No.A1432-3/27 LE25FW418A Table 2 Command Settings Command Read 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 03h A23-A16 A15-A8 A7-A0 0Bh A23-A16 A15-A8 A7-A0 Set HD_READ mode D4h MD *1 Small sector erase D7h A23-A16 A15-A8 A7-A0 Sector erase D8h A23-A16 A15-A8 A7-A0 Chip erase C7h Page program 02h A23-A16 A15-A8 A7-A0 Write enable 06h Write disable 04h Power down B9h Status register read 05h Status register write 01h X A7-A0 Read silicon ID 1 *2 9Fh Read silicon ID 2 *4 ABh Exit power down mode ABh 5th bus cycle 6th bus cycle Nth bus cycle PD *2 PD *2 X PD *2 DATA X Explanatory notes for Table 2 "X" signifies "don't care" (that is to say, any value may be input). The "h" following each code indicates that the number given is in hexadecimal notation. Addresses A23 to A19 for all commands are "Don't care". In order for commands other than the read command to be recognized, CS must rise after all the bus cycle input. *1. MD: mode register data. Various operation methods of the HD_READ mode such as the operation frequencies and the clock latency. Please refer to Table 3 for details. *2: "PD" stands for page program data. Any amount of data from 1 to 256 bytes in 1-byte unit is input. *3: Of the two silicon ID commands, it is for the command with the 9Fh setting that the manufacturer code 62h is first output. For as long as the clock input is continued, 10h of the device code is output continuously, followed by the repeated output of 62h and 10h. *4: Read ID2 (ABh) A23 to A1 are don't care. A read cycle from address A0=‘0’ outputs the manufacture code (SANYO: 62h). A read cycle at address A0=‘1’ outputs the device code (10h). No.A1432-4/27 LE25FW418A Device Operation The LE25FW418A features electrical on-chip erase functions using a single 3.0V power supply, that have been added to the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are facilitated by incorporating the command registers inside the chip. The read, erase, program and other required functions of the device are executed through the command registers. The command addresses and data input in accordance with "Table 2 Command Settings" are latched inside the device in order to execute the required operations. "Figure 3 Serial Input Timing" shows the timing waveforms of the serial data input. First, at the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are introduced internally in sequence starting with bit 7 in synchronization with the rising SCK edge. At this time, output pin SO is in the high-impedance state. The output pin is placed in the low-impedance state when the data is output in sequence starting with bit 7 synchronized to the falling clock edge during read, status register read and silicon ID. Refer to "Figure 4 Serial Output Timing" for the serial output timing. The LE25FW418A supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. Figure 3 Serial Input Timing tCPH CS tCLS tCLHI tCSS tCLLO tCSH tCLH SCK tDS SI SO tDH DATA VALID High Impedance High Impedance Figure 4 Serial Output Timing CS SCK tCLZ SO tHO tCHZ DATA VALID tV SI No.A1432-5/27 LE25FW418A Outline of High-Density read mode (HD_READ mode) operation LE25FW418A has the HD_READ mode in addition to two kinds of normal read (4 bus read and 5 bus read). The HD_READ mode is greatly different from the normal mode in three points. The first is the difference of the role of pins. Four pins (SO, WP, HOLD, SI) become I/O pins (SIO3 to SIO0) in the HD_READ mode while the input pin (SI) and the output pin (SO) are only one in the normal mode respectively as shown in Figure 2. Because SO, WP, HOLD and SI operate as I/O pin in the HD_READ mode, the setting of read address and the outputting read data become to be done from four pins. The second is the difference of the relation between the clock and the data output. The rising edge of SCK is made a trigger for the address input and the falling edge of SCK is made a trigger for the data output in the normal mode. However, both edges of rising and falling of SCK will be done to the address taking and the data outputting in the HD_READ mode. The third is the difference of the data composition at the time of reading. It is read by the ×16 bit in the HD_READ mode though it is read by the ×8 bit in the normal read. Therefore, please fix least significant bit (LSB) : A0 to L in the address input in HD_READ mode. Pin Assignments Entry CS 1 8 VDD SO 2 7 WP 3 VSS 4 Normal mode CS 1 8 VDD HOLD SIO3 2 7 SIO1 6 SCK SIO2 3 6 SCK 5 SI VSS 4 5 SIO0 Slipping out HD_READ mode Top view Top view Figure 5: Serial input / output timing diagram for HD_READ mode (CL=1.0) tCSS tCLHI tCLLO tV2 tCLZ CS tHO tAS tAH tAS tAH tAS tAH SCK SIO3 “0” A3 data data SIO2 A22 A2 data data SIO1 A21 A1 data data SIO0 A20 “0” data data No.A1432-6/27 LE25FW418A Command Definition "Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions and operations corresponding to each command is presented below. 1. Conventional Read There are two read commands, the 4 bus cycle read command and 5 bus cycle read command. Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following (03h), and the data in the designated addresses is output synchronized to SCK. The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 6-a 4 Bus Read" shows the timing waveforms. Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference. "Figure 6-b 5 Bus Read" shows the timing waveforms. The only difference between these two commands is whether the dummy bits in the fifth bus cycle are input. When SCK is input continuously after the read command has been input and the data in the designated addresses has been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address (7FFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO is in a high-impedance state. Figure 6-a 4 Bus Read CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 31 32 23 24 39 40 47 Mode0 8CLK SI Add 03h Add Add N High Impedance SO DATA MSB N+1 N+2 DATA DATA MSB MSB Figure 6-b 5 Bus Read CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 Mode0 8CLK SI SO 0Bh Add High Impedance Add Add X N N+1 N+2 DATA DATA DATA MSB MSB MSB No.A1432-7/27 LE25FW418A 2. High-Density Read LE25FW418A has the HD_READ mode in addition to two kinds of normal read (4 bus read and 5 bus read). The HD_READ mode is greatly different from the normal mode in three points. The first is the difference of the role of pins. Four pins (SO, WP, HOLD, SI) become I/O pins (SIO3 – SIO0) in the HD_READ mode while the input pin (SI) and the output pin (SO) are only one in the normal mode respectively as shown in Figure 2. Because SO, WP, HOLD and SI operate as I/O pin in the HD_READ mode, the setting of read address and the outputting read data become to be done from four pins. The second is the difference of the relation between the clock and the data output. The rising edge of SCK is made a trigger for the address input and the falling edge of SCK is made a trigger for the data output in the normal mode. However, both edges of rising and falling of SCK will be done to the address taking and the data outputting in the HD_READ mode. The third is the difference of the data composition at the time of reading. It is read by the ×16 bit in the HD_READ mode though it is read by the ×8 bit in the normal read. Therefore, please fix least significant bit (LSB): A0 to L in the address input in HD_READ mode. When the HD_READ mode is used with LE25FW418A, it is necessary to input the HD_READ mode command first according to the usual serial input specification. Please refer to Table 1 for the command input to set of the HD_READ mode. The command is composed at two bus cycles, and various operation methods of the HD_READ mode can be set at the second bus cycle. Please refer to Table 2 for a set content. Please refer to Figure 7 for the input waveform when the HD_READ mode is set. The HD_READ mode becomes effective by making CS to H after the command is input. It keeps maintaining the HD_READ mode until the power supply is cut or the above-mentioned release command is input after entering the HD_READ mode once. Figure 7: HD_READ mode setting waveform (CL=1.0) CL=0.5 CS CL=0 SCK CL=1.0 Mode0 A23-A0 = N SIO3(SO) N High Impedance A23 A19 A15 A11 N+1 A7 A3 D15 D11 D7 D3 D15 “0” SIO2(WP) A22 A18 A14 A10 A6 A2 D14 D10 D6 D2 D14 SIO1(HOLD) A21 A17 A13 A9 A5 A1 D13 D9 D5 D1 D13 A20 A16 A12 A8 A4 A0 D12 D8 D4 D0 D12 16CLK SIO0(SI) D4h Register Setting Normal mode “0” HD_READ mode Because the HD_READ mode entry is an input in the normal mode, either input of SPI mode 0/3 is possible. However, there is no concept of SPI mode for the period when the HD_READ mode is set. Please control CS according to timing that provides with this specifications. No.A1432-8/27 LE25FW418A The composition of one input pin and one output pin changes into the composition of four I/O pins if it enters in the HD_READ mode. Therefore, the start address of reading in HD_READ mode is set from four I/O pins (SIO0 - SIO3). At this time, the address from A23 to A0 are latched internally by rising edge of CS, rising and falling edge of SCK. Please refer to Figure 7. However, it is necessary to note the following points. • Even if CS is fixed at H, four I/O pins become the input waiting states in the HD_READ mode. Therefore, please fix the state of four I/O pins at H or L for this period as much as possible. The input level changes or it becomes middle potential, the penetration current will flow in the pin input buffer inside the flash. • The address that can be input is only an even number address because output data is read in each x16 bit in the HD_READ mode. • Please input L to most significant bit (A23) of the address. • The input address from A22 to A20 is don’t care. Those are for the serial flash memory that exceeds 8Mbit (planning). Please rise CS to H in arbitrary timing when you want to stop reading in the HD_READ mode temporarily. The level of SCK at this time doesn't ask H or L. The output is be the state of Hi-Z after tCHZ by rising CS, and four I/O pins (SIO0 - SIO3) become the input waiting states. Therefore, please fix the state of four I/O pins for this period at H level or L level. Afterwards, please execute it from the address input again when you restart reading. Address A23-A0 is set to xx55AAh to release from the HD_READ mode to the normal mode, and then the operation that makes CS to H immediately when SCK becomes L after the address input is done. Please refer to Figure 8. Figure 8: HD_READ mode release waveform tCPH tCSH tCPH CS SCK Data output A23-0=xx55AAh SIO3(SO) “0” A19 A15 A11 A7 A3 SIO2(WP) A22 A18 A14 A10 A6 A2 SIO1(HOLD) A21 A17 A13 A9 A5 A1 SIO0(SI) A20 A16 A12 A8 A4 “0” HD_READ mode Normal mode No.A1432-9/27 LE25FW418A 3. HD_READ Mode Register Setting Various operation methods of the HD_READ mode can be set to an internal register in the HD_READ mode command input at the second bus cycle. The register are eight bits in all, and shows the meaning of each bit in the table 3: HD_READ mode register table. This register setting is effective until the release from HD_READ mode to the normal mode. It is not necessary to set it again at each temporary stop of reading in the HD_READ mode. Table 3: HD_READ Mode Register Table MSB REGBL2 BIT LSB REGBL1 Name 7 REGBL2 6 REGBL1 5 REGBL0 4 REGFCLK1 3 REGFCLK0 2 REGCL2 1 REGCL1 0 REGCL0 REGBL0 REGFCLK1 REGFCLK0 REGCL2 Function REGCL1 REGCL0 Set value : Set content [0, 0, 0]: continuous Burst length [REGBL2, REGBL1, REGBL0] [1, 0, 0]: 4words wrap around [1, 0, 1]: 8 words wrap around [1, 1, 0]: 16 words wrap around [1, 1, 1]: 32 words wrap around [0, 0]: 16MHz or less + power save mode Clock frequency [0, 1]: 25MHz or less [REGFCLK1, REGFCLK0] [1, 0]: 50MHz or less [1, 1]: 51MHz or more (1) [0, 0, 0]: Clock latency = 0.5 (2) [0, 0, 1]: Clock latency = 1.0 Clock latency [0, 1, 0]: Clock latency = 1.5 [REGCL2, REGCL1, REGCL0] [0, 1, 1]: Clock latency = 2.0 [1, 0, 0]: Clock latency = 2.5 [1, 0, 1]: Clock latency = 3.0 (1) The specification that exceeds fCLK=50MHz is planning. (2) When fCLK exceeds 30MHz, it is necessary to adjust the CL to 1.0 or more. •Burst length setting In this model, two kinds of reading methods of "Continuous reading" and "Wrap around reading" in the HD_READ mode can be set alternately. And, the delimitation of the address can be set to four kinds (every 4 words, 8 words, 16 words, and 32 words (one word =16 bits)) in "Wrap around reading". • Continuous reading When the burst length is set, the Continuous reading is set by specifying (0, 0, 0) the register bit. The Continuous reading method automatically continues to read as long as the SCK is input. Reading is begun from the input address, and an internal address is automatically count up by two addresses (every 16 bits). If the internal address reaches to the final address (7FFFEh), it returns to the first address (00000h) and reading is continued. If it wants to shift to an arbitrary address on the way, the operation that makes CS to H once and makes to L again is done. No.A1432-10/27 LE25FW418A • Wrap around reading When the burst length is set, the wrap around reading method is set by specifying (1, X, X) the register bit. The wrap around reading method automatically continues to read as long as the SCK is input. Reading is begun from the input address, and an internal address is automatically count up by two addresses (every 16 bits). If the internal address reaches to the delimitation of the address set beforehand, it returns to the head of the delimitation of the address and reading is repeated. The delimitation of the address can be set to four kinds (every 4 words, 8 words, 16 words and 32 words (one word =16 bits)) by two subordinate position bits of the register bit. For instance, 16 words becomes a unit of the address delimitation for reading by 16 word wrap around. After it reaches the final word of the address delimitation by 16 words, it returns to the first word and reading is done even if reading is started from which address. The order of reading for 20 words when the address of the third word from the head is read as a start address is as follows. The order of reading address The order of reading address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 17 18 19 20 0011 0100 0101 0110 ＊Mark address is A4 to A1 Clock frequency setting In this model, it is necessary to set the register bit of the clock frequency according to the operation frequency used .The clock of 50MHz or less can be input at present. Especially, the power saving mode that decreases the power consumption at HD_READ can be selected by specifying (0, 0) the register bit. However, this power saving mode use with operation frequency 16MHz or less. Moreover, spec (tV2) of the output data time from SCK changes in this case. Clock latency setting In this model, CL (= clock latency: number of clocks from the setting of the address to the output of the first data) can be set by setting the clock latency register bit. Please refer to Figure 7 for the method of counting CL. The falling edge of the first SCK after the address input is assumed to be CL=0, and 0.5 CL is added every half clock of SCK. CL can be set within the range from 0.5 to 3.0. However, when the clock frequency exceeds 30MHz, it is necessary to set CL to 1.0 or more. No.A1432-11/27 LE25FW418A 4. Status Register The Status Register's contents are shown in Table 4. The Status Register can perform detection state of a device and setup of protection. Table 4 Status Registers Bit Name Bit0 RDY Bit1 Bit2 Logic WEN Function Power-on Time Information 0 Ready 1 Erase/Program 0 Write disabled 1 Write enabled 0 0 BP0 0 Nonvolatile information 1 Bit3 Bit4 BP1 0 Block protect information 1 See status register descriptions on BP0, BP1, and BP2. 0 BP2 Nonvolatile information Nonvolatile information 1 Bit5 Reserved bits 0 Bit6 Reserved bits 0 Bit7 SRWP 0 Status register write enabled 1 Status register write disabled Nonvolatile information 4-1. Status Register Read The contents of the status registers can be read using the status register read command. This command can be executed even during the following operations. • Small sector erase, sector erase, chip erase • Page program • Status register write "Figure 9 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The data can be read by the status register read command at any time (even during a program or erase cycle). Figure 9 Status Register Read CS Mode 3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 Mode 0 8CLK SI SO 05h High Impedance DATA MSB DATA MSB DATA MSB No.A1432-12/27 LE25FW418A 4-2. Status Register Write By Status Register Write, BP0, BP1, BP2 and SRWP can be rewritten. RDY, WEN, Bit5, and Bit6 are read-only, BP0, BP1, BP2 and SRWP are non-volatile. A timing waveform is shown in Figure 10 and a flow chart is shown in Figure 23. Status Register Write command consists of the 1st bus cycle and the 2nd bus cycle, and internal Write operation starts with the rising edge of CS after inputting data after OP-code (01h). Erase and program are automatically performed inside the device and a Status Register Write rewrites BP0, BP1, BP2 and SRWP non-volatilized data. The write-in data to read-only bits (RDY, WEN, Bit 5, Bit 6) are don't care. The end of a Status Register Write is detectable with RDY of a Status Register Read. The number of times of rewriting of a Status Register Write is 1,000 times (min). In order to perform a Status Register Write, it is necessary to change WEN of a Status Register into "1" state for WP pin. Figure 10 Status Register Write Self-timed Write Cycle tSRW CS tWPS tWPH WP Mode3 SCK 0 1 2 3 4 5 6 7 8 15 Mode0 8CLK SI SO 01h DATA High Impedance 4-3. Contents of Each Status Register RDY (bit 0) The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is in a busy state, and when it is "0", it means that write is completed. No.A1432-13/27 LE25FW418A WEN (bit 1) The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations in any area that is not block-protected. WEN can be controlled using the write enable and write disable commands. By inputting the write enable command (06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following states, WEN is automatically set to "0" in order to protect against unintentional writing. • At power-on • Upon completion of small sector erase, sector erase or chip erase • Upon completion of page program • Upon completion of status register write * If a write operation has not been performed inside the LE25FW418A because, for instance, the command input for any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation. BP0, BP1, BP2 (bits 2, 3, 4) Block protect BP0, BP1, and BP2 are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to "Table 5 Protect level setting conditions". Table 5 Protect Level Setting Conditions Status Register Bits Protect Level Protected Area BP2 BP1 BP0 0 (Whole area unprotected) 0 0 0 None 1 (1/8 protected) 0 0 1 70000h to 7FFFFh 2 (1/4 protected) 0 1 0 60000h to 7FFFFh 3 (1/2 protected) 0 1 1 40000h to 7FFFFh 4 (Whole area protected) 1 0 0 00000h to 7FFFFh 4 (Whole area protected) 1 0 1 00000h to 7FFFFh 4 (Whole area protected) 1 1 0 00000h to 7FFFFh 4 (Whole area protected) 1 1 1 00000h to 7FFFFh * Chip erase is enabled only when the protect level is 0. SRWP (bit 7) Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status registers BP0, BP1, BP2, and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5 SRWP setting conditions". Table 6 SRWP Setting Conditions WP Pin 0 1 SRWP Status Register Protect State 0 Unprotected 1 Protected 0 Unprotected 1 Unprotected Bits 5 and 6 are reserved bits, and have no significance. No.A1432-14/27 LE25FW418A 5. Write Enable Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command. "Figure 11 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). • Small sector erase, sector erase, chip erase • Page program • Status register write 6. Write Disable The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 12 Write Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command (06h). Figure 11 Write Enable CS CS Mode3 SCK Figure 12 Write Disable Mode3 0 1 2 3 4 5 6 7 SCK Mode0 8CLK SI 06h High Impedance SO 0 1 2 3 4 5 6 7 Mode0 8CLK SI 04h High Impedance SO 7. Power-down The power-down command sets all the commands, with the exception of the silicon ID read command and the command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 13 Power-down" shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the silicon ID read command (ABh) has been input). "Figure 14 Exiting from Power-down" shows the timing waveforms of the power-down exit command. Figure 13 Power-down CS Figure 14 Exiting from Power-down CS tPRB Mode3 SCK Mode3 0 1 2 3 4 5 6 7 SCK Mode0 8CLK SI SO B9h High Impedance 0 1 2 3 4 5 6 7 Mode0 8CLK SI SO ABh High Impedance No.A1432-15/27 LE25FW418A 8. Small Sector Erase Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of 4Kbytes. "Figure 15 Small Sector Erase" shows the timing waveforms, and Figure 24 shows a small sector erase flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D7h). Addresses A18 to A12 are valid, and Addresses A23 to A19 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 15 Small Sector Erase Self-timed Erase Cycle tSSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI D7h Add Add X High Impedance SO 9. Sector Erase Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure 16 Sector Erase" shows the timing waveforms, and Figure 24 shows a sector erase flowchart. The sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h). Addresses A18 to A16 are valid, and Addresses A23 to A19 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 16 Sector Erase Self-timed Erase Cycle tSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI SO D8h Add Add X High Impedance No.A1432-16/27 LE25FW418A 10. Chip Erase Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 17 Chip Erase" shows the timing waveforms, and Figure 24 shows a chip erase flowchart. The chip erase command consists only of the first bus cycle, and it is initiated by inputting (C7h). After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 17 Chip Erase Self-timed Erase Cycle tCHE CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI C7h High Impedance SO 11. Page Program Page Program can program the arbitrary numbers of bytes of 1 to 256 bytes into the sector erased in advance. Figure 18 shows timing waveform and a flow chart is shown in Figure 25. 24-bit address is inputted after OP-code (02H). As for an address A18-A0 are effective. Then, loading is possible for program data during CS is low. When the data loaded exceeds 256 bytes, 256 bytes loaded at the end are programmed. It is necessary to load program data per byte, and when it programs by loading the data below a byte unit, a normal Page Program is not performed. Figure 18 Page Program Self-timed Program Cycle tPP CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 2079 Mode0 8CLK SI SO 02h Add Add Add PD PD PD High Impedance No.A1432-17/27 LE25FW418A 12. Silicon ID Read Silicon ID read is an operation that reads the manufacturer code and device code information. "Table 7 Silicon ID codes table" lists the silicon ID codes. The silicon ID read command is not accepted during writing. Two methods are used for silicon ID reading. The first method involves inputting the 9Fh command: the setting is completed with only the first bus cycle input, and in subsequent bus cycles the manufacturer code 62h and device code 10h are repeatedly output in succession so long as the clock input is continued. Refer to "Figure 19-a Silicon ID read 1" for the waveforms. The second method involves inputting the ABh command. This command consists of the first through fourth bus cycles, and the silicon ID can be read when 16 dummy bits and an 8-bit address are input after (ABh). When address A0 is "0", the manufacturer code 62h is read in the fifth bus cycle, and the device code 10h is read in the sixth bus cycle. "Figure 19-b Silicon ID read 2" shows the timing waveforms. If, after the manufacturer code or device code has been read, the SCK input is continued, the manufacturer code and device code are output alternately with each bus cycle. When address A0 is "1", reading starts with device code 10h in the fifth bus cycle. Table 7 Silicon ID Codes Address Output Code A0 Manufacturer code 0 62h Device code 1 10h The data is output starting with the falling clock edge of the fourth bus cycle bit 0, and silicon ID reading ends at the rising CS edge. Figure 19-a Silicon ID Read 1 CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 Mode0 8CLK SI 9Fh High Impedance SO N N+1 N SiID SiID SiID MSB MSB MSB Figure 19-b Silicon ID Read 2 CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 Mode0 8CLK SI ABh X X Add N SO High Impedance SiID MSB N+1 SiID MSB N SiID MSB No.A1432-18/27 LE25FW418A 13. Hold Function Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 21 HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state, and SI and SCK are "don't care". Figure 21 HOLD Active CS Active HOLD tHS tHS SCK tHH tHH HOLD tHHZ tHLZ High Impedance SO 14. Power-on Please make CS to high to prevent a careless writing when you turn on the power supply. Please begin the command input of the read operation after 100μs (tPU_READ) from the state to which the powersupply voltage is 2.7V or more steady. Please begin the command input of the program or erase operation after 10ms (tPU_WRITE) from the state to which the power-supply voltage is 2.7V or more steady. Figure 21 Power-on Timing Program, Erase and Write Command not Allowed Full Access Allowed VDD Chip selection not Allowed Read Access Allowed VDD(max) VDD(min) tPU_READ tPU_WRITE 0V No.A1432-19/27 LE25FW418A 15. Hardware Data Protection In order to protect against unintentional writing at power-on, the LE25FW418A incorporates a power-on reset function. The following conditions must be met in order to ensure that the power reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. Figure 22 Power-down Timing Program, Erase and Write Command not Allowed VDD VDD(max) No Device Access Allowed VDD(min) tPU_READ tPU_WRITE tPD 0V vBOT 16. Software Data Protection The LE25FW418A eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. • When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK) • When the page program data is not in 1-byte increments • When the status register write command is input for 2 bus cycles or more 17. Decoupling Capacitor A 0.1μF ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure that the device will operate stably. No.A1432-20/27 LE25FW418A Specifications Absolute Maximum Ratings Parameter Symbol Maximum supply voltage DC voltage (all pins) Storage temperature Conditions Ratings unit With respect to VSS -0.5 to +4.6 With respect to VSS -0.5 to VDD+0.5 V -55 to +150 °C Tstg V Operating Conditions Parameter Symbol Conditions Ratings unit Operating supply voltage 2.7 to 3.6 V 0 to +70 °C -40 to +85(Planning) °C Operating ambient temperature Allowable DC Operating Conditions Parameter Symbol Ratings Conditions min Power Supply Current ICCR CS = 0.1VDD, HOLD = WP = 0.9VDD SI = 0.1VDD / 0.9VDD, SO =open (Normal Mode) unit typ max 4.5 8 mA CS = 0.1VDD, SO = WP = HOLD = SI = open VDD = VDD max. Clock frequency = 16MHz (Power saving mode) 3 6 mA CS = 0.1VDD, SO = WP = HOLD = SI = open VDD = VDD max. Clock frequency = 25MHz (frequency setting=0:1) 6 12 mA 10 20 mA 15 mA 50 µA clock frequency = 50MHz, VDD = VDD max Power Supply Current ICCR (HD_Read) CS = 0.1VDD, SO = WP = HOLD = SI = open VDD = VDD max. Clock frequency = 50MHz (frequency setting=1:0) Power Supply Current ICCW VDD = VDD max (Write) tSSE=80ms, tSE=100ms, tCHE=250ms, tPP=0.5ms CMOS standby current ISB CS = HOLD = WP = VDD-0.3V, SO = open SI = VIH / VIL, VDD = VDD max Input Leakage Current ILI VIN = VSS to VDD, VDD = VDD max 2 µA Output Leakage Current ILO VIN = VSS to VDD, VDD = VDD max 2 µA Input Low Voltage VIL VDD = VDD max -0.3 0.3 VDD V Input High Voltage VIH VDD = VDD min 0.7VDD VDD+0.3 V Output low Voltage VOL IOL = 100μA, VDD = VDD min 0.2 V IOL = 1.6mA, VDD = VDD min 0.4 Output High Voltage VOH IOH = -100μA, VDD = VDD min V VDD-0.2 Power-on Timing Parameter Ratings Symbol min unit max Time from power-on to read operation tPU_READ 100 μs Time from power-on to write operation tPU_WRITE 10 ms Power-down time tPD 10 Power-down voltage vBOT ms 0.2 V Pin Capacitance at Ta=25°C, f=1MHz Parameter Symbol Conditions Ratings unit max Output pin capacitance CDQ VDQ=0V 12 pF Input pin Capacitance CIN VIN=0V 6 pF Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices. No.A1432-21/27 LE25FW418A AC Characteristics Parameter Ratings Symbol min unit typ max Clock frequency fCLK SCK High pulse width tCLHI 9 50 SCK Low pulse width tCLLO 9 Input rising, falling time tRF CS Setup time tCSS 5 ns SCK Setup time tCLS 5 ns Data Setup time tDS 2 ns Data Hold time tDH 5 ns ns tAS 2 Address Hold time (HD_READ Mode) tAH 3*1 SCK to output valid tV SCK to output valid (HD_READ) tV2 SCK Hold time CS Standby pulse width ns ns ns 6 SCK to output valid (HD_READ, power saving mode) tCSH ns 20 Address Setup time (HD_READ Mode) CS Hold time MHz 9 ns 6 9 ns 10 15 ns 5 ns tCLH 5 ns tCPH 25 CS to High-Z output tCHZ 1 2.5 Output data hold time tHO 1 2.5 HOLD Setup time tHS 5 ns HOLD Hold time tHH 3 ns HOLD High to Low-Z Output tHLZ ns 8 ns ns 8 ns HOLD Low to High-Z Output tHHZ WP Setup time tWPS 20 ns WP Hold time tWPH 20 ns Status Register Write cycle time tSRW Page Program cycle time tPP Small Sector Erase cycle time 8 ns 5 15 ms 1.5 2.5 ms tSSE 0.025 0.1 s Sector Erase cycle time tSE 0.025 0.5 s Chip Erase cycle time tCHE 0.25 5 s Power Down recovery time tPRB 25 ns SCK to Low-Z output tCLZ 0 ns *1 : 2.7V to 3.0V=3ns , 3.0V to 3.6V=2.5ns AC Test Conditions Input pulse level··············· 0V, 3.0V Input rising/falling time···· 3ns Input timing level············· 0.3VDD, 0.7VDD Output timing level ·········· 1/2×VDD Output load ······················ 30pF Note: As the test conditions for "typ", the measurements are conducted using 3.0V for VDD at room temperature. No.A1432-22/27 LE25FW418A Figure 23 Status Register Write Flowchart Status register write Start 06h 01h Write enable Set status register write command Data Program start on rising edge of CS 05h NO Set status register read command Bit 0= “0” ? YES End of status register write * Automatically placed in write disabled state at the end of the status register write No.A1432-23/27 LE25FW418A Figure 24 Erase Flowcharts Small sector erase Sector erase Start Start 06h Write enable 06h D8h D7h Address 1 NO Address 1 Set small sector erase command Address 2 Address 2 Address 3 Address 3 Start erase on rising edge of CS Start erase on rising edge of CS Set status register read command 05h Write enable 05h NO Bit 0 = “0” ? YES End of erase * Automatically placed in write disabled state at the end of the erase Set sector erase command Set status register read command Bit 0 = “0” ? YES End of erase * Automatically placed in write disabled state at the end of the erase No.A1432-24/27 LE25FW418A Chip erase Start 06h Write enable C7h Set chip erase command Start erase on rising edge of CS 05h NO Set status register read command Bit 0 = “0” ? YES End of erase * Automatically placed in write disabled state at the end of the erase No.A1432-25/27 LE25FW418A Figure 25 Page Program Flowchart Page program Start 06h Write enable 02h Address 1 Set page program command Address 2 Address 3 Data 0 Data n Start program on rising edge of CS Set status register read command 05h NO Bit 0= “0” ? YES End of programming * Automatically placed in write disabled state at the end of the programming operation. No.A1432-26/27 LE25FW418A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2009. Specifications and information herein are subject to change without notice. PS No.A1432-27/27