LMR10510 LMR10510 SIMPLE SWITCHER ® 5.5Vin, 1A Step-Down Voltage Regulator in SOT-23 and LLP Literature Number: SNVS727A LMR10510 SIMPLE SWITCHER® 5.5Vin, 1A Step-Down Voltage Regulator in SOT-23 and LLP Features Performance Benefits ■ ■ ■ ■ ■ Extremely easy to use ■ Tiny overall solution reduces system cost ■ ■ ■ ■ ■ ■ ■ Input voltage range of 3V to 5.5V Output voltage range of 0.6V to 4.5V Output current up to 1A 1.6MHz (LMR10510X) and 3 MHz (LMR10510Y) switching frequencies Low shutdown Iq, 30 nA typical Internal soft-start Internally compensated Current-Mode PWM operation Thermal shutdown SOT23-5 (2.92 x 2.84 x 1 mm) and LLP-6 (3 x 3 x 0.8 mm) packaging Fully enabled for WEBENCH® Power Designer Applications ■ ■ ■ ■ ■ ■ Point-of-Load Conversions from 3.3V, and 5V Rails Space Constrained Applications Battery Powered Equipment Industrial Distributed Power Applications Power Meters Portable Hand-Held Instruments System Performance Efficiency vs Load Current - "Y" VIN = 5V 100 100 90 90 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs Load Current - "X" VIN = 5V 80 70 60 50 40 80 70 60 50 1.8Vout 3.3Vout 40 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 1.8Vout 3.3Vout 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 30165696 30165697 Typical Application 30165664 © 2011 Texas Instruments Incorporated 301656 www.ti.com LMR10510 SIMPLE SWITCHER® 5.5Vin, 1A Step-Down Voltage Regulator in SOT-23 and LLP October 31, 2011 LMR10510 Connection Diagrams 30165603 30165601 5-Pin SOT-23 6-Pin LLP Ordering Information Order Number Frequency Option NSC Package Drawing Package Type Top Mark LMR10510XMFE LMR10510XMF 250 units Tape and Reel 1.6MHz LMR10510XMFX SH7B SOT23-5 LMR10510YMFE LMR10510YSDE LMR10510YSD 250 units Tape and Reel SH9B 1000 units Tape and Reel 3000 units Tape and Reel 3MHz 250 units Tape and Reel LLP-6 SDE06A LMR10510YSDX www.ti.com 1000 units Tape and Reel 3000 units Tape and Reel MF05A LMR10510YMF LMR10510YMFX Supplied As L268B 1000 units Tape and Reel 4500 units Tape and Reel 2 LMR10510 Pin Descriptions 5-Pin SOT23 Pin Name 1 SW 2 GND Function Switch node. Connect to the inductor and catch diode. Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible to this pin. 3 FB Feedback pin. Connect to external resistor divider to set output voltage. 4 EN Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3V. 5 VIN Input supply voltage. Pin Descriptions 6-Pin LLP Pin Name 1 FB 2 GND Function Feedback pin. Connect to external resistor divider to set output voltage. Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible to this pin. 3 SW 4 VIND Switch node. Connect to the inductor and catch diode. Power Input supply. 5 VINA Control circuitry supply voltage. Connect VINA to VIND on PC board. 6 EN Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VINA + 0.3V. DAP Die Attach Pad Connect to system ground for low thermal impedance, but it cannot be used as a primary GND connection. 3 www.ti.com LMR10510 Junction Temperature (Note 2) 150°C Storage Temperature −65°C to +150°C For soldering specifications: see product folder at www.national.com and www.national.com/ms/MS/MS-SOLDERING.pdf Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VIN FB Voltage EN Voltage SW Voltage ESD Susceptibility -0.5V to 7V -0.5V to 3V -0.5V to 7V -0.5V to 7V 2kV Operating Ratings VIN Junction Temperature 3V to 5.5V −40°C to +125°C Electrical Characteristics (Note 3), (Note 4) VIN = 5V unless otherwise indicated under the Conditions column. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol VFB ΔVFB/VIN IB UVLO Parameter Conditions Feedback Voltage Feedback Voltage Line Regulation Min Typ Max Units 0.588 0.600 0.612 V VIN = 3V to 5V 0.02 Feedback Input Bias Current Undervoltage Lockout VIN Rising Switching Frequency DMAX Maximum Duty Cycle DMIN Minimum Duty Cycle RDS(ON) ICL VEN_TH Switch On Resistance Switch Current Limit 2.73 2.90 V 1.85 LMR10510-X 1.2 2.3 1.6 1.95 LMR10510-Y 2.25 3.0 3.75 LMR10510-X 86 94 LMR10510-Y 82 90 0.43 LMR10510-X 5 LMR10510-Y 7 LLP-6 Package 150 SOT23-5 Package 130 VIN = 3.3V 1.2 Switch Leakage Enable Pin Current Quiescent Current (switching) Quiescent Current (shutdown) V MHz % % 195 1.75 mΩ A 0.4 Enable Threshold Voltage IEN www.ti.com nA Shutdown Threshold Voltage ISW IQ 100 VIN Falling UVLO Hysteresis FSW %/V 0.1 1.8 V 100 nA Sink/Source 100 nA LMR10510X VFB = 0.55 3.3 5 mA LMR10510Y VFB = 0.55 4.3 6.5 mA All Options VEN = 0V 30 4 nA Parameter θJA Junction to Ambient 0 LFPM Air Flow (Note 5) θJC Junction to Case TSD Thermal Shutdown Temperature Conditions Min Typ LLP-6 Package 80 SOT23-5 Package 118 LLP-6 Package 18 SOT23-5 Package 80 165 Max Units °C/W °C/W °C Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not guarantee specfic performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device. Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 4: Typical numbers are at 25°C and represent the most likely parametric norm. Note 5: Applies for packages soldered directly onto a 3” x 3” PC board with 2oz. copper on 4 layers in still air. 5 www.ti.com LMR10510 Symbol Unless stated otherwise, all curves taken at VIN = 5.0V with configuration in typical application circuit shown in Figure 3. TJ = 25° C, unless otherwise specified. η vs Load "Y" Vin = 5V, Vo = 3.3V & 1.8V 100 100 90 90 EFFICIENCY (%) EFFICIENCY (%) η vs Load "X" Vin = 5V, Vo = 1.8V & 3.3V 80 70 60 50 40 80 70 60 50 1.8Vout 3.3Vout 40 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 1.8Vout 3.3Vout 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 30165696 30165697 η vs Load "X and Y" Vin = 3.3V, Vo = 1.8V Load Regulation Vin = 3.3V, Vo = 1.8V (All Options) 100 90 EFFICIENCY (%) LMR10510 Typical Performance Characteristics 80 70 60 50 40 LMR10510Y LMR10510X 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 30165698 30165683 www.ti.com 6 LMR10510 Load Regulation Vin = 5V, Vo = 1.8V (All Options) Load Regulation Vin = 5V, Vo = 3.3V (All Options) 30165684 30165685 Oscillator Frequency vs Temperature - "X" Oscillator Frequency vs Temperature - "Y" 30165624 30165636 Current Limit vs Temperature Vin = 3.3V RDSON vs Temperature (LLP-6 Package) 30165687 30165686 7 www.ti.com LMR10510 RDSON vs Temperature (SOT23-5 Package) LMR10510X IQ (Quiescent Current) 30165688 30165628 LMR10510Y IQ (Quiescent Current) Line Regulation Vo = 1.8V, Io = 500mA 30165637 30165653 VFB vs Temperature 30165627 www.ti.com 8 LMR10510 Gain vs Frequency (Vin = 5V, Vo = 1.2V @ 1A) Phase Plot vs Frequency (Vin = 5V, Vo = 1.2V @ 1A) 30165656 30165657 Simplified Block Diagram 30165604 FIGURE 1. 9 www.ti.com LMR10510 General Description The LMR10510 regulator is a monolithic, high frequency, PWM step-down DC/DC converter in a 5 pin SOT23 and a 6 Pin LLP package. It provides all the active functions to provide local DC/DC conversion with fast transient response and accurate regulation in the smallest possible PCB area. With a minimum of external components, the LMR10510 is easy to use. The ability to drive 1.0A loads with an internal 130 mΩ PMOS switch results in the best power density available. The world-class control circuitry allows on-times as low as 30ns, thus supporting exceptionally high frequency conversion over the entire 3V to 5.5V input operating range down to the minimum output voltage of 0.6V. The LMR10510 is a constant frequency PWM buck regulator IC that delivers a 1.0A load current. The regulator has a preset switching frequency of 1.6MHz or 3.0MHz. This high frequency allows the LMR10510 to operate with small surface mount capacitors and inductors, resulting in a DC/DC converter that requires a minimum amount of board space. The LMR10510 is internally compensated, so it is simple to use and requires few external components. Even though the operating frequency is high, efficiencies up to 93% are easy to achieve. External shutdown is included, featuring an ultra-low stand-by current of 30 nA. The LMR10510 utilizes current-mode control and internal compensation to provide high-performance regulation over a wide range of operating conditions. Additional features include internal soft-start circuitry to reduce inrush current, pulse-by-pulse current limit, thermal shutdown, and output over-voltage protection. 30165666 FIGURE 2. Typical Waveforms SOFT-START This function forces VOUT to increase at a controlled rate during start up. During soft-start, the error amplifier’s reference voltage ramps from 0V to its nominal value of 0.6V in approximately 600 µs. This forces the regulator output to ramp up in a controlled fashion, which helps reduce inrush current. OUTPUT OVERVOLTAGE PROTECTION The over-voltage comparator compares the FB pin voltage to a voltage that is 15% higher than the internal reference VREF. Once the FB pin voltage goes 15% above the internal reference, the internal PMOS control switch is turned off, which allows the output voltage to decrease toward regulation. Applications Information THEORY OF OPERATION The following operating description of the LMR10510 will refer to the Simplified Block Diagram (Figure 1) and to the waveforms in Figure 2. The LMR10510 supplies a regulated output voltage by switching the internal PMOS control switch at constant frequency and variable duty cycle. A switching cycle begins at the falling edge of the reset pulse generated by the internal oscillator. When this pulse goes low, the output control logic turns on the internal PMOS control switch. During this on-time, the SW pin voltage (VSW) swings up to approximately VIN, and the inductor current (IL) increases with a linear slope. IL is measured by the current sense amplifier, which generates an output proportional to the switch current. The sense signal is summed with the regulator’s corrective ramp and compared to the error amplifier’s output, which is proportional to the difference between the feedback voltage and VREF. When the PWM comparator output goes high, the output switch turns off until the next switching cycle begins. During the switch off-time, inductor current discharges through the Schottky catch diode, which forces the SW pin to swing below ground by the forward voltage (VD) of the Schottky catch diode. The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage. www.ti.com UNDERVOLTAGE LOCKOUT Under-voltage lockout (UVLO) prevents the LMR10510 from operating until the input voltage exceeds 2.73V (typ). The UVLO threshold has approximately 430 mV of hysteresis, so the part will operate until VIN drops below 2.3V (typ). Hysteresis prevents the part from turning off during power up if VIN is non-monotonic. CURRENT LIMIT The LMR10510 uses cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a current limit comparator detects if the output switch current exceeds 1.75A (typ), and turns off the switch until the next switching cycle begins. THERMAL SHUTDOWN Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature exceeds 165°C. After thermal shutdown occurs, the output switch doesn’t turn on until the junction temperature drops to approximately 150°C. 10 LMR10510 30165695 FIGURE 3. Typical Application Schematic Design Guide INDUCTOR SELECTION The Duty Cycle (D) can be approximated quickly using the ratio of output voltage (VO) to input voltage (VIN): In general, ΔiL = 0.1 x (IOUT) → 0.2 x (IOUT) If ΔiL = 20% of 1A, the peak current in the inductor will be 1.2A. The minimum guaranteed current limit over all operating conditions is 1.2A. One can either reduce ΔiL, or make the engineering judgment that zero margin will be safe enough. The typical current limit is 1.75A. The LMR10510 operates at frequencies allowing the use of ceramic output capacitors without compromising transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple. See the output capacitor section for more details on calculating output voltage ripple. Now that the ripple current is determined, the inductance is calculated by: The catch diode (D1) forward voltage drop and the voltage drop across the internal PMOS must be included to calculate a more accurate duty cycle. Calculate D by using the following formula: VSW can be approximated by: VSW = IOUT x RDSON The diode forward drop (VD) can range from 0.3V to 0.7V depending on the quality of the diode. The lower the VD, the higher the operating efficiency of the converter. The inductor value determines the output ripple current. Lower inductor values decrease the size of the inductor, but increase the output ripple current. An increase in the inductor value will decrease the output ripple current. One must ensure that the minimum current limit (1.2A) is not exceeded, so the peak current in the inductor must be calculated. The peak current (ILPK) in the inductor is calculated by: Where When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating. Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating correctly. Because of the speed of the internal current limit, the peak current of the inductor need only be specified for the required maximum output current. For example, if the designed maximum output current is 1.0A and the peak current is 1.25A, then the inductor should be specified with a saturation current limit of > 1.25A. There is no need to specify the saturation or peak current of the inductor at the 1.75A typical switch current limit. The difference in inductor size is a factor of 5. Because of the operating frequency of the LMR10510, ferrite based inductors are preferred to minimize core losses. This presents little restriction since the variety of ferrite-based inductors is huge. Lastly, inductors with lower series resistance (RDCR) will pro- ILPK = IOUT + ΔiL 30165605 FIGURE 4. Inductor Current 11 www.ti.com LMR10510 tances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not. Since the output capacitor is one of the two external components that control the stability of the regulator control loop, most applications will require a minimum of 22 µF of output capacitance. Capacitance often, but not always, can be increased significantly with little detriment to the regulator stability. Like the input capacitor, recommended multilayer ceramic capacitors are X7R or X5R types. vide better operating efficiency. For recommended inductors see Example Circuits. INPUT CAPACITOR An input capacitor is necessary to ensure that VIN does not drop excessively during switching transients. The primary specifications of the input capacitor are capacitance, voltage, RMS current rating, and ESL (Equivalent Series Inductance). The recommended input capacitance is 22 µF.The input voltage rating is specifically stated by the capacitor manufacturer. Make sure to check any recommended deratings and also verify if there is any significant change in capacitance at the operating input voltage and the operating temperature. The input capacitor maximum RMS input current rating (IRMS-IN) must be greater than: CATCH DIODE The catch diode (D1) conducts during the switch off-time. A Schottky diode is recommended for its fast switching times and low forward voltage drop. The catch diode should be chosen so that its current rating is greater than: ID1 = IOUT x (1-D) The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin. To improve efficiency, choose a Schottky diode with a low forward voltage drop. Neglecting inductor ripple simplifies the above equation to: OUTPUT VOLTAGE The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and R1 is connected between VO and the FB pin. A good value for R2 is 10kΩ. When designing a unity gain converter (Vo = 0.6V), R1 should be between 0Ω and 100Ω, and R2 should be equal or greater than 10kΩ. It can be shown from the above equation that maximum RMS capacitor current occurs when D = 0.5. Always calculate the RMS at the point where the duty cycle D is closest to 0.5. The ESL of an input capacitor is usually determined by the effective cross sectional area of the current path. A large leaded capacitor will have high ESL and a 0805 ceramic chip capacitor will have very low ESL. At the operating frequencies of the LMR10510, leaded capacitors may have an ESL so large that the resulting impedance (2πfL) will be higher than that required to provide stable operation. As a result, surface mount capacitors are strongly recommended. Sanyo POSCAP, Tantalum or Niobium, Panasonic SP, and multilayer ceramic capacitors (MLCC) are all good choices for both input and output capacitors and have very low ESL. For MLCCs it is recommended to use X7R or X5R type capacitors due to their tolerance and temperature characteristics. Consult capacitor manufacturer datasheets to see how rated capacitance varies over operating conditions. VREF = 0.60V PCB LAYOUT CONSIDERATIONS When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The most important consideration is the close coupling of the GND connections of the input capacitor and the catch diode D1. These ground ends should be close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. Next in importance is the location of the GND connection of the output capacitor, which should be near the GND connections of CIN and D1. There should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with the GND of R1 placed as close as possible to the GND of the IC. The VOUT trace to R2 should be routed away from the inductor and any other traces that are switching. High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as possible. However, making the traces wide increases radiated noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor. The remaining components should also be placed as close as possible to the IC. Please see Application Note AN-1229 for further considerations and the LMR10510 demo board as an example of a good layout. OUTPUT CAPACITOR The output capacitor is selected based upon the desired output ripple and transient response. The initial current of a load transient is provided mainly by the output capacitor. The output ripple of the converter is: When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the output ripple will be approximately sinusoidal and 90° phase shifted from the switching action. Given the availability and quality of MLCCs and the expected output voltage of designs using the LMR10510, there is really no need to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to bypass high frequency noise. A certain amount of switching edge noise will couple through parasitic capaci- www.ti.com 12 If the inductor ripple current is fairly small, the conduction losses can be simplified to: The complete LMR10510 DC/DC converter efficiency can be calculated in the following manner. Switching losses are also associated with the internal PFET. They occur during the switch on and off transition periods, where voltages and currents overlap resulting in power loss. The simplest means to determine this loss is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node. Switching Power Loss is calculated as follows: PCOND = IOUT2 x RDSON x D Or PSWR = 1/2(VIN x IOUT x FSW x TRISE) PSWF = 1/2(VIN x IOUT x FSW x TFALL) PSW = PSWR + PSWF Another loss is the power required for operation of the internal circuitry: Calculations for determining the most significant power losses are shown below. Other losses totaling less than 2% are not discussed. Power loss (PLOSS) is the sum of two basic types of losses in the converter: switching and conduction. Conduction losses usually dominate at higher output loads, whereas switching losses remain relatively fixed and dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D): PQ = IQ x VIN IQ is the quiescent operating current, and is typically around 3.3mA for the 1.6MHz frequency option. Typical Application power losses are: Power Loss Tabulation VSW is the voltage drop across the internal PFET when it is on, and is equal to: VSW = IOUT x RDSON VD is the forward voltage drop across the Schottky catch diode. It can be obtained from the diode manufactures Electrical Characteristics section. If the voltage drop across the inductor (VDCR) is accounted for, the equation becomes: VIN 5.0V VOUT 3.3V POUT 3.3W PDIODE 150mW IOUT 1.0A VD 0.45V FSW 1.6MHz IQ 3.3mA PQ 17mW TRISE 4nS PSWR 16mW TFALL 4nS PSWF 16mW RDS(ON) 150mΩ PCOND 100mW INDDCR 70mΩ PIND 70mW D 0.667 PLOSS 369mW η 88% PINTERNAL 149mW ΣPCOND + PSW + PDIODE + PIND + PQ = PLOSS ΣPCOND + PSWF + PSWR + PQ = PINTERNAL PINTERNAL = 149mW Thermal Definitions The conduction losses in the free-wheeling Schottky diode are calculated as follows: TJ = Chip junction temperature TA = Ambient temperature RθJC = Thermal resistance from chip junction to device case RθJA = Thermal resistance from chip junction to ambient air Heat in the LMR10510 due to internal power dissipation is removed through conduction and/or convection. Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs. conductor). Heat Transfer goes as: Silicon → package → lead frame → PCB Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural convection occurs when air currents rise from the hot device to cooler air. Thermal impedance is defined as: PDIODE = VD x IOUT x (1-D) Often this is the single most significant power loss in the circuit. Care should be taken to choose a Schottky diode that has a low forward voltage drop. Another significant external power loss is the conduction loss in the output inductor. The equation can be simplified to: PIND = IOUT2 x RDCR The LMR10510 conduction loss is mainly associated with the internal PFET: 13 www.ti.com LMR10510 Calculating Efficiency, and Junction Temperature LMR10510 Thermal impedance from the silicon junction to the ambient air is defined as: Once this is determined, the maximum ambient temperature allowed for a desired junction temperature can be found. An example of calculating RθJA for an application using the LMR10510 is shown below. A sample PCB is placed in an oven with no forced airflow. The ambient temperature was raised to 147°C, and at that temperature, the device went into thermal shutdown. From the previous example: The PCB size, weight of copper used to route traces and ground plane, and number of layers within the PCB can greatly effect RθJA. The type and number of thermal vias can also make a large difference in the thermal impedance. Thermal vias are necessary in most applications. They conduct heat from the surface of the PCB to the ground plane. Four to six thermal vias should be placed under the exposed pad to the ground plane if the LLP package is used. Thermal impedance also depends on the thermal properties of the application operating conditions (Vin, Vo, Io etc), and the surrounding circuitry. Silicon Junction Temperature Determination Method 1: To accurately measure the silicon temperature for a given application, two methods can be used. The first method requires the user to know the thermal impedance of the silicon junction to case temperature. RθJC is approximately 18°C/Watt for the 6-pin LLP package with the exposed pad. Knowing the internal dissipation from the efficiency calculation given previously, and the case temperature, which can be empirically measured on the bench we have: PINTERNAL = 149 mW Since the junction temperature must be kept below 125°C, then the maximum ambient temperature can be calculated as: Tj - (RθJA x PLOSS) = TA 125°C - (121°C/W x 149 mW) = 107°C LLP Package where TC is the temperature of the exposed pad and can be measured on the bottom side of the PCB. Therefore: 30165668 FIGURE 5. Internal LLP Connection Tj = (RθJC x PLOSS) + TC For certain high power applications, the PCB land may be modified to a "dog bone" shape (see Figure 6). By increasing the size of ground plane, and adding thermal vias, the RθJA for the application can be reduced. From the previous example: Tj = (RθJC x PINTERNAL) + TC Tj = 18°C/W x 0.149W + TC The second method can give a very accurate silicon junction temperature. The first step is to determine RθJA of the application. The LMR10510 has over-temperature protection circuitry. When the silicon temperature reaches 165°C, the device stops switching. The protection circuitry has a hysteresis of about 15°C. Once the silicon temperature has decreased to approximately 150°C, the device will start to switch again. Knowing this, the RθJA for any application can be characterized during the early stages of the design one may calculate the RθJA by placing the PCB circuit into a thermal chamber. Raise the ambient temperature in the given working application until the circuit enters thermal shutdown. If the SW-pin is monitored, it will be obvious when the internal PFET stops switching, indicating a junction temperature of 165°C. Knowing the internal power dissipation from the above methods, the junction temperature, and the ambient temperature RθJA can be determined. www.ti.com 30165606 FIGURE 6. 6-Lead LLP PCB Dog Bone Layout 14 LMR10510 LMR10510X Design Example 1 30165607 FIGURE 7. LMR10510X (1.6MHz): Vin = 5V, Vo = 1.2V @ 1.0A LMR10510X Design Example 2 30165608 FIGURE 8. LMR10510X (1.6MHz): Vin = 5V, Vo = 3.3V @ 1.0A 15 www.ti.com LMR10510 LMR10510Y Design Example 3 30165660 FIGURE 9. LMR10510Y (3MHz): Vin = 5V, Vo = 3.3V @ 1.0A LMR10510Y Design Example 4 30165662 FIGURE 10. LMR10510Y (3MHz): Vin = 5V, Vo = 1.2V @ 1.0A www.ti.com 16 LMR10510 Physical Dimensions inches (millimeters) unless otherwise noted 5-Lead SOT-23 Package NS Package Number MF05A 6-Lead LLP Package NS Package Number SDE06A 17 www.ti.com LMR10510 SIMPLE SWITCHER® 5.5Vin, 1A Step-Down Voltage Regulator in SOT-23 and LLP Notes TI/NATIONAL INTERIM IMPORTANT NOTICE Texas Instruments has purchased National Semiconductor. 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