LMR14003, LMR14006 www.ti.com SNVSA10 – NOVEMBER 2013 SIMPLE SWITCHER® 40V 300/600mA Buck Regulators with High Efficiency Sleep Mode Check for Samples: LMR14003, LMR14006 FEATURES 1 • • • • • • • • • • • • • Ultra Low 28µA Standby Current in Sleep Mode Input Voltage Range 4V to 40V 1µA Shutdown Current High Duty Cycle Operation Supported Output Current Options of 300mA and 600mA 5V Fixed Voltage Option Available 1.1MHz and 2.1MHz Switching Frequency Internal Compensation High Voltage Enable Input Internal Soft Start Over Current Protection Over Temperature Protection Small Overall Solution Size (TSOT-6L Package) APPLICATIONS • • • • • Industrial Distributed Power Systems Automotive Battery Powered Equipment Portable Handheld Instruments Portable Media Players DESCRIPTION The LMR14003 and LMR14006 are PWM DC/DC buck (step-down) regulators. With a wide input range of 4V-40V, they are suitable for a wide range of application from industrial to automotive for power conditioning from an unregulated source. The regulator’s standby current is 28µA in sleep mode, which is suitable for battery operating systems. An ultra low 1µA current can further prolong battery life in shutdown mode. Operating frequency is fixed at 1.1MHz(X version) and 2.1MHz(Y version) allowing the use of small external components while still being able to have low output ripple voltage. Soft-start and compensation circuits are implemented internally, and these allow the device to be used with minimized external components. The LMR14006 is optimized for up to 600mA load currents while the LMR14003 is optimized for up to 300mA load current. They all have a 0.765V typical feedback voltage. The device has built-in protection features such as pulse by pulse current limit, thermal sensing and shutdown due to excessive power dissipation. The LMR14003 and LMR14006 are available in a low profile TSOT-6L package. VIN Up to 40V VIN CB Cboot L1 Cin 5V, 0.3/0.6A SW SHDN LMR14003/6 Cout D1 R1 GND FB Fixed 5V Output Option Available R2 Figure 1. Typical Application Schematic 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LMR14003, LMR14006 SNVSA10 – NOVEMBER 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) Description Value Unit VIN, /SHDN Unregulated inputs -0.3 to 45 V FB Sense voltage for error amplifiers -0.3 to 7 V SW Switch point for buck converter -0.3 to 40 V -2V for 30ns (1) BOOT Bootstrap capacitor voltage -0.3 to 46 V ESD Electrostatic Discharge HBM 2 kV TS Storage Temperature Range -55 to 165 °C TJ Junction temperature range -40 to 150 °C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS (1) (1) Function Terminal Value Unit Buck Regulator VIN 4 to 40 V CB 4 to 46 V SW -1 to 40 V FB 0 to 5.5 V Control /SHDN 0 to 40 V Temperature Operating junction temperature range, TJ -40 to 125 °C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS VIN = /SHDN = 12V, TA = 25°C, unless otherwise specified. Parameter Conditions Min Typ Max Unit VIN (Input Power Supply) Operating input voltage 4 Shutdown supply current EN = 0V 1 Undervoltage lockout thresholds Rising threshold Falling threshold 40 V 3 µA 4 V 3 Device on : not switching Sleep mode, no load, VIN = 12V 28 µA Device on : not switching Fixed 5V version, VIN = 12V, 25°C 31 µA /SHDN AND UVLO Rising /SHDN Threshold Voltage Input current 1.05 1.25 /SHDN = 2.3V –4.2 /SHDN = 0.9V –1 Hysteresis current 1.38 V µA –3 µA HIGH-SIDE MOSFET On-resistance VIN = 12V, CB to SW=5.8V 600 mΩ tON-min fsw = 2.1MHz 95 ns DMAX : Maximum duty cycle LMR14003/6 X 96 % LMR14003/6 Y 97 VFB : Feedback voltage 0.747 0.765 0.782 V VIN = 12V, TJ = 25°C(LMR14003) 600 900 mA VIN = 12V, TJ = 25°C(LMR14006) 1200 1700 mA CURRENT LIMIT Current limit threshold 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 LMR14003, LMR14006 www.ti.com SNVSA10 – NOVEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) VIN = /SHDN = 12V, TA = 25°C, unless otherwise specified. Parameter Conditions Min Typ Max Unit fSW Switching frequency LMR14003/6 935 1100 1285 kHz LMR14003/6 1785 2100 2415 kHz Thermal Performance TSHUTDOWN Thermal shutdown trip point THYS Hysteresis 170 ºC 10 ºC DDC Package TSOT-6L (TOP VIEW) LMR14003/6 CB 1 GND 2 FB PIN 1 ID 3 6 SW 5 VIN 4 SHDN TSOT-6L Table 1. PIN FUNCTIONS Name NO. I/O Description CB 1 O SW FET Gate Bias voltage. Connect Cboot cap between CB and SW GND 2 - Ground Connection FB 3 I Feedback Pin: Set feedback voltage divider ratio with VOUT = VFB (1+(R1/R2)) /SHDN 4 I Enable and disable input pin(high voltage tolerant). Internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. VIN 5 I Power input voltage pin: Input for internal supply and drain node input for internal high-side MOSFET SW 6 I Switch node, Connect to inductor, diode, and Cboot cap Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 3 LMR14003, LMR14006 SNVSA10 – NOVEMBER 2013 www.ti.com Table 2. PART ORDERING INFORMATION 4 Order Number Package Supplied As Top-Side Marking LMR14003XDDCT TSOT-6 250 Units on Tape and Reel Product Preview LMR14003XDDCR 3000 Units on Tape and Reel Product Preview LMR14003YDDCT 250 Units on Tape and Reel Product Preview LMR14003YDDCR 3000 Units on Tape and Reel Product Preview LMR14006XDDCT 250 Units on Tape and Reel B02X LMR14006XDDCR 3000 Units on Tape and Reel B02X LMR14006YDDCT 250 Units on Tape and Reel B02Y LMR14006YDDCR 3000 Units on Tape and Reel B02Y LMR14003YQDDCT 250 Units on Tape and Reel Product Preview LMR14003YQDDCR 3000 Units on Tape and Reel Product Preview LMR14006YQDDCT 250 Units on Tape and Reel Product Preview LMR14006YQDDCR 3000 Units on Tape and Reel Product Preview LMR14003YQ5DDCT 250 Units on Tape and Reel Product Preview LMR14003YQ5DDCR 3000 Units on Tape and Reel Product Preview LMR14006YQ5DDCT 250 Units on Tape and Reel Product Preview LMR14006YQ5DDCR 3000 Units on Tape and Reel Product Preview Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 LMR14003, LMR14006 www.ti.com SNVSA10 – NOVEMBER 2013 TYPICAL CHARACTERISTICS VIN = 12V, TA = 25°C, unless otherwise specified. Efficiency vs. Load Current (fSW = 2.1MHz, Vout = 12V) Efficiency vs. Load Current (fSW = 2.1MHz, Vout = 5V) 100 100 Vin = 15V Vin = 18V 80 80 Efficiency (%) Efficiency (%) Vin = 12V 90 90 70 60 Vin = 15V 70 60 50 50 40 40 30 0.1 1 10 100 0.1 1000 Output Current (mA) 1 Figure 2. 100 1000 C003 Figure 3. Efficiency vs. Load Current (fSW=2.1MHz) Line Regulation (Vout=5V, 200mA Load) 4% 100 90 Vout = 5V 3% 70 Output Voltage Change 80 Efficiency (%) 10 Output Current (mA) C002 Vout = 3.3V 60 50 40 30 20 2% 1% 0% ±1% ±2% ±3% 10 0 ±4% 0.1 1 10 100 5 1000 Output Current (mA) 7 9 11 13 15 17 19 Input Voltage (V) C001 Figure 4. 21 C002 Figure 5. Load Regulation (Vout=5V) Supply Current vs Input Voltage (No Load) 100 1.5% Sleep Input Current (uA) Output Voltage Change 1.0% 0.5% 0.0% ±0.5% 10 Shutdown 1 ±1.0% 0.1 ±1.5% 0 100 200 300 400 Load Current (mA) 500 600 4 C003 Figure 6. 14 24 34 Input Voltage (V) 44 C001 Figure 7. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 5 LMR14003, LMR14006 SNVSA10 – NOVEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VIN = 12V, TA = 25°C, unless otherwise specified. Switching Node and Output Voltage Waveform (Vout=5V, 600mA Load) UVLO vs Temperature 3.60 Undervoltage Lockout (V) 3.55 UVLO_H 3.50 3.45 3.40 3.35 3.30 3.25 UVLO_L 3.20 3.15 3.10 ±50 0 50 100 Temperature (C) 6 150 C004 Figure 8. Figure 9. 12V Output Start-up Waveform (Vin=18V, 300mA Load) 12V Output Shutdown Waveform (Vin=18V, 300mA Load) Figure 10. Figure 11. 5V Output Start-up Waveform (300mA Load) 5V Output Shutdown Waveform (300mA Load) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 LMR14003, LMR14006 www.ti.com SNVSA10 – NOVEMBER 2013 TYPICAL CHARACTERISTICS (continued) VIN = 12V, TA = 25°C, unless otherwise specified. Short Circuit to Ground (5V) Load Transient Waveform (50mA to 300mA) Figure 14. Figure 15. INTERNAL FUNCTIONAL BLOCKS VIN Leading Edge Blanking Bootstrap Regulator CB Logic & PWM Latch HS Driver SW PWM Comparator ± Frequency Shift + 0.765V SS + COMP EA + ± Main OSC SHDN Bandgap Ref FB Slope Compensation GND Fixed 5V Option Figure 16. DETAILED DESCRIPTION The LMR14003/6 device is a 40V, 300mA/600mA, step-down (buck) converter. The buck regulator has a very low quiescent current during light load to prolong the battery life. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 7 LMR14003, LMR14006 SNVSA10 – NOVEMBER 2013 www.ti.com For LMR14003/6, to improve performance during line and load transients it implements a constant frequency, current mode control which requires less output capacitance and simplifies frequency compensation design. Two switching frequency options, 1.1MHz and 2.1MHz, are available, thus smaller inductor and capacitor can be used. The LMR14003/6 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the CB to SW pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high side MOSFET off when the boot voltage falls below a preset threshold. The LMR14003/6 can operate at high duty cycles because of the boot UVLO and refresh wimp FET. The output voltage can be stepped down to as low as the 0.8V reference. Internal soft start is featured to minimize inrush currents. Continuous Conduction Mode The LMR14003/6 steps the input voltage down to a lower output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady state), the buck regulator operates in two cycles. The power switch is connected between VIN and SW. In the first cycle of operation the transistor is closed and the diode is reverse biased. Energy is collected in the inductor and the load current is supplied by Cout and the rising current through the inductor. During the second cycle the transistor is open and the diode is forward biased due to the fact that the inductor current cannot instantaneously change direction. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as: D = VOUT/VIN and D' = (1-D) where D is the duty cycle of the switch, D and D' will be required for design calculations. Fixed Frequency PWM Control The LMR14003/6 has two fixed frequency options, and it implements peak current mode control. The output voltage is compared through external resistors on the VFB pin to an internal voltage reference by an error amplifier which drives the internal COMP node. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current. When the power switch current reaches the level set by the internal COMP voltage, the power switch is turned off. The internal COMP node voltage will increase and decrease as the output current increases and decreases. The device implements a current limit by clamping the COMP node voltage to a maximum level. Sleep Mode The LMR14003/6 operates in sleep mode at light load currents to improve efficiency by reducing switching and gate drive losses. The LMR14003/6 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the sleep current threshold, IINDUCTOR ≤ 80mA, the device enters sleep mode. For sleep mode operation, the LMR14003/6 senses peak current, not average or load current, so the load current where the device enters sleep mode is dependent on the output inductor value. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 28µA input quiescent current. Bootstrap Voltage (CB) The LMR14003/6 has an integrated boot regulator, and requires a small ceramic capacitor between the CB and SW pins to provide the gate drive voltage for the high side MOSFET. The CB capacitor is refreshed when the high side MOSFET is off and the low side diode conducts. To improve drop out, the LMR14003/6 is designed to operate at 100% duty cycle as long as the CB to SW pin voltage is greater than 3V. When the voltage from CB to SW drops below 3V, the high side MOSFET is turned off using an UVLO circuit which allows the low side diode to conduct and refresh the charge on the CB capacitor. Since the supply current sourced from the CB capacitor is low, the high side MOSFET can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching regulator is high. Attention must be taken in maximum duty cycle applications with light load. To ensure SW can be pulled to ground to refresh the CB capacitor, an internal circuit will charge the CB capacitor when the load is light or the device is working in dropout condition. Output Voltage Setting The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in Figure 1. The feedback pin voltage 0.765V, so the ratio of the feedback resistors sets the output voltage according to the following equation: VOUT = 0.765V (1+(R1/R2)) Typically R2 will be given as 100Ω - 10kΩ for a starting value. To solve for R1 given R2 and Vout uses R1 = R2 ((VOUT/0.765V)-1). 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 LMR14003, LMR14006 www.ti.com SNVSA10 – NOVEMBER 2013 Enable (/SHDN) and VIN Under Voltage Lockout LMR14003/6 /SHDN pin is a high voltage tolerant input with an internal pull up circuit. The device can be enabled even if the /SHDN pin is floating. The regulator can also be turned on using 1.23V or higher logic signals. If the use of a higher voltage is desired due to system or other constraints, a 100kΩ or larger resistor is recommended between the applied voltage and the /SHDN pin to protect the device. When /SHDN is pulled down to 0V, the chip is turned off and enters the lowest shutdown current mode. In shutdown mode the supply current will be decreased to approximately 1µA. If the shutdown function is not to be used the /SHDN pin may be tied to VIN. The maximum voltage to the SHDN pin should not exceed 40V. LMR14003/6 has an internal UVLO circuit to shutdown the output if the input voltage falls below an internally fixed UVLO threshold level. This ensures that the regulator is not latched into an unknown state during low input voltage conditions. The regulator will power up when the input voltage exceeds the voltage level. If there is a requirement for a higher UVLO voltage, the /SHDN can be used to adjust the input voltage UVLO by using external resistors. Current Limit The LMR14003/6 implements current mode control which uses the internal COMP voltage to turn off the high side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and internal COMP voltage are compared, when the peak switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP node high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit. Overvoltage Transient Protection The LMR14003/6 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low value output capacitor, by implementing a circuit to compare the FB pin voltage to OVTP threshold which is 108% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower than the OVTP threshold, the high side MOSFET is allowed to turn on at the next clock cycle. Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 170°C(typ). The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the junction temperature decreases below 160°C(typ), the device reinitiates the power up sequence. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 9 LMR14003, LMR14006 SNVSA10 – NOVEMBER 2013 www.ti.com APPLICATION INFORMATION Design Guide – Step By Step Design Procedure This example details the design of a high frequency switching regulator using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level: Input Voltage, VIN 9V to 16V, Typical 12V Output Voltage, VOUT 5.0V ± 3% Maximum Output Current IO_max 0.6A Minimum Output Current IO_min 0.03A Transient Response 0.03A to 0.6A 5% Output Voltage Ripple 1% Switching Frequency Fsw 2.1MHz Target during Load Transient Over Voltage Peak Value 106% of Output Voltage Under Voltage Value 91% of Output Voltage Selecting the Switching Frequency The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage and the output voltage and the frequency shift limitation. For this example, the output voltage is 5V and the maximum input voltage is 16V, a switching frequency of 2100kHz is used. Output Inductor Selection The most critical parameters for the inductor are the inductance, peak current and the DC resistance. The inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages. Since the ripple current increases with the input voltage, the maximum input voltage is always used to determine the inductance. To calculate the minimum value of the output inductor, use Equation 1. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. A reasonable value is setting the ripple current to be 30% of the DC output current. For this design example, the minimum inductor value is calculated to be 9.1 µH, and a nearest standard value was chosen: 10 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 3 and Equation 4. The inductor ripple current is 0.16A, and the RMS current is 0.602A. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. A good starting point for most applications is a 10μH with 2A current rating. Using a rating near 2A will enable the LMR14003/6 to current limit without saturating the inductor. This is preferable to the LMR14003/6 going into thermal shutdown mode and the possibility of damaging the inductor if the output is shorted to ground or other long-term overload. Vin max Vout Vout Lo min u I o u K IND Vin max u f sw (1) I ripple I L-RMS I L peak 10 Vout u (Vin max Vout ) Vin max u Lo u f sw (2) 1 I ripple2 12 (3) I o2 Io I ripple 2 (4) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 LMR14003, LMR14006 www.ti.com SNVSA10 – NOVEMBER 2013 Output Capacitor The selection of COUT is mainly driven by three primary considerations. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the most stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 5 shows the minimum output capacitance necessary to accomplish this. For this example, the transient load response is specified as a 3% change in VOUT for a load step from 0.03A to 0.6A (full load). For this example, ΔIOUT = 0.6 0.03 = 0.57A and ΔVOUT = 0.03 × 5 = 0.15V. Using these numbers gives a minimum capacitance of 3.6µF. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account. The stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. Equation 6 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be from 0.6A to 0.03A. The output voltage will increase during this load transition and the stated maximum in our specification is 3% of the output voltage. This will make Vo_overshoot = 1.03 × 5 = 5.15V. Vi is the initial capacitor voltage which is the nominal output voltage of 5V. Using these numbers in Equation 6 yields a minimum capacitance of 2.36µF. Equation 7 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Vo_ripple is the maximum allowable output voltage ripple, and IL_ripple is the inductor ripple current. Equation 7 yields 0.21µF. Equation 8 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 8 indicates the ESR should be less than 277mΩ. Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase this minimum value. For this example, 10µF ceramic capacitors will be used. Capacitors in the range of 4.7µF100µF are a good starting point with an ESR of 0.1Ω or less. 2 u 'I out Cout ! fsw u 'Vout (5) Cout ! Lo u Cout ( Ioh2 Iol 2 ) (Vf 2 Vi 2 ) 1 1 ! u V 8 u fsw o _ ripple I L _ ripple RESR (6) (7) Vo _ ripple I L _ ripple (8) Schottky Diode The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. The current rating for the diode should be equal to the maximum output current for best reliability in most applications. In cases where the input voltage is much greater than the output voltage the average diode current is lower. In this case it is possible to use a diode with a lower average current rating, approximately (1-D) × IOUT however the peak current rating should be higher than the maximum load current. A 0.5A to 1A rated diode is a good starting point. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 11 LMR14003, LMR14006 SNVSA10 – NOVEMBER 2013 www.ti.com Input Capacitor A low ESR ceramic capacitor is needed between the VIN pin and ground pin. This capacitor prevents large voltage transients from appearing at the input. Use a 1µF-10µF value with X5R or X7R dielectric. Depending on construction, a ceramic capacitor’s value can decrease up to 50% of its nominal value when rated voltage is applied. Consult with the capacitor manufactures data sheet for information on capacitor derating over voltage and temperature. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the LMR14003/6. The input ripple current can be calculated using below Equation 9. For this example design, one 2.2µF, 50V capacitor is selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 10. Using the design example values, IOUTmax = 0.6A, CIN = 2.2µF, ƒSW = 2100kHz, yields an input voltage ripple of 32.5mV and a rms input ripple current of 0.3A. I cirms 'Vin I out u (Vin min Vout ) Vout u Vin min Vin min (9) I out max u 0.25 Cin u fsw (10) Bootstrap Capacitor Selection A 0.1μF ceramic capacitor or larger is recommended for the bootstrap capacitor (CBOOT). For applications where the input voltage is close to output voltage a larger capacitor is recommended, generally 0.1µF to 1µF to ensure plenty of gate drive for the internal switches and a consistently low RDSON. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended because of the stable characteristics over temperature and voltage. Application Schematic VIN VIN CB Cin 2.2µF/50V Cboot L1 100nF 10µH 5V, 0.6A SW SHDN LMR14006Y GND D1 Cout 10µF R1 54.9k FB R2 10k Figure 17. LMR14006 Design Example with 2.1MHz Switching Frequency Other Application Examples Below are the recommended typical output voltage inductor/capacitor combinations for optimized total solution size. 12 P/N Vout(V) R1(kΩ) R2(kΩ) L(μH) Cout(μF) LMR14003/6 Y 5 54.9(1%) 10(1%) 3.3 22 LMR14003/6 Y 12 147(1%) 10(1%) 3.3 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 LMR14003, LMR14006 www.ti.com SNVSA10 – NOVEMBER 2013 Typical Application Circuits VIN VIN CB Cin 2.2µF/50V Cboot L1 100nF 3.3µH 12V, 0.6A SW SHDN LMR14006Y GND D1 R1 147k Cout 10µF FB R2 10k Figure 18. Application Circuit, 12V Output PCB Layout Consideration To reduce problems with conducted noise pick up the ground side of feedback network should be connected directly to the GND pin with its own connection. The feedback network, resistors R1 and R2, should be kept close to the FB pin, and away from the inductor to minimize coupling noise into the feedback pin. The input bypass capacitor CIN must be placed close to the VIN pin. This will reduce copper trace resistance which effects input voltage ripple of the IC. The inductor L1 should be placed close to the SW pin to reduce magnetic and electrostatic noise. The output capacitor, COUT should be placed close to the junction of L1 and the diode D1. The L1, D1, and COUT trace should be as short as possible to reduce conducted and radiated noise and increase overall efficiency. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the system ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the system ground plane. For more detail on switching power supply layout considerations see Application Note AN-1149. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMR14003 LMR14006 13 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMR14006XDDCR ACTIVE SOT DDC 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B02X LMR14006XDDCT ACTIVE SOT DDC 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B02X LMR14006YDDCR ACTIVE SOT DDC 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B02Y LMR14006YDDCT ACTIVE SOT DDC 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B02Y (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMR14006XDDCR SOT DDC 6 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMR14006XDDCT SOT DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMR14006YDDCR SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMR14006YDDCT SOT DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR14006XDDCR SOT DDC 6 3000 210.0 185.0 35.0 LMR14006XDDCT SOT DDC 6 250 210.0 185.0 35.0 LMR14006YDDCR SOT DDC 6 3000 210.0 185.0 35.0 LMR14006YDDCT SOT DDC 6 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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