LT6554 650MHz Gain of 1 Triple Video Buffer U FEATURES DESCRIPTIO ■ The LT®6554 is a high-speed triple video buffer with an internally fixed gain of 1. The individual buffers are optimized for performance with a 1k load and feature a 2VP–P full signal bandwidth of 400MHz, making them ideal for driving very high-resolution video signals. Separate power supply pins for each amplifier boost channel separation to 90dB, allowing the LT6554 to excel in many highspeed applications. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 650MHz –3dB Small Signal Bandwidth 400MHz –3dB 2VP-P Large Signal Bandwidth 100MHz ±0.1dB Bandwidth High Slew Rate: 2500V/µs Fixed Gain of 1 Requires No External Resistors 90dB Channel Separation at 10MHz 60dB Channel Separation at 100MHz –82dBc 2nd Harmonic Distortion at 10MHz, 2VP-P –96dBc 3rd Harmonic Distortion at 10MHz, 2VP-P Low Supply Current: 8mA per Amplifier 6ns 0.1% Settling Time for 2V Step TTL Compatible Enable: ISS ≤ 100µA When Disabled Differential Gain of 0.022%, Differential Phase of 0.006° Wide Supply Range: ±2.25V (4.5V) to ±6V (12V) Available in 16-Lead SSOP Package U APPLICATIO S ■ ■ ■ While the performance of the LT6554 is optimized for dual supply operation, it can also be used on a single supply as low as 4.5V. Using dual 5V supplies, each amplifier draws only 8mA. When disabled, the amplifiers draw less than 100µA and the outputs become high impedance. Furthermore, the amplifiers are capable of turning on in less than 50ns, making them suitable for multiplexing and portable applications. The LT6554 is manufactured on Linear Technology’s proprietary low voltage complementary bipolar process and is available in the 16-lead SSOP package that fits in the same PCB area as an SO-8 package. RGB Buffers A/D Drivers LCD Projectors , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U TYPICAL APPLICATIO Triple Video Buffer and A/D Driver 5V 1 2 16 LT6554 Large Signal Transient Response 15 1.5 + 14 – 1k 480Ω 4 13 480Ω – GIN 5 6 – BIN –5V 7 0.5 –5V 12 + 480Ω 11 1k 5V 0 –0.5 –1.0 10 –1.5 + 1k 8 VOUT = 2VP–P VS = ±5V 1.0 RL = 1k TA = 25°C OUTPUT (V) RIN 3 9 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) –5V 6554 TA01b 6554 TA01a 6554fa 1 LT6554 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Total Supply Voltage (V+ to V–) ............................ 13.2V Input Current (Note 2) ........................................ ±10mA Output Current (Continuous) ............................. ±70mA EN to DGND Voltage (Note 2) ................................. 5.5V Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) ... –40°C to 85°C Specified Temperature Range (Note 5) .... –40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Junction Temperature ........................................... 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW EN 1 16 V + DGND 2 15 V + INR 3 AGND 4 ING 5 AGND 6 INB 7 V– 8 G = +1 LT6554CGN LT6554IGN 14 OUTR 13 V – G = +1 12 OUTG GN PART MARKING 11 V + G = +1 10 OUTB 9 V– 6554 6554I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 135°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 1k, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND = 0V. SYMBOL PARAMETER CONDITIONS VOS Offset Voltage VIN = 0V, VOS = VOUT MIN TYP MAX UNITS 11 ±35 ±70 mV mV –17 ±50 ● ● IIN Input Current en Output Noise Voltage f = 100kHz 20 nV√Hz in Input Noise Current f = 100kHz 3.5 pA√Hz RIN Input Resistance VIN = ±1V 400 kΩ CIN Input Capacitance f = 100kHz 1 pF PSRR Power Supply Rejection Ratio VS (Total) = 4.5V to 12V (Note 6) ● 65 dB IPSRR Input Current Power Supply Rejection VS (Total) = 4.5V to 12V (Note 6) ● AV ERR Gain Error VOUT = ±2V ● AV MATCH Gain Matching Any One Channel to Another VOUT Maximum Output Voltage Swing ● IS Supply Current, Per Amplifier IEN ● 150 51 µA 1 ±5 µA/V –2.5 –0.6 0 % ±0.03 % ±3.75 ±3.85 V RL = ∞ RL = ∞ ● Supply Current, Disabled, Total VEN = 4V VEN = Open ● ● Enable Pin Current VEN = 0.4V VEN = V+ ● ● –200 ● ±50 ±105 mA 1700 2500 V/µs ISC Output Short-Circuit Current RL = 0Ω, VIN = ±2V SR Slew Rate 4VP-P Output Step (Note 9) 8 10 13 mA mA 22 0.5 100 100 µA µA –95 0.5 50 µA µA –3dB BW Small Signal –3dB Bandwidth VOUT = 200mVP-P 650 MHz 0.1dB BW Gain Flatness ±0.1dB Bandwidth VOUT = 200mVP-P 100 MHz 6554fa 2 LT6554 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 1k, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND = 0V. SYMBOL PARAMETER CONDITIONS MIN TYP LSBW Large Signal Bandwidth VOUT = 2VP-P (Note 7) VOUT = 4VP-P (Note 7) 270 400 200 MHz MHz All-Hostile Crosstalk f = 10MHz, VOUT = 2VP-P f = 100MHz, VOUT = 2VP-P –90 –60 dB dB tS Settling Time 0.1% of VFINAL, VSTEP = 2V 6 ns tR, tF Small-Signal Rise and Fall Time 10% to 90%, VOUT = 200mVP-P 550 ps dG Differential Gain (Note 8) 0.022 % dP Differential Phase (Note 8) 0.006 Deg HD2 2nd Harmonic Distortion f = 10MHz, VOUT = 2VP-P –82 dBc HD3 3rd Harmonic Distortion f = 10MHz, VOUT = 2VP-P –96 dBc Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This parameter is guaranteed to meet specified performance through design and characterization. It is not production tested. Note 3: As long as output current and junction temperature are kept below the Absolute Maximum Ratings, no damage to the part will occur. Depending on the supply voltage, a heat sink may be required. Note 4: The LT6554C is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 5: The LT6554C is guaranteed to meet specified performance from 0°C to 70°C. The LT6554C is designed, characterized and expected to meet specified performance from –40°C and 85°C but is not tested or QA sampled at these temperatures. The LT6554I is guaranteed to meet specified performance from –40°C to 85°C. MAX UNITS Note 6: The two supply voltage settings for power supply rejection are shifted from the typical ±VS points for ease of testing. The first measurement is taken at V+ = 3V, V– = –1.5V to provide the required 3V headroom for the enable circuitry to function with EN, DGND, AGND and all inputs connected to 0V. The second measurement is taken at V+ = 8V, V– = –4V. Note 7: Large signal bandwidth is calculated from the slew rate: LSBW = SR/(π • VP-P) Note 8: Differential gain and phase are measured using a Tektronix TSG120YC/NTSC signal generator and a Tektronix 1780R video measurement set. The resolution of this equipment is better than 0.05% and 0.05°. Nine identical amplifier stages were cascaded giving an effective resolution of better than 0.0056% and 0.0056°. Note 9: Slew rate is 100% production tested on the G channel. Slew rate of the R and B channels is guaranteed through design and characterization. 6554fa 3 LT6554 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current per Amplifier vs Temperature SUPPLY CURRENT (mA) VEN = 0V 8 VEN = 0.4V 6 V– = –V+ VEN, VDGND, VIN = 0V 10 TA = 25°C 4 2 8 6 4 0 5 25 45 65 85 105 125 TEMPERATURE (°C) 1 0 2 Input Bias Current vs Input Voltage 0 VS = ±5V VIN = 0V TYPICAL PART 0 VS = ±5V 5.0 2.5 0 0 EN PIN CURRENT (µA) 7.5 TA = 125°C –20 4.0 VS = ±5V VDGND = 0V –20 10.0 3.5 1.0 1.5 2.0 2.5 3.0 EN PIN VOLTAGE (V) 0.5 EN Pin Current vs EN Pin Voltage 20 INPUT BIAS CURRENT (µA) OFFSET VOLTAGE (mV) 4 6554 G03 TA = 25°C TA = –55°C –40 –40 TA = 125°C –60 TA = –55°C –80 TA = 25°C –100 –120 –2.5 –60 –2.5 5 25 45 65 85 105 125 TEMPERATURE (°C) –1.5 0.5 1.5 –0.5 INPUT VOLTAGE (V) 6554 G04 0 5 VS = ±5V 4 RL = 1k 3 –1 –2 TA = –55°C –3 OUTPUT VOLTAGE (V) 0 5 4 Output Voltage Swing vs ILOAD (Output Low) 0 VS = ±5V VIN = 4V 4 1 3 2 EN PIN VOLTAGE (V) 6554 G06 Output Voltage Swing vs ILOAD (Output High) 5 TA = 25°C 1 6554 G05 Output Voltage vs Input Voltage 2 –140 2.5 VS = ±5V VIN = –4V –1 TA = –55°C 3 TA = 25°C 2 TA = 125°C 1 OUTPUT VOLTAGE (V) –5.0 –55 –35 –15 OUTPUT VOLTAGE (V) 6 6554 G02 Offset Voltage vs Temperature 12.5 TA = 125°C 0 3 4 5 6 7 8 9 10 11 12 TOTAL SUPPLY VOLTAGE (V) 6554 G01 15.0 TA = 25°C 8 2 2 0 –55 –35 –15 VS = ±5V VDGND = 0V VIN = 0V TA = –55°C 10 SUPPLY CURRENT (mA) 10 12 12 VS = ±5V RL = ∞ VIN = 0V SUPPLY CURRENT (mA) 12 Supply Current per Amplifier vs EN Pin Voltage Supply Current per Amplifier vs Supply Voltage TA = 25°C –2 TA = 125°C –3 TA = –55°C –4 –4 TA = 125°C –5 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 INPUT VOLTAGE (V) 6554 G07 0 –5 0 10 20 30 40 50 60 70 80 90 100 SOURCE CURRENT (mA) 6554 G08 0 10 20 30 40 50 60 70 80 90 100 SINK CURRENT (mA) 6554 G09 6554fa 4 LT6554 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Noise Spectral Density Input Impedance vs Frequency 1000 VS = ±5V TA = 25°C in 10 VS = ±5V VIN = 0V TA = 25°C 10 1 0.001 0.01 0.1 1 FREQUENCY (kHz) 10 0.1 0.01 100 0.1 1 10 FREQUENCY (MHz) 100 50 VS = ±5V TA = 25°C ±PSRR +PSRR –PSRR 40 30 20 VOUT = 2VP-P VOUT = 4VP-P –3 0 –5 – 0.4 1000 B-CHANNEL – 0.2 – 0.3 100 10 FREQUENCY (MHz) G-CHANNEL – 0.1 –4 1 R-CHANNEL – 0.5 0.1 1 10 100 FREQUENCY (MHz) Frequency Response with Capacitive Loads 2 CL = 3.3pF DISTORTION (dBc) CL = 6.8pF 0 CL = 1.5pF –2 WORST ADJACENT 0.1 1 10 100 FREQUENCY (MHz) –40 –50 –60 –70 HD2 –80 HD3 –100 1000 6554 G15 Output Impedance vs Frequency VS = ±5V RL = 1k TA = 25°C 10000 –90 –4 –6 0.1 – 80 100000 VS = ±5V –10 V OUT = 2VP-P –20 RL = 1k T = 25°C –30 A CL = 12pF 4 ALLHOSTILE – 60 Harmonic Distortion vs Frequency CL = 9pF 6 – 40 – 120 1000 0 12 100 VS = ±5V VOUT = 2VP-P RL = 1k TA = 25°C 6554 G14 6554 G13 VS = ±5V 10 VOUT = 200mVP-P RL = 1k 8 TA = 25°C 10 – 100 OUTPUT IMPEDANCE (Ω) –2 – 20 AMPLITUDE (dB) AMPLITUDE (dB) –1 0 VS = ±5V 0.4 VOUT = 200mVP-P RL = 1k 0.3 C = 1.5pF L 0.2 TA = 25°C TYPICAL PART 0.1 VOUT = 200mVP-P 0 0.1 1 FREQUENCY (MHz) Crosstalk vs Frequency 0.5 VS = ±5V 2 RL = 1k CL = 1.5pF 1 TA = 25°C 0.01 6554 G12 Gain Flatness vs Frequency Frequency Response 3 –6 0.1 0 0.001 1000 6554 G11 6554 G10 AMPLITUDE (dB) 60 10 1 AMPLITUDE (dB) 70 REJECTION RATIO (dB) en 100 PSRR vs Frequency 100 INPUT IMPEDANCE (kΩ) INPUT NOISE (nV/√Hz OR pA/√Hz) 1000 DISABLED VEN = 4V 1000 100 10 ENABLED VEN = 0.4V 1 –110 1 100 10 FREQUENCY (MHz) 1000 6554 G16 –120 0.01 0.1 1 10 FREQUENCY (MHz) 100 6554 G17 0.1 0.01 0.1 1 10 100 FREQUENCY (MHz) 1000 6554 G18 6554fa 5 LT6554 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum Capacitive Load vs Output Series Resistor 0.15 30 0.9 VIN = 700mVP–P 0.8 VS = ±5V R = 1k 0.7 L TA = 25°C 0.6 VIN = 100mVP–P VS = ±5V 0.10 RL = 1k TA = 25°C VOUT = 2VP–P VS = ±5V RL = 1k TA = 25°C 25 20 15 AC PEAKING >2dB 10 OUTPUT (V) 0.05 OUTPUT (V) OUTPUT SERIES RESISTANCE (Ω) 35 Video Amplitude Transient Response Small Signal Transient Response 0 –0.05 5 –0.10 0 –0.15 0.5 0.4 0.3 0.2 0.1 0 1 10 100 CAPACITIVE LOAD (pF) 1000 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6554 G25 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) 6554 G20 6554 G19 Large Signal Transient Response Large Signal Transient Response 1.5 4 VIN = 2VP–P VS = ±5V 1.0 RL = 1k TA = 25°C VIN = 5VP–P VS = ±5V RL = 1k TA = 25°C 3 2 OUTPUT (V) 0.5 OUTPUT (V) –0.1 0 –0.5 1 0 –1 –2 –1.0 –1.5 –3 0 2 4 6 –4 8 10 12 14 16 18 20 TIME (ns) 0 2 4 6554 G21 Gain Error Matching Distribution 40 VS = ±5V VOUT = ±2V RL = 1k TA = 25°C 35 PERCENT OF UNITS (%) PERCENT OF UNITS (%) 30 25 20 15 10 5 0 –1.1 8 10 12 14 16 18 20 TIME (ns) 6554 G22 Gain Error Distribution 35 6 30 VS = ±5V VOUT = ±2V RL = 1k TA = 25°C 25 20 15 10 5 –0.1 –0.9 –0.5 –0.3 –0.7 GAIN ERROR–INDIVIDUAL CHANNEL (%) 6554 G23 0 –0.10 0.10 0.02 0.06 –0.02 –0.06 GAIN ERROR BETWEEN CHANNELS (%) 6554 G24 6554fa 6 LT6554 U U U PI FU CTIO S EN (Pin 1): Enable Control Pin. An internal pull-up resistor of 46k defines the pin’s impedance and will turn the part off if the pin is unconnected. When the pin is pulled low, the part is enabled. DGND (Pin 2): Digital Ground Reference for Enable Pin. This pin is normally connected to ground. INR (Pin 3): Red Channel Input. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. AGND (Pin 4): Analog Ground for Isolation Between Red and Green Channel Inputs. The AGND pins have ESD protection and therefore should not be connected to potentials outside the power supply range. ING (Pin 5): Green Channel Input. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. AGND (Pin 6): Analog Ground for Isolation Between Green and Blue Channel Inputs. The AGND pins have ESD protection and therefore should not be connected to potentials outside the power supply range. INB (Pin 7): Blue Channel Input. This pin has a nominal impedance of 400kΩ and does not have any internal termination resistor. V – (Pin 8): Negative Supply Voltage. V – pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. V – (Pin 9): Negative Supply Voltage for Blue Channel Output Stage. V – pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUTB (Pin 10): Blue Channel Output. It is the buffered output of the blue channel input. V + (Pin 11): Positive Supply Voltage for Blue and Green Channel Output Stages. V+ pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUTG (Pin 12): Green Channel Output. It is the buffered output of the green channel input. V – (Pin 13): Negative Supply Voltage for Green and Red Channel Output Stages. V – pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. OUTR (Pin 14): Red Channel Output. It is the buffered output of the red channel input. V + (Pin 15): Positive Supply Voltage for Red Channel Output Stage. V+ pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. V + (Pin 16): Positive Supply Voltage. V+ pins are not internally connected to each other, and must all be connected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. 6554fa 7 LT6554 U W U U APPLICATIO S I FOR ATIO Power Supplies The LT6554 is optimized for ±5V supplies but can be operated on as little as ±2.25V or a single 4.5V supply and as much as ±6V or a single 12V supply. Internally, each supply is independent to improve channel isolation. Do not leave any supply pins disconnected! Enable/Shutdown The LT6554 has a TTL compatible shutdown mode controlled by the EN pin and referenced to the DGND pin. If the amplifier will be enabled at all times, the EN pin can be connected directly to DGND. If the enable function is desired, either driving the pin above 2V or allowing the internal 46k pull-up resistor to pull the EN pin to the top rail will disable the amplifier. When disabled, the output will become very high impedance. Supply current into the amplifier in the disabled state will be primarily through V+ and approximately equal to (V+ – VEN)/46k. It is important that the two following constraints on the DGND pin and the EN pin are always followed: V+ – VDGND ≥ 3V VEN – VDGND ≤ 5.5V Split supplies of ±3V to ±5.5V will satisfy these requirements with DGND connected to 0V. In single supply applications above 5.5V, an additional resistor may be needed from the EN pin to DGND if the pin is ever allowed to float. For example, on a 12V single supply, a 33k resistor to ground would protect the pin from floating too high while still allowing the internal pull-up resistor to disable the part. On dual ±2.25V supplies, connecting the EN and DGND pins to V– is the easiest way of ensuring that V+ – VDGND is more than 3V. The DGND pin should not be pulled above the EN pin since doing so will turn on an ESD protection diode. If the EN pin voltage is forced a diode drop below the DGND pin, current should be limited to 10mA or less. The enable/disable times of the LT6554 are fast when driven with a logic input. Turn on (from 50% EN input to 50% output) typically occurs in less than 50ns. Turn off is slower, but is nonetheless below 300ns. Input Considerations The LT6554 input voltage range is from V– + 1V to V+ – 1V and is therefore larger than the output swing. The inputs can be driven beyond the point at which the output clips so long as input currents are limited to below ±10mA. Layout and Grounding It is imperative that care is taken in PCB layout in order to utilize the very high speed and very low crosstalk of the LT6554. Separate power and ground planes are highly recommended and trace lengths should be kept as short as possible. If input traces must be run over a distance of several centimeters, they should use a controlled impedance with either series or shunt terminations (nominally 50Ω or 75Ω) to maintain signal fidelity. Care should be taken to minimize capacitance on the LT6554’s output traces by increasing spacing between traces and adjacent metal and by eliminating metal planes in underlying layers. To drive cable or traces longer than several centimeters, using the LT6553 with its fixed gain of +2 in conjunction with series and load termination resistors may provide better results. A plot of LT6554 performance driving a 1k load with various trace lengths is shown in Figure 1. All data is from a 4-layer board with 2oz copper, 18mil of board layer thickness to the ground plane, a trace width of 12mils and spacing to adjacent metal of 18mils. The 0.2cm output trace places the 1k resistor as close to the part as possible, while the other curves show the load resistor consecutively further away. The worst case, 4cm, trace has almost 10pF of parasitic capacitance. In order to counteract any peaking in the frequency response from driving a capacitive load, a series resistance can be inserted in the line at the output of the part to flatten the response. Figure 2 shows the frequency response with the same 4cm trace from Figure 1, now with a 10Ω series resistor inserted near the output pin of the LT6554. Note that using a 10Ω series resistor with a 1k load only decreases the output amplitude by 0.1dB or 1% and has a minimal effect on the bandwidth of the system. See the graph labeled “Maximum Capacitive Load vs Output Series Resistor” in the Typical Performance Characteristics section for more information. 6554fa 8 LT6554 U W U U APPLICATIO S I FOR ATIO 6 AMPLITUDE (dB) 4 VS = ±5V VOUT = 200mVP-P RL = 1k TA = 25°C supply. The smallest value capacitors should be placed closest to the package. To maintain the LT6554’s channel isolation, it is beneficial to shield parallel input and output traces using a ground plane or power supply traces. Vias between topside and backside metal are recommended to maintain a low inductance ground, especially between closely spaced signal traces. 4cm TRACE 2 2cm TRACE 0 0.2cm TRACE –2 –4 –6 Single Supply Operation 0.1 1 10 100 FREQUENCY (MHz) 1000 6554 F01 Figure 1. Response vs Output Trace Length 6 AMPLITUDE (dB) 4 VS = ±5V VOUT = 200mVP-P RL = 1k TA = 25°C 4cm TRACE The only additional power dissipation in the single supply configuration is through the resistor bias string at the input and through any load resistance at the output. In many cases, the output can be used to directly drive other single supply devices without additional coupling and without any resistive load. 2 0 4cm TRACE RS, OUT = 10Ω –2 –4 –6 0.1 1 10 100 FREQUENCY (MHz) Figure 3 illustrates how to use the LT6554 with a single supply ranging from 4.5V to 12V. Since the output range is comparable to the input range, the DC bias point at the input can be set anywhere between the supplies that will prevent the AC-coupled signal from running into the output range limits. As shown, the DC input level is midsupply. 1000 6554 F02 Figure 2. Response vs Series Output Resistance While the AGND pins on the LT6554 are not connected to the amplifier circuitry, tying them to ground or another “quiet” node significantly increases channel isolation and is always recommended. The AGND pins do have ESD protection and therefore should not be connected to potentials outside the power supply range. Low ESL/ESR bypass capacitors should be placed as close to the positive and negative supply pins as possible. One 4700pF ceramic capacitor is recommended for both V+ and V–. Additional 470pF ceramic capacitors with minimal trace length on each supply pin will further improve AC and transient response as well as channel isolation. For high current drive and large-signal transient applications, additional 1µF to 10µF tantalums should be added on each ESD Protection The LT6554 has reverse-biased ESD protection diodes on all pins. If any pins are forced a diode drop above the positive supply or a diode drop below the negative supply, large currents may flow through these diodes. If the current is kept below 10mA, no damage to the device will occur. 4.5V TO 12V 5k 22µF IN VIN 5k AGND V+ 1/3 LT6554 OUT V– 6554 F03 Figure 3. Single Supply Configuration, One Channel Shown 6554fa 9 LT6554 U TYPICAL APPLICATIO RGB Buffer Demo Board combined input and output of the other channels. This trace can be used for calibrating the effects of electrical delay and impedance mismatching and is not necessary in an end-user application. Jumpers and additional connectors are also included to allow for evaluation of the enable feature and single supply operation. The DC794 Demo Board illustrates optimal routing, bypassing and termination using the LT6554 as an RGB video buffer. The schematic is shown in Figure 4. All inputs and outputs are routed to have a characteristic impedance of 75Ω. The 75Ω input shunt and output series terminations are connected as close to the part as possible. While the 75Ω back termination resistors at the outputs of the LT6554 minimize signal reflections in the output traces and isolate the part from any capacitive loading in those traces, they also contribute to gain error if the output is not terminated with high impedance. For example, if the output is terminated with a 1k load, the 75Ω back termination will cause a 7% gain error. Decreasing the value of the back termination resistors will decrease the signal attenuation but may compromise the AC response. However, connecting the LT6554 outputs to the output traces on the DC794 board without some series resistance is not recommended; 10Ω to 20Ω is generally sufficient. RGB Video Selector/Cable Driver A video multiplexer can be implemented using the EN pins of parallel LT6554s as shown in Figure 5. In this application, the corresponding outputs are connected together and one LT6554 is switched on while the other is switched off. A fast inverter provides a complementary signal to ensure that only one set of R, G and B channels is buffered at any time. Since the output impedance of a disabled LT6554 is very high, adding additional channels will not resistively load an enabled output. However, since the disabled LT6554 has around 6pF of capacitance, it may be desirable to resistively isolate the outputs of each channel to maintain flat frequency response as shown in the graph labeled “Maximum Capacitive Load vs Output Series Resistor” in the Typical Performance Characteristics section. A fourth signal trace is provided at the bottom of the DC794 demo board with dimensions identical to the E1 EN J1 50Ω BNC 1 EN JP1 CONTROL 1 2 ENABLE 5 4 3 2 V+ 3 EXT C1 4700pF JP2 DGND 1 2 3 AGND FLOAT INR ING INB 5 4 3 2 BNC × 3 1 E2 DGND 1 2 Z = 75 3 4 J5 5 4 3 2 1 Z = 75 5 6 J6 5 4 3 2 Z = 75 1 7 R4 75Ω J7 R5 75Ω R6 75Ω 8 LT6554 EN V+ 16 DGND V+ 15 OUTR INR V– AGND OUTG ING + V AGND OUTB INB R1 75Ω 14 13 R2 75Ω 12 11 R3 75Ω 10 C2 470pF C3 4700pF V+ C4 J2 10µF, 16V BANANA 1210 JACK BNC x3 1 Z = 75 Z = 75 OUTG J10 5 4 3 2 OUTB J11 5 4 3 2 1 Z = 75 1 9 V– V– OUTR J9 5 4 3 2 V– E3 AGND SINGLE 1 AGND CAL 5 4 3 2 V– J3 BANANA JACK 1 DUAL 2 3 JP3 SUPPLY C5 470pF C6 1000pF C7 470pF C8 4700pF J4 BANANA JACK C9 10µF, 16V 1210 Z = 75 J8 BNC ALL BNC: CANARE BCJ-BPLH Figure 4. DC794 Demo Board Schematic 1 J12 BNC 5 4 3 2 CAL 6554 F04 6554fa 10 LT6554 W W SI PLIFIED SCHE ATIC V+ V+ TO OTHER AMPLIFIERS BIAS V+ 46k 150Ω 1k EN 480Ω IN OUT V– DGND V– 6554 SS V– U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 TYP RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .053 – .068 (1.351 – 1.727) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 0502 6554fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LT6554 U TYPICAL APPLICATIO 3.3V NC7SZ14 1 LT6554 2 3 R1 15 ×1 4 5 G1 7 75Ω 75Ω 75Ω 14 13 ×1 6 B1 16 12 11 ×1 8 10 9 ROUT GOUT 1 SEL LT6554 3 ×1 5 ×1 7 75Ω 75Ω 75Ω 12 11 6 B0 14 13 4 G0 BOUT 15 2 R0 16 ×1 8 10 9 NOTE: POWER SUPPLY BYPASS CAPACITORS NOT SHOWN FOR CLARITY –3.3V 6554 F05 Figure 5. RGB Video Selector and A/D Driver RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1259/LT1260 Dual/Triple 130MHz Current Feedback Amplifiers Shutdown, Operates to ±15V LT1395/LT1396/LT1397 Single/Dual/Quad 400MHz Current Feedback Amplifiers 800V/µs Slew Rate LT1398/LT1399 Dual/Triple 300MHz Current Feedback Amplifiers 0.1dB Gain Flatness to 150MHz, Shutdown LT1675/LT1675-1 250MHz, Triple and Single RGB Multiplexer with Current Feedback Amplifiers 100MHz Pixel Switching, –3dB Bandwidth: 250MHz, 1100V/µs Slew Rate LT1809/LT1810 Single/Dual, 180MHz, Rail-to-Rail Input and Output Amplifiers 350V/µs Slew Rate, Shutdown, Low Distortion –90dBc at 5MHz LT6550/LT6551 3.3V Triple and Quad Video Buffers 110MHz Gain of 2 Buffers in MSOP Package LT6553 650MHz, Gain of 2, Triple Video Amplifier Same Pinout as LT6554 6554fa 12 Linear Technology Corporation LT/TP 0305 1K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004