LTC1287 3V Single Chip 12-Bit Data Acquisition System U FEATURES ■ ■ ■ ■ DESCRIPTIO Single Supply 3.3V Operation Built-In Sample-and-Hold Direct 3-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports 30kHz Maximum Throughput Rate U KEY SPECIFICATIO S ■ ■ ■ ■ The serial I/O is designed to communicate without external hardware to most MPU serial ports and all MPU parallel I/O ports allowing data to be transmitted and received over three wires. The low voltage operating capability and the low power consumption of this device make it ideally suited for battery applications. Given the ease of use, small package size and the minimum number of interconnects for I/O, the LTC1287 can be used for remote sensing applications. Minimum Guaranteed Supply Voltage: 2.7V Resolution: 12 Bits Fast Conversion Time: 24µs Max Over Temp. Low Supply Current: 1.0mA U APPLICATIO S ■ ■ ■ The LTC®1287 is a 3V data acquisition component which contains a serial I/O successive approximation A/D converter. The device specifications are guaranteed at a supply voltage of 2.7V. It uses LTCMOSTM switched capacitor technology to perform a 12-bit unipolar, A/D conversion. The differential input has an on-chip sampleand-hold on the (+) input. Battery-Powered Instruments Data Logger Data Acquisition Modules , LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOS is a trademark of Linear Technology Corporation U TYPICAL APPLICATIO 3V Differential Input Data Acquisition System 22µF TANTALUM + INL with VREF = 1.2V + 3V LITHIUM 10k CLK +IN 0.5 LTC1287 – –IN DOUT GND VREF 22µF TANTALUM + LT1004-1.2 ERROR (LSB) DIFFERENTIAL INPUTS COMMON MODE RANGE 0V TO VCC* 1.0 VCC CS 0 –0.5 TO AND FROM MPU * FOR OVERVOLTAGE PROTECTION, LIMIT THE INPUT CURRENT TO 15mA PER PIN OR CLAMP THE INPUTS TO VCC AND GND WITH 1N4148 DIODES. CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED CHANNEL OR OTHER CHANNEL IS OVERVOLTAGED (VIN < GND OR VIN > VCC). SEE SECTION ON OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION. –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1287 TA02 1287 TA01 1287fa 1 LTC1287 U RATI GS U W W W AXI U W (Notes 1 and 2) U ABSOLUTE PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW Supply Voltage (VCC) to GND .................................. 12V Voltage Analog and Reference Inputs .... –0.3V to VCC + 0.3V Digital Inputs ........................................ –0.3V to 12V Digital Outputs .......................... –0.3V to VCC + 0.3V Power Dissipation ............................................. 500mW Operating Temperature Range .................... 0°C to 70°C Storage Temperature Range ................. –65°C to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°C CS 1 8 VCC +IN 2 7 CLK –IN 3 6 DOUT GND 4 5 VREF LTC1287BCN8 LTC1287CCN8 N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 100°C, θJA = 130°C/W (N) J8 PACKAGE 8-LEAD CERAMIC DIP TJMAX = 150°C, θJA = 100°C/W (J) LTC1287BCJ8 LTC1287CCJ8 OBSOLETE PACKAGE Consider N8 Package for Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges. U U W CO VERTER A D ULTIPLEXER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1287B PARAMETER CONDITIONS Offset Error VCC = 2.7V (Note 4) ● Linearity Error (INL) VCC = 2.7V (Notes 4 & 5) Gain Error VCC = 2.7V (Note 4) Minimum Resolution for Which No Missing Codes are Guaranteed MIN TYP MAX LTC1287C MIN TYP MAX UNITS ±3.0 ±3.0 LSB ● ±0.5 ± 0.5 LSB ● ±0.5 ±1.0 LSB ● 12 12 Bits – 0.05V to VCC + 0.05V Analog and REF Input Range (Note 7) On Channel Leakage Current (Note 8) On Channel = 3V Off Channel = 0V ● ±1 ±1 µA On Channel = 0V Off Channel = 3V ● ±1 ±1 µA On Channel = 3V Off Channel = 0V ● ±1 ±1 µA On Channel = 0V Off Channel = 3V ● ±1 ±1 µA Off Channel Leakage Current (Note 8) V AC CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1287B/LTC1287C MIN TYP MAX SYMBOL PARAMETER CONDITIONS fCLK Clock Frequency (Note 6) tSMPL Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles tCONV Conversion Time See Operating Sequence 12 CLK Cycles tCYC Total Cycle Time See Operating Sequence (Note 6) tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits ● tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● 80 160 ns ten Delay Time, CLK↓ to DOUT Enabled See Test Circuits ● 130 250 ns (Note 9) 0.5 14 CLK+5.0µs UNITS MHz Cycles 250 450 ns 1287fa 2 LTC1287 AC CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1287B/LTC1287C MIN TYP MAX SYMBOL PARAMETER CONDITIONS UNITS thDO Time Output Data Remains Valid After CLK↓ tf DOUT Fall Time See Test Circuits ● 40 100 ns tr DOUT Rise Time See Test Circuits ● 40 100 ns tWHCLK CLK High Time VCC = 3V (Note 6) 600 ns tWLCLK CLK Low Time VCC = 3V (Note 6) 800 ns tsuCS Setup Time, CS↓ Before CLK↑ VCC = 3V (Note 6) 100 ns tWHCS CS High Time Between Data Transfer Cycles VCC = 3V (Note 6) 5.0 µs tWLCS CS Low Time During Data Transfer VCC = 3V (Note 6) 14 CLK Cycles CIN Input Capacitance Analog Inputs On Channel Analog Inputs Off Channel Digital Inputs 50 ns 100 5 5 pF pF pF U DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1287B/LTC1287C MIN TYP MAX SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VCC = 3.6V ● VIL Low Level Input Voltage VCC = 3.0V ● 0.45 V IIH High Level Input Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● –2.5 µA VOH High Level Output Voltage VCC = 3.0V, IO = 20µA IO = 400µA ● VCC = 3.0V, IO = 20µA IO = 400µA ● ● ● VOL Low Level Output Voltage 2.1 2.7 UNITS V 2.90 2.85 0.05 0.10 V V 0.3 V V 3 –3 µA µA IOZ High Z Output Leakage VOUT = VCC, CS High VOUT = 0V, CS High ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VCC 9 mA ICC Positive Supply Current CS High ● 1.5 5 mA IREF Reference Current VREF = 2.5V ● 10 50 µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground (unless otherwise noted). Note 3: VCC = 3V, VREF = 2.5V, CLK = 500kHz unless otherwise specified. Note 4: One LSB is equal to VREF divided by 4096. For example, when VREF = 2.5V, 1LSB = 2.5V/4096 = 0.61mV. Note 5: Integral nonlinearity error is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Recommended operating conditions. Note 7: Two on-chip diodes are tied to each analog input which will conduct for analog voltages one diode drop below GND or one diode drop above VCC. Be careful during testing at low VCC levels, as high level analog inputs can cause this input diode to conduct, especially at elevated temperature, and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. Note 8: Channel leakage current is measured after the channel selection. Note 9: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it is recommended that fCLK ≥ 30kHz at 85°C and fCLK ≥ 3kHz at 25°C. 1287fa 3 LTC1287 U W TYPICAL PERFOR A CE CHARACTERISTICS 2.8 0.9 1.9 CLK = 500kHz TA = 25°C CLK = 500kHz VCC = 3V 1.8 SUPPLY CURRENT (mA) 2.4 2.2 2.0 1.8 1.6 1.4 1.7 1.6 1.5 1.2 1.4 0.8 1.3 –40 –25 –10 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 0.4 0.3 VOS = 0.125mV 0.2 80 0 95 MAGNITUDE OF OFFSET CHANGE (LSB) VCC = 3V –0.2 0.3 –0.3 0.2 –0.4 0.1 –0.5 0.5 2.5 1.0 1.5 2.0 REFERENCE VOLTAGE (V) 3.0 0 0.5 2.5 1.0 1.5 2.0 REFERENCE VOLTAGE (V) 0.4 0.3 0.2 0.1 Change in Linearity vs Temperature Change in Gain vs Temperature 0.5 DOUT Delay Time vs Temperature 0.5 MAGNITUDE OF GAIN CHANGE (LSB) 0.3 0.2 0.1 0 40 20 0 60 –40 –20 80 AMBIENT TEMPERATURE (°C) 100 LTC1287 G7 0.4 100 LTC1287 G6 LTC1287 G5 LTC1287 G4 VCC = 3V VREF = 2.5V CLK = 500kHz VCC = 3V VREF = 2.5V CLK = 500kHz 0 40 20 0 60 –40 – 20 80 AMBIENT TEMPERATURE (°C) 3.0 350 VCC = 3V VCC = 3V VREF = 2.5V CLK = 500kHz DOUT DELAY TIME FROM CLK↓ (ns) 0 3.0 Change in Offset vs Temperature –0.1 0.4 2.5 1.0 1.5 2.0 REFERENCE VOLTAGE (V) 0.5 0 0.5 VCC = 3V 0.5 LTC1287 G3 Change in Gain vs Reference Voltage CHANGE IN GAIN (LSB = 1/4096 × VREF) CHANGE IN LINEARITY (LSB = 1/4096 × VREF) 0.5 LTC1287 G2 Change in Linearity vs Reference Voltage MAGNITUDE OF LINEARITY CHANGE (LSB) VOS = 0.250mV 0 5 20 35 50 65 TEMPERATURE (°C) LTC1287 G1 0.4 0.7 0.6 0.1 1.0 0 VCC = 3V 0.8 OFFSET (LSB = 1/4096 × VREF) 2.6 SUPPLY CURRENT (mA) Unadjusted Offset Voltage vs Reference Voltage Supply Current vs Temperature Supply Current vs Supply Voltage 0.3 0.2 0.1 0 40 20 0 60 –40 –20 80 AMBIENT TEMPERATURE (°C) 100 LTC1287 G8 300 MSB-FIRST DATA 250 200 LSB-FIRST DATA 150 100 50 0 –40 –20 40 80 20 60 0 AMBIENT TEMPERATURE (°C) 100 LTC1287 G9 1287fa 4 LTC1287 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum Clock Rate vs Source Resistance Maximum Filter Resistor vs Cycle Time Minimum Clock Rate for 0.1LSB Error** 10k VCC = 3V VREF = 2.5V CLK = 500kHz 300 200 +VIN RSOURCE– 100 0 100 +IN –IN 1k 10k RSOURCE – (Ω) VIN 0.25 MAXIMUM RFILTER*** (Ω) 400 VCC = 3V MINIMUM CLK FREQUENCY (MHz) 0.20 0.15 0.10 –50 100k 75 0 25 50 –25 AMBIENT TEMPERATURE (°C) INPUT CHANNEL LEAKAGE CURRENT (nA) S & H ACQUISITION TIME TO 0.02% (µs) VIN RSOURCE+ + – 1 100 1k 100 10 1 100 10 10k RSOURCE+ (Ω) 1000 100 CYCLE TIME (µs) 900 Noise Error vs Reference Voltage 1.0 GUARANTEED 800 700 600 500 400 300 200 100 ON CHANNEL OFF CHANNEL 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE (°C) LTC1287 G13 * MAXIMUM CLK FREQUENCY REPRESENTS THE CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED. 10000 LTC1287 G12 1000 VREF = 2.5V VCC = 3V TA = 25°C 0V TO 2.5V INPUT STEP + – Input Channel Leakage Current vs Temperature Sample-and-Hold Acquisition Time vs Source Resistance 10 CFILTER ≥1µF 1k LTC1287 G11 LTC G10 100 RFILTER 0.05 LTC1287 G14 PEAK-TO-PEAK NOISE ERROR (LSB) MAXIMUM CLK FREQUENCY* (MHz) 500 LTC1287 NOISE = 200µVP-P 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.5 2.0 2.5 1.0 REFERENCE VOLTAGE (V) 3.0 LTC1287 G15 *** MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER = 0Ω IS FIRST DETECTED. ** AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED. U U U PI FU CTIO S CS (Pin 1): Chip Select Input. A logic low on this input enables the LTC1287. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. +IN, –IN (Pin 2,3): Analog Inputs. These inputs must be free of noise with respect to GND. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. GND (Pin 4): Analog Ground GND should be tied directly to an analog ground plane. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 5): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. 1287fa 5 LTC1287 W BLOCK DIAGRA VCC 8 7 INPUT SHIFT REGISTER +IN –IN OUTPUT SHIFT REGISTER 2 ANALOG INPUT MUX 3 SAMPLE AND HOLD 6 CLK DOUT COMP 12-BIT SAR 12-BIT CAPACITIVE DAC 4 5 GND VREF CONTROL AND TIMING 1 CS LTC1287 BD TEST CIRCUITS Voltage Waveforms for DOUT Delay Time, tdDO On and Off Channel Leakage Current 3V CLK ION 0.45V A ON CHANNEL tdDO IOFF 2.1V A DOUT OFF CHANNEL 0.6V LTC1287 TC03 Voltage Waveforms for DOUT Rise and Fall Times, tr, tf POLARITY LTC1287 TC1 Load Circuit for tdis and ten 2.1V DOUT 0.6V TEST POINT tr tf LTC1287 TC04 3V tdis WAVEFORM 2, ten 3k DOUT Voltage Waveforms for tdis tdis WAVEFORM 1 100pF Load Circuit for tdDO, tr and tf 1.5V 2.1V CS LTC1287 TC05 DOUT WAVEFORM 1 (SEE NOTE 1) 90% tdis 3k DOUT TEST POINT DOUT WAVEFORM 2 (SEE NOTE 2) 100pF LTC1287 TC06 LTC1287 TC02 6 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1287fa LTC1287 TEST CIRCUITS Voltage Waveforms for ten CS CLK B11 DOUT 0.6V ten W U U UO APPLICATI LTC1287 TC07 S I FOR ATIO does not require a configuration input word and has no DIN pin. It is permanently configured to have a single differential input and to operate in unipolar mode. A falling CS initiates data transfer. The first CLK pulse enables DOUT. After one null bit, the A/D conversion result is output on the DOUT line with a MSB-first sequence followed by a LSBfirst sequence. With the half duplex serial interface the DOUT data is from the current conversion. This provides easy interface to MSB- or LSB-first serial ports. Bringing CS high resets the LTC1287 for the next data exchange. The LTC1287 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample-and-hold (S/H) 4. Synchronous, half-duplex serial interface 5. Control and timing logic DIGITAL CONSIDERATIONS Serial Interface The LTC1287 communicates with microprocessors and other external circuitry via a synchronous, half-duplex, three-wire serial interface (see Operating Sequence). The clock (CLK) synchronizes the data transfer with each bit being transmitted on the falling CLK edge. The LTC1287 Logic Levels The logic level standards for this supply range have not been well defined. What standards that do exist are not universally accepted. The trip point on the logic inputs of the LTC1287 is 0.28 × VCC. This makes the logic inputs compatible with HC-type levels and processors that are tCYC CS CLK Hi-Z DOUT tSMPL B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 tSMPL tCONV LTC1287 F01 Figure 1. LTC1287 Operating Sequence 1287fa 7 LTC1287 W U U UO APPLICATI S I FOR ATIO specified at 3.3V. The output DOUT is also compatible with the above standards. The following summarizes such levels. VCC – 0.1V VOH (no load) VOL (no load) 0.1V VOH 0.9 × VCC VOL 0.1 × VCC VIH 0.7 × VCC VIL 0.2 × VCC The LTC1287 can be driven with 5V logic even when VCC is at 3.3V. This is due to a unique input protection device that is found on the LTC1287. Microprocessor Interfaces The LTC1287 can interface directly (without external hardware) to most popular microprocessor (MPU) synchronous serial formats. If an MPU without a serial interface is used, then three of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1287. Many of the popular MPUs can operate with 3V supplies. For example the MC68HC11 is an MPU with a serial format (SPI). Likewise parallel MPUs that have the 8051 type architecture are also capable of operating at this voltage range. The code for these processors remains the same and can be found in the LTC1292 data sheet. Sharing the Serial Interface The LTC1287 can share the same two-wire serial interface with other peripheral components or other LTC1287s (Figure 2). In this case, the CS signals decide which LTC1287 is being addressed by the MPU. ANALOG CONSIDERATIONS Grounding The LTC1287 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance use a PC board. The ground pin (Pin 4) should be tied directly to the ground plane with minimum lead length (a low profile socket is fine). Pin 7 (VCC) should be bypassed to the ground plane with a 22µF (minimum value) tantalum with leads as short as possible and as close as possible to the pin. A 0.1µF ceramic disk also should be placed in parallel with the 22µF and again with leads as short as possible and as close to VCC as possible. Figure 3 shows an example of an ideal LTC1287 ground plane design for a two-sided board. Of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. Bypassing For good performance, VCC must be free of noise and ripple. Any changes in the VCC voltage with respect to ground during a conversion cycle can induce errors or noise in the output code. VCC noise and ripple can be kept below 0.5mV by bypassing the VCC pin directly to the analog plane with a minimum of 22µF tantalum capacitor and with leads as short as possible. The lead from the device to the VCC supply also should be kept to a minimum and the VCC supply should have a low output impedance VCC 0.1µF 22µF TANTALUM 2 1 0 OUTPUT PORT SERIAL DATA MPU 2-WIRE SERIAL INTERFACE TO OTHER PERIPHERALS OR LTC1287s 2 2 2 CS LTC1287 2 CS LTC1287 CS LTC1287 1 8 2 7 LTC1287 3 6 4 5 LTC1287 F03 2 CHANNELS 2 CHANNELS 2 CHANNELS LTC1287 F02 Figure 2. Several LTC1287s Sharing One 2-Wire Serial Interface Figure 3. Example Ground Plane for the LTC1287 1287fa 8 LTC1287 U W U UO APPLICATI S I FOR ATIO such as obtained from a voltage regulator (e.g., LT1117). For high frequency bypassing a 0.1µF ceramic disk placed in parallel with the 22µF is recommended. Again the leads should be kept to a minimum. Using a battery to power the LTC1287 will help reduce the amount of bypass capacitance required on the VCC pin. A battery placed close to the device will only require 10µF to adequately bypass the supply pin. Figure 4 shows the effect of poor VCC bypassing. Figure 5 shows the settling of a LT1117 low dropout regulator with a 22µF bypass capacitor. The noise and ripple is kept around 0.5mV. Figure 6 shows the response of a lithium battery with a 10µF bypass capacitor. The noise and ripple is kept below 0.5mV. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1287 have CS 5V/DIV VCC 0.5mV/DIV HORIZONTAL: 20µs/DIV Figure 6. Lithium Battery with 10µF Bypassing on VCC capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. If large source resistances are used or if slow settling op amps drive the inputs, take care to insure the transients caused by the current spikes settle completely before the conversion begins. VERTICAL: 0.5mV/DIV Source Resistance The analog inputs of the LTC1287 look like a 100pF capacitor (CIN) in series with a 1.5k resistor (RON). This value for RON is for VCC = 2.7V. With larger supply voltages RON will be reduced. For example, with VCC = 2.7V and V – = – 2.7V, RON becomes 500Ω. CIN gets switched between (+) and (–) inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constant is short enough to allow the analog inputs to settle completely within the allowed time. HORIZONTAL: 10µs/DIV Figure 4. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors RSOURCE + “+” INPUT LTC1287 VIN + C1 CS 5V/DIV RSOURCE – “–” INPUT VIN – VCC 0.5mV/DIV CS↑ RON = 1.5k tWHCS + 1/2 CLK CIN = 100pF C2 LTC1287 F07 Figure 7. Analog Input Equivalent Circuit HORIZONTAL: 20µs/DIV Figure 5. LT1117 Regulator with 22µF Bypassing on VCC 1287fa 9 LTC1287 W U U UO APPLICATI S I FOR ATIO “+” Input Settling The input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figures 8a, 8b and 8c). The sample period can be as short as tWHCS + 0.5 CLK cycle or as long as tWHCS + 1.5 CLK cycles before a conversion starts. This variability depends on where CS falls relative to CLK. The voltage on the “+” input must settle completely within the sample period. Minimizing RSOURCE+ and C1 will improve the settling time. If large “+” input source resistance must be used, the sample time can be increased by using a slower CLK frequency. With the minimum possible sample time of 6.0µs, RSOURCE+ < 4.0k and C1 < 20pF will provide adequate settle time. “–” Input Settling At the end of the sample phase the input capacitor switches to the “–” input and the conversion starts (see Figures 8a, 8b and 8c). During the conversion, the “+” input voltage is “+” and “–” Input Settling Windows tWHCS CS tSUCS CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 HI-Z B10 B9 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1287 F8a Figure 8a. Setup Time (tSUCS) is Met tWHCS CS CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 B10 B9 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT Figure 8b. Setup Time (tSUCS) is Met LTC1287 F8b 1287fa 10 LTC1287 W U U UO APPLICATI S I FOR ATIO tWHCS CS CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME B11 DOUT B10 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1287 F8c Figure 8c. Setup Time (tSUCS) is Not Met effectively “held” by the sample and hold and will not affect the conversion result. It is critical that the “–” input voltage be free of noise and settle completely during the first CLK cycle of the conversion. Minimizing RSOURCE – and C2 will improve settling time. If large “–” input source resistance must be used the time can be extended by using a slower CLK frequency. At the maximum CLK frequency of 500kHz, RSOURCE – < 200Ω and C2 < 20pF will provide adequate settling. VERTICAL: 5mV/DIV VERTICAL: 5mV/DIV Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settles within the allowed time (see Figures 8a, 8b and 8c). Again the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. For single supply low voltage application the LT1797 and LT1677 can be made to settle well even with the minimum settling windows of 6µs (“+” input) and 2µs (“–” input) which occur at the maximum clock rates (CLK = 500kHz). Figures 9 and 10 show examples of adequate and poor op amp settling. The LT1077, LT1078 or LT1079 can be used here to reduce power consumption. Placing an RC network at the output of the op amps will inprove the settling response and also reduce the broadband noise. HORIZONTAL: 500ns/DIV Figure 9. Adequate Settling of Op Amp Driving Analog Input HORIZONTAL: 20µs/DIV Figure 10. Poor Op Amp Settling Can Cause A/D Errors 1287fa 11 LTC1287 U W U UO APPLICATI S I FOR ATIO RC Input filtering It is possible to filter the inputs with an RC network as shown in Figure 11. For large values of CF (e.g., 1µF) the capacitive input switching currents are averaged into a net DC current. A filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 100pF × VIN/tCYC and is roughly proportional to VIN. When running at the minimum cycle time of 33µs, the input current equals 7.6µA at VIN = 2.5V. Here a filter resistor of 8Ω will cause 0.1LSB of full-scale error. If a large filter resistor must be used, errors can be reduced by increasing the cycle time as shown in the Typical Performance Characteristics curve Maximum Filter Resistor vs Cycle Time. RFILTER IDC VIN – “+” CFILTER Acquisition Time vs Source Resistance). The input voltage is sampled during the tSMPL time as shown in Figure 8. The sampling interval begins at rising edge of CS and continues until the falling edge of the CLK before the conversion begins. On this falling edge the S&H goes into the hold mode and the conversion begins. Differential Input With a differential input the A/D no longer converts a single voltage but converts the difference between two voltages. The voltage on the +IN pin is sampled and held and can be rapidly time varying. The voltage on the –IN pin must remain constant and be free of noise and ripple throughout the conversion time. Otherwise the differencing operation will not be done accurately. The conversion time is 12 CLK cycles. Therefore a change in the –IN input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the –IN input this error would be: LTC1287 “–” LTC1287 F11 Figure 11. RC Input Filtering Input Leakage Current Input leakage currents also can create errors if the source resistance gets too large. For example, the maximum input leakage specification of 1µA (at 85°C) flowing through a source resistance of 1k will cause a voltage drop of 1mV or 1.6LSB with VREF = 2.5V. This error will be much reduced at lower temperatures because leakage drops rapidly (see Typical Performance Characteristics curve Input Channel Leakage Current vs Temperature). SAMPLE-AND-HOLD Single-Ended Input The LTC1287 provides a built-in sample and hold (S&H) function on the +IN input for signals acquired in the single ended mode (–IN pin grounded). The sample and hold allows the LTC1287 to convert rapidly varying signals (see Typical Performance Characteristics curve of S&H Where f(–IN) is the frequency of the –IN input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. Usually VERROR will not be significant. For a 60Hz signal on the –IN input to generate a 0.25LSB error (150µV) with the converter running at CLK = 500kHz, its peak value would have to be 16mV. Rearranging the above equation, the maximum sinusoidal signal that can be digitized to a given accuracy is given as: For 0.25LSB error (150µV) the maximum input sinusoid with a 2.5V peak amplitude that can be digitized is 0.4Hz. Reference Input The voltage on the reference input of the LTC1287 determines the voltage span of the A/D converter. The reference input has transient capacitive switching currents due to the switched capacitor conversion technique (see Figure 12). During each bit test of the 1287fa 12 LTC1287 W U U UO APPLICATI S I FOR ATIO conversion (every CLK cycle) a capacitive current spike will be generated on the reference pin by the A/D. These current spikes settle quickly and do not cause a problem. If slow settling circuitry is used to drive the reference input, take care to insure that transients caused by these current spikes settle completely during each bit test of the conversion. REF+ 14 ROUT VREF LTC1287 EVERY CLK CYCLE RON 8pF – 40pF GND 13 LTC 1287 F12 VERTICAL: 0.5mV/DIV Figure 12. Reference Input Equivalent Circuit HORIZONTAL: 1µs/DIV VERTICAL: 0.5mV/DIV Figure 13. Adequate Reference Settling HORIZONTAL: 10µs/DIV Figures 13 and 14 show examples of both adequate and poor settling. Using a slower CLK will allow more time for the reference to settle. Even at the maximum CLK rate of 500kHz most references and op amps can be made to settle within the 2µs bit time. For example an LT1790 with a 4.7µF bypass capacitor will settle adequately. Reduced Reference Operation The effective resolution of the LTC1287 can be increased by reducing the input span of the converter. The LTC1287 exhibits good linearity over a range of reference voltages (seeTypical Performance Characteristics curves of Change in Linearity vs Reference Voltage). Care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter. Offset and Noise are factors that must be considered when operating at low VREF values. Offset with Reduced VREF The offset of the LTC1287 has a larger effect on the output code when the A/D is operated with a reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The Typical Performance Characteristics curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example a VOS of 0.1mV, which is 0.2LSB with a 2.5V reference becomes 0.4LSB with a 1.25 reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the –IN input to the LTC1287. Noise with Reduced VREF The total input referred noise of the LTC1287 can be reduced to approximately 200µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 2.5V reference input but will become a larger fraction of an LSB as the size of the LSB is reduced. The Typical Performance Characteristics Figure 14. Poor Reference Settling Can Cause A/D Errors 1287fa 13 LTC1287 U W U UO APPLICATI S I FOR ATIO curve of Noise Error vs Reference Voltage shows the LSB contribution of this 200µV of noise. For operation with a 2.5V reference, the 200µV noise is only 0.32LSB peak-to-peak. Here the LTC1287 noise will contribute virtually no uncertainty to the output code. For reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1.25V reference, this 200µV noise is 0.64LSB peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 0.64LSB. Now averaging readings may be necessary. This noise data was taken in a very clean test fixture. Any setup induced noise (noise or ripple on VCC, VREF or VIN) will add to the internal noise. The lower the reference voltage used, the more critical it becomes to have a noise-free setup. Overvoltage Protection Applying signals to the LTC1287’s analog inputs that exceed the positive supply or that go below ground will degrade the accuracy of the A/D and possibly damage the device. For example this condition would occur if a signal is applied to the analog inputs before power is applied to the LTC1287. Another example is the input source operating from different supplies of larger value than the LTC1287. These conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp or current limit the input source. There are two ways to protect the inputs. In Figure 15 diode clamps from the inputs to VCC and GND are used. The second method is to put resistors in series with the analog inputs for current limiting. Limit the current to 15mA per channel. The +IN input can accept a resistor value of 1k but the –IN input cannot accept more than 200Ω when clocked at its maximum clock frequency of 500kHz. If the LTC1287 is clocked at the maximum clock frequency and 200Ω is not enough to current limit the input source then the clamp diodes are recommended (Figures 16 and 17). The reason for the limit on the resistor value is the MSB bit test is affected by the value of the resistor placed at the –IN input (see discussion on Analog Inputs and the Typical Performance Characteristics curve of Maximum CLK Frequency vs Source Resistance). If VCC and VREF are not tied together, then VCC should be turned on first, then VREF. If this sequence cannot be met, connecting a diode from VREF to VCC is recommended (see Figure 18). Because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device VCC without damaging the device. 1N4148 DIODES CS VCC +IN CLK +3V LTC1287 –IN DOUT GND VREF LTC1287 F15 Figure 15. Overvoltage Protection for Inputs CS VCC +IN CLK +3V 1k 200Ω LTC1287 –IN DOUT GND VREF LTC1287 F16 Figure 16. Overvoltage Protection for Inputs 1N4148 DIODES CS VCC +IN CLK +3V 1k LTC1287 –IN DOUT GND VREF LTC1287 F17 Figure 17. Overvoltage Protection for Inputs 1287fa 14 LTC1287 W U U UO APPLICATI S I FOR ATIO CS VCC +IN CLK 1N4148 LTC1287 –IN DOUT GND A “Quick Look” Circuit for the LTC1287 Users can get a quick look at the function and timing of the LTC1287 by using the following simple circuit (Figure 19). VREF is tied to VCC. VIN is applied to the +IN input and the –IN input is tied to the ground plane. CS is driven at 1/32 the clock rate by the 74HC393 and DOUT outputs the data. The output data from the DOUT pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of CS (Figure 20). Note the LSB data is partially clocked out before CS goes high. +3V +2.5V VREF LTC1287 F18 Figure 18 22µF TANTALUM + +3V f/32 VIN CS VCC +IN CLK –IN LTC1287 DOUT GND VREF TO OSCILLOSCOPE A1 f VCC CLR1 0.1µF A2 1QA CLR2 1QB 74HC393 2QA 1QC 2QB 1QD 2QC GND 2QD CLOCK IN 500kHz LTC1287 F19 Figure 19. "Quick Look" Circuit for the LTC1287 CLK CS DOUT NULL MSB LSB LSB DATA BIT (B11) (B1) (B0) VERTICAL: 5V/DIV HORIZONTAL: 5µs/DIV Figure 20. Scope Trace of the LTC1287 “Quick Look” Circuit Showing A/D Output 1010101010 (AAAHEX) 1287fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. 15 LTC1287 U PACKAGE DESCRIPTIO J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) 0.300 BSC (0.762 BSC) CORNER LEADS OPTION (4 PLCS) 0.008 – 0.018 (0.203 – 0.457) 0° – 15° 0.015 – 0.060 (0.381 – 1.524) 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 0.405 (10.287) MAX 0.005 (0.127) MIN 8 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS 0.014 – 0.026 (0.360 – 0.660) 0.100 (2.54) BSC 5 0.025 (0.635) RAD TYP 0.220 – 0.310 (5.588 – 7.874) 1 0.045 – 0.065 (1.143 – 1.651) 6 7 2 3 4 0.125 3.175 MIN 0.200 (5.080) MAX J8 1298 OBSOLETE PACKAGE N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( 0.045 – 0.065 (1.143 – 1.651) 0.400* (10.160) MAX 0.130 ± 0.005 (3.302 ± 0.127) 0.065 (1.651) TYP 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) +0.035 0.325 –0.015 +0.889 8.255 –0.381 ) 0.100 (2.54) BSC 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1098 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1289 12-Bit, 8-Channel Serial ADC 3V or ±3V Supply, Programmable MUX, 25ksps LTC1401 12-Bit, 200ksps Serial ADC in SO-8 3V Supply, 15mW, Internal References LTC1594L/LTC1598L 12-Bit, 4-/8-Channel Serial ADC 3V, Micropower, Auto Shutdown, 10ksps LTC1852/LTC1853 10-Bit/12-Bit, 8-Channel, 400ksps Parallel ADC 3V to 5V Supply, Programmable MUX and Sequencer LTC1860/LTC1861 12-Bit, 1-/2-Channel Serial ADCs 5V, Micropower, 250ksps, MSOP Package 1287fa 16 Linear Technology Corporation LT/TP 0102 1.5K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 1992