LTC1426 Micropower Dual 6-Bit PWM DAC U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Wide Supply Range: 2.7V ≤ VCC ≤ 5.5V Wide Reference Voltage Range: 0V to 5.5V Two Interface Modes: Pulse Mode (Increment Only) Pushbutton Mode (Increment/Decrement) Low Supply Current: 50µA 0.2µA Supply Current in Shutdown Available in 8-Pin MSOP and SO Packages DAC Contents Are Retained in Shutdown DACs Power-Up at Midrange Low Output Impedance: < 100Ω Output Frequency: 5kHz Typ The LTC®1426 is a dual micropower 6-bit PWM DAC featuring versatile PWM outputs and a flexible pushbutton compatible digital interface. The DAC outputs provide a PWM signal that swings from 0V to VREF, allowing the fullscale output to be varied by adjusting the voltage at VREF. The PWM output frequency is typically 5kHz, easing output filtering requirements. VCC supply current is typically 50µA and drops to 0.2µA in shutdown. The LTC1426 can be controlled using one of two interface modes: pushbutton and pulse. The LTC1426 automatically configures itself into the appropriate mode at startup by monitoring the state of the CLK pins. In pushbutton mode, the CLK pins can be directly connected to external pushbuttons to control the DAC output. In pulse mode, the CLK pins can be connected to CMOS compatible logic. The DAC outputs initially power up at half scale and the contents of the internal DAC registers are retained in shutdown. U APPLICATIONS ■ ■ ■ ■ ■ LCD Contrast and Backlight Brightness Control Power Supply Voltage Adjustment Battery Charger Voltage and Current Adjustment GaAs FET Bias Adjustment Trimmer Pot Elimination The LTC1426 is available in 8-pin MSOP and SO packages. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATION Pushbutton Adjustable CCFL/LCD Contrast Generator R1 44.2k 1% 5V RP1 47k UP R2 44.2k 1% 1 2 3 4 SHDN UP CONTRAST UP/DOWN 1 CCFL UP/DOWN 2 3 DOWN ICCFL = 0µA TO 50µA C2 1µF C1 0.1µF RSHDN 1M RP2 47k DOWN 4 C7 1µF LTC1426 CLK1 SHDN CLK2 VCC GND VREF PWM1 PWM2 R3 5.1k 1% R4 4.99k 1% 8 5 6 7 6 C8 0.68µF 5 UP TO 6mA LAMP CCFL PGND CCFL VSW ICCFL DIO BULB LT1182 CCFL VC BAT ROYER AGND VIN SHDN FBP 7 LCD VC R7 8 LCD PGND 10k FBN LCD VSW R5 20k 1% HIGH VOLTAGE ROYER 16 15 14 8V TO 28V 13 12 11 10 9 + C10 2.2µF 35V + C11 2.2µF 35V 5V C9 2.2µF LCD CONTRAST CONVERTER 1426 TA01 C3 10µF C4 0.1µF R6 40k 1% CONSULT THE LT1182 DATA SHEET FOR DETAILS ON THE HIGH VOLTAGE ROYER AND LCD CONTRAST CONVERTER SECTIONS VOUT NEGATIVE LCD CONTRAST VOUT = –10V TO –30V 1 LTC1426 W U PACKAGE/ORDER INFORMATION U W W W (Note 1) Total Supply Voltage (VCC) ........................................ 7V Reference Voltage (VREF) ............................... – 0.3 to 7V Input Voltage (All Inputs) .............. – 0.3 to (VCC + 0.3V) DAC Output Short-Circuit Duration.................. Indefinite IPWM(MAX) .......................................................... 100mA Operating Temperature Range LTC1426C................................................ 0°C to 70°C LTC1426I........................................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U ABSOLUTE MAXIMUM RATINGS ORDER PART NUMBER TOP VIEW CLK1 1 8 SHDN CLK2 2 7 VCC GND 3 6 VREF PWM1 4 LTC1426CMS8 LTC1426CS8 LTC1426IS8 5 PWM2 MS8 PART MARKING MS8 PACKAGE S8 PACKAGE 8-LEAD PLASTIC MSOP 8-LEAD PLASTIC SO LTBQ TJMAX = 100°C, θJA = 200°C/ W (MS8) TJMAX = 100°C, θJA = 130°C/ W (S8) S8 PART MARKING 1426 1426I Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TA = 25°C, (Note 2) unless otherwise specified. CONDITIONS MIN TYP MAX UNITS VCC Supply Voltage ● 2.7 5.5 V VREF Reference Voltage ● 0 5.5 V ICC Supply Current Pulse Mode: VSHDN = VCC, VCLK1 = VCLK2 = 0V, PWM1 = PWM2 = NC Pushbutton Mode: VSHDN = VCC, VCLK1 = VCLK2 = PWM1 = PWM2 = NC SHDN = 0 (Note 3) ● ● ● 40 50 0.2 100 100 ±10 µA µA µA IREF Reference Current Pulse Mode: VSHDN = VCC, VCLK1 = VCLK2 = 0V, PWM1 = PWM2 = NC Pushbutton Mode: VSHDN = VCC, VCLK1 = VCLK2 = PWM1 = PWM2 = NC SHDN = 0 (Note 3) ● ● ● 75 75 0.2 150 150 ±10 µA µA µA DAC Resolution 6 DAC Frequency 0°C ≤ TA ≤ 70°C – 40°C ≤ TA ≤ 85°C ● ● DAC Output Impedance VCC = 2.7V, VREF = 0.5V ● 3 2 DAC Full-Scale Duty Cycle bits 5 5 6 6 20 100 98.44 DAC Zero-Scale Duty Cycle kHz kHz Ω % 0 % DNL DAC Differential Nonlinearity Monotonicity Guaranteed (Note 4) ● ±0.05 LSB INL DAC Integral Nonlinearity (Note 4) ● ±0.05 LSB FS Error DAC Full-Scale Error IIN Logic Input Current VIH 2 CLK High Level Input Voltage (Note 5) ● ±0.50 LSB Pulse Mode: 0V ≤ VIN ≤ VCC SHDN CLK1, CLK2 ● ● ±5 ±5 µA µA Pushbutton Mode: 0V ≤ VIN ≤ VCC SHDN CLK1, CLK2 ● ● ±5 ±10 µA µA VCC = 5.5V SHDN CLK1, CLK2 ● ● 2.0 4.4 V V VCC = 3.6V SHDN CLK1, CLK2 ● ● 1.9 2.9 V V LTC1426 ELECTRICAL CHARACTERISTICS TA = 25°C, (Note 2) unless otherwise specified. SYMBOL PARAMETER CONDITIONS MAX UNITS VIL VCC = 4.5V SHDN CLK1, CLK2 ● ● 0.8 0.8 V V VCC = 2.7V SHDN CLK1, CLK2 ● ● 0.45 0.45 V V ● ±5 µA 1 750 MHz kHz CLK Low Level Input Voltage (Note 5) MIN SHDN = 0 TYP IOZ Three-State Output Leakage ZIN CLK Input Resistance Pushbutton Mode, CLK1/CLK2 fCLK Clock Frequency Pulse Mode, VCC = 3.3V Pulse Mode, VCC = 2.7V ● ● tCKHI Clock High Time Pulse Mode, VCC = 3.3V Pulse Mode, VCC = 2.7V ● ● 450 600 ns ns tCKLO Clock Low Time Pulse Mode, VCC = 3.3V Pulse Mode, VCC = 2.7V ● ● 450 600 ns ns tPW Pulse Width Pushbutton Mode ● 670 tDEB Debounce Time Pushbutton Mode ● 10.7 12.8 21.3 ms tDELAY Repeat Rate Delay Pushbutton Mode ● 340 410 680 ms fREPEAT Repeat Frequency Pushbutton Mode ● 11.7 19.5 23.4 Hz 2.5 MΩ µs Note 3: Shutdown current can be negative due to leakage currents if VCC > VREF or VREF > VCC. Note 4: Guaranteed by Design. Decouple the VCC and VREF pins to GND using high quality, low ESR, low ESL 0.1µF capacitors to eliminate PWM switching noise that may otherwise get coupled into the CLK1/CLK2 high impedance input buffers. The decoupling capacitors should be located in close proximity to these pins and the ground line to have maximum effect. Note 5: Input thresholds apply for both pushbutton and pulse modes. The ● denotes the specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground, unless otherwise specified. All typicals are given for VCC = VREF = 5V, TA = 25°C and PWM1/PWM2 output to GND, CPWM = 10pF. U W TYPICAL PERFORMANCE CHARACTERISTICS 0.05 0.03 0.03 0.02 0.02 0.01 0 – 0.01 0 – 0.01 – 0.02 – 0.03 – 0.03 – 0.04 – 0.04 – 0.05 – 0.05 16 24 32 40 CODE 48 56 64 1426 G01 VCC = 5V 0.01 – 0.02 8 1000 VCC = VREF = 5V TA = 25°C 0.04 ERROR (LSB) DNL ERROR (LSB) VCC = VREF = 5V 0.04 TA = 25°C OUTPUT PULL-DOWN VOLTAGE (mV) 0.05 0 Output Pull-Down Voltage vs Output Current Sink Capability Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 0 8 16 24 32 40 CODE 48 56 64 1426 G02 85°C 100 25°C – 40°C 10 1 0.1 0.1 1 10 100 OUTPUT CURRENT SINK CAPABILITY (mA) 1426 G03 3 LTC1426 U W TYPICAL PERFORMANCE CHARACTERISTICS Minimum Clock High Time vs Temperature Supply Current vs Logic Input Voltage 60 VCC = 3V 300 200 VCC = 5V 100 32.5 PULSE MODE 30.5 28.5 26.5 TA = 25°C CLK1 AND CLK2 TIED TOGETHER 24.5 0 – 40 50 34.5 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 400 VCC = 5V PUSHBUTTON MODE 36.5 500 CLOCK HIGH TIME (ns) Supply Current vs Temperature 38.5 600 10 35 TEMPERATURE (°C) 85 60 0 1 30 PULSE MODE 20 10 22.5 – 15 PUSHBUTTON MODE 40 3 4 2 LOGIC INPUT VOLTAGE (V) 1426 G04 5 0 – 40 – 15 10 35 TEMPERATURE (°C) 60 85 1426 G06 1426 F05 U U U PIN FUNCTIONS CLK1 (Pin 1): Channel 1 Clock/Pushbutton Input. CLK2 (Pin 2): Channel 2 Clock/Pushbutton Input. GND (Pin 3): Ground. It is recommended that GND be tied to a ground plane. PWM1 (Pin 4): Channel 1 PWM Output. PWM2 (Pin 5): Channel 2 PWM Output. VREF (Pin 6): Voltage Reference Input. VREF powers the DAC output buffers and can be used to control the output span. Bypass VREF to GND with an external capacitor to minimize output errors. VREF can be tied to VCC if desired. VCC (Pin 7): Voltage Supply. This supply must be kept free from noise and ripple by bypassing directly to the ground plane. SHDN (Pin 8): Shutdown. A logic low puts the chip into shutdown mode with the PWM outputs in high impedance. The digital settings for the DACs are retained in shutdown. WU W TI I G DIAGRA S Pulse Mode Timing tCKL0 Pushbutton Mode Timing tPW tCKHI CLK1 CLK2 CLK1 CLK2 1426 TC01 4 1426 TC02 LTC1426 W BLOCK DIAGRAM POWER-ON RESET LATCH AND LOGIC CLK1 CLK2 MODE SELECT 0 = PUSHBUTTON MODE 1 = PULSE MODE INPUT CONDITIONING CONTROL LOGIC DEBOUNCE CIRCUIT SHDN VREF 6-BIT UP/DOWN COUNTER 6 6-BIT UP/DOWN COUNTER 6 6-BIT UP COUNTER 6 COMPARATOR DRIVER PWM1 DRIVER PWM2 COMPARATOR OSCILLATOR 1426 F01 Figure 1. LTC1426 Block Diagram U U DEFI ITIO S LSB: The least significant bit or the ideal duty cycle difference between two successive codes. LSB = DCMAX/64 DCMAX = The DAC output maximum duty cycle DNL: Differential nonlinearity is the difference between the measured duty cycle change and the ideal 1LSB duty cycle change between any two adjacent codes. The DNL error between any two codes is calculated as follows: Resolution: The resolution is the number of DAC output states (64) that divide the full-scale output duty cycle range. The resolution does not necessarily imply linearity. DNL = (∆DCOUT – LSB)/LSB ∆DCOUT = The measured duty cycle difference between two adjacent codes. INL: End point integral nonlinearity is the maximum deviation from a straight line passing through the end points of the DAC transfer curve. The INL error at a given code is calculated as follows: Full-Scale Error: Full-scale error is the difference between the ideal and measured DAC output duty cycles with all bits set to one (Code = 63). The full-scale error is calculated as follows: INL = (DCOUT – DCIDEAL)/LSB DCIDEAL = (Code)(LSB) DCOUT = the DAC output duty cycle measured at the given number of clocked in pulses. FSE = (DCOUT – DCIDEAL)/LSB DCIDEAL = DCMAX U W U U APPLICATIONS INFORMATION Dual 6-Bit PWM DAC Figure 1 shows a block diagram of the LTC1426. Each 6-bit PWM DAC is guaranteed monotonic and is digitally adjustable in 64 equal steps, which corresponds from 0% to 98.5% duty cycle full scale. At power-up, the counters reset to 100000B and both DAC outputs assume midscale duty cycle. The PWM outputs have an output impedance of less than 100Ω. The DAC outputs swing from 0V to the reference voltage, VREF, which can be biased from 0V to 5.5V. The frequency of the DAC outputs is above 3kHz, easing output filtering. In the case of a pure resistive load, the voltage measured across load RL is given by: V = (VPWM)RL/(RL + ROUT) 5 LTC1426 U U W U APPLICATIONS INFORMATION where VPWM is the no load DAC output voltage, RL is the resistive load and ROUT is the DAC output impedance. Therefore, the resistive load RL should be sufficiently large to ignore the effect of output impedance on the load voltage. Figure 2 shows a typical lowpass filter recommended to filter the PWM outputs. Without filtering, results obtained from unfiltered outputs can be erroneous when taking measurements from a voltmeter. The ratio of the filter time constant, t, to the PWM frequency determines the amount of output ripple frequency that feeds into the system. In addition, the loading of the output also determines an additional error voltage drop across R1. R1 10k INPUT C1 0.1µF OUTPUT power-up, then the chip configures in pulse mode until the next VCC reset. Figure 3 shows the simplified logic for determining the interface mode at power-up. A set of pull-up/pull-down resistors allow the LTC1426 to sense the state of the CLK pins at power-up. If both CLK1 and CLK2 pins are floating on power-up then the control signal from the LTC1426 leaves these resistors in place, allowing the LTC1426 to detect three operating states at each CLK pin: high, low and “middle” (floating). If the CLK pins are tied to either logic 0 or 1 at power-up, then the control signal will disconnect these resistors, making CLK1 and CLK2 CMOS compatible input pins. Note that both CLK pins will always be in the same mode. If one pin is floating and the other is at logic high/low on power-up, the LTC1426 will assume pulse mode. 1426 F02 Figure 2. Lowpass Filter for PWM Averaging VCC Digital Interface The LTC1426 can be controlled by using one of two interface modes: pulse mode and pushbutton mode. The operating interface mode is determined during powerup. If both CLK1 and CLK2 inputs are floating on power-up, then an interface mode detect circuit configures the chip in pushbutton mode until the next VCC reset (Figure 3). However, if either of CLK1 or CLK2 is at logic 0 or 1 at INTERNAL LOGIC CLK1 INPUT CLK2 INPUT CONTROL CLK1 CLK2 LTC1426 1426 F03 Figure 3. Interface Mode Detect Circuit U TYPICAL APPLICATIONS N Typical applications for this part include digital calibration, industrial process control, automatic test equipment, cellular telephones and portable battery-powered applications. Figures 4 and 5 show how easy this part is to use. In all applications, the PWM full-scale output voltage is set by VREF. This makes interfacing convenient when a variety of reference spans are needed. processors (MPUs). The Intel 8051 was chosen to demonstrate direct interface for the LTC1426, as this VCC 2.7V TO 5.5V MPU (e.g. 8051) P1.0 2 P1.1 3 Pulse Mode Figure 4 shows the LTC1426 in a pulse mode, stand-alone application. The LTC1426 can interface directly with minimum external components to most popular micro- 6 0.1µF LTC1426 1 PWM1 4 CLK1 SHDN CLK2 VCC GND VREF PWM1 PWM2 8 SHDN 7 6 VREF 0V TO 5.5V 5 PWM2 PWM1/PWM2: 0V TO 0.985(VREF) 1426 F04 Figure 4. Stand-Alone Pulse Mode Interface LTC1426 U TYPICAL APPLICATIONS N microprocessor has “quasi-bidirectional” ports that eliminate additional pull-up resistors to VCC. However, external pull-up resistors should be used if the microprocessor doesn’t pull the port pins high during reset. respective counter by one count, and stops incrementing when the counter reaches full scale (111111B). A logic 0 pulse applied to the CLK1 or CLK2 input decrements the respective counter by one count, and stops decrementing when the counter reaches zero scale (000000B). An onchip debouncing circuit has a debounce time of 12.8ms to prevent unintended counts with bouncing pushbuttons. After a time delay of 410ms, the counter will begin to increment/decrement at a repeat rate of 19.5Hz if the pushbutton remains pressed. In pulse mode, each clock pulse applied to the CLK1 or CLK2 input increments the respective counter by one count. When the counter increases beyond full scale (111111B), the counter rolls over and becomes zero scale (000000B). In this way, a single pulse applied to the CLK1 or CLK2 input increases the respective counter by one count, and 63 pulses decrease that counter by one count. Care should be taken to avoid running the CLK and PWM traces close to one another. Since the CLK pins are high impedance input nodes in pushbutton mode, current spikes caused by the switching of the PWM outputs feedthrough via any stray capacitance between PWM and CLK lines if not properly routed. Use of proper grounding techniques and spacing of these lines are highly recommended for optimal performance. Pushbutton Mode Figure 5 shows how to use the LTC1426 in a typical pushbutton application. In pushbutton mode, a logic 1 pulse applied to the CLK1 or CLK2 input increments the VCC 2.7V TO 5.5V R VCC 2.7V TO 5.5V R LTC1426 1 UP UP 2 3 DOWN DOWN PWM1 4 CLK1 SHDN CLK2 VCC GND VREF PWM1 PWM2 Figure 6 shows a dual digitally programmable current source using the LT ®1013 dual precision op amp and two NPN transistors (2N3904). After the lowpass filter combination of R1, C1 (R2, C2), its output swings from 0V to 4.93V. In the configuration shown, this voltage will be forced across the resistor RA1 (RA2). If RA1 (RA2) is chosen to be 493Ω, the output current will range from 0mA at zero scale to 10mA at full scale. The minimum voltage for VS is determined by the load resistor RL1 (RL2) and Q1(Q2)’s VCESAT voltage. With a load resistor of 50Ω, the voltage source can be as low as 5V. 0.1µF 8 SHDN 7 6 VREF 0V TO 5.5V 5 PWM2 PWM1/PWM2: 0V TO 0.985(VREF) 1426 F05 LIMITING RESISTOR R PREVENTS SHORTING OF VCC AND GND WHEN BOTH BUTTONS ARE SIMULTANEOUSLY PUSHED. THIS RESISTOR CAN BE PLACED EITHER IN THE VCC OR GND LEG AND THIS DETERMINES THE FUNCTION WHEN BOTH BUTTONS ARE PUSHED. VALUE OF R < 50k Figure 5. Pushbutton Mode Interface SHDN MPU (e.g. 8051) P1.0 P1.1 5V VS RL1 0.1µF LTC1426 1 2 3 4 CLK1 SHDN CLK2 VCC GND VREF PWM1 PWM2 VS 10V 0.1µF 2N3904 8 RL2 2N3904 LT1013 1 7 6 RA1 493Ω R1 10k 5 2 3 C1 0.1µF R2 10k C2 0.1µF 4 OUT A V+ –IN A OUT B +IN A – IN B V– + IN B 8 RA2 493Ω 7 6 5 1426 F06 IOUT1/IOUT2: 0mA TO 10mA RL1/RL2: < 50Ω VS: 5V TO 30V Figure 6. Dual Digitally Programmable Current Source Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7 LTC1426 U TYPICAL APPLICATIONS N Shutdown Mode shutdown function features the data retention of the current PWM1 and PWM2 codes so that upon release from a shutdown condition, these states are reinstated. This is a functional difference in comparison to the half-scale preset for both PWM1 and PWM2 outputs upon power-up. Upon the application of a logic low shutdown signal, the entire IC converts to micropower shutdown mode where VCC supply current reduces to less than 0.3µA typical. The U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.040 ± 0.006 (1.02 ± 0.15) 0.007 (0.18) 0.006 ± 0.004 (0.15 ± 0.10) 0.118 ± 0.004* (3.00 ± 0.10) 8 7 6 5 0° – 6° TYP 0.021 ± 0.004 (0.53 ± 0.01) 0.118 ± 0.004** (3.00 ± 0.10) 0.192 ± 0.004 (4.88 ± 0.10) 0.012 (0.30) 0.025 (0.65) TYP 1 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 2 3 4 MSOP08 0595 S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0.189 – 0.197* (4.801 – 5.004) 8 0.004 – 0.010 (0.101 – 0.254) 7 6 5 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.050 (1.270) BSC 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) SO8 0695 1 2 3 4 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1182/LT1183 CCFL/LCD Contrast Switching Regulators 3V to 30V Single Supply in 16-Pin SO LTC1257 Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V. Reference Can Be Overdriven Up to 12V, i.e., FS Max = 12V 5V to 15V Single Supply, Complete VOUT DAC in SO-8 LTC1329/LTC1329-10/LTC1329-50 Micropower IOUT 8-Bit Current DAC 2.7V to 6.5V Single Supply in SO-8 LTC1446/LTC1446L Dual, Serial I/O VOUT 12-Bit DAC in SO-8 Rail-to-Rail VOUT, 5V/3V Single Supply LTC1451/LTC1452/LTC1453 Complete Serial I/O VOUT 12-Bit DACs Rail-to-Rail VOUT, 3V/5V Single Supply in S0-8 LTC1590 Dual, Serial I/O Multiplying IOUT 12-Bit DAC 5V Single Supply in 16-pin SO Package LTC8043 Serial I/O Mulitplying IOUT 12-Bit DAC 5V Single Supply in SO-8 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com 1426f LT/GP 0597 7K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1997