LTC3447 I2C Controllable Buck Regulator in 3mm × 3mm DFN U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO I2C Programmable Output with 21.6mV Resolution Overtemperature Protected High Efficiency: Up to 93% Very Low Quiescent Current: Only 33µA 600mA Output Current at VIN = 3V 2.5V to 5.5V Input Voltage Range 1MHz Constant Frequency Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle Stable with Ceramic Capacitors Shutdown Mode Draws <1µA Supply Current ±2% Output Voltage Accuracy Standard (100kHz) or Fast Mode (400kHz) I2C 6-Bit Voltage DAC (0.69V to 2.05V) Disable Burst Mode Operation Enable Power Good Blanking Optional External Start-Up Resistors Soft-Start 10 Lead, 3mm × 3mm DFN Package U APPLICATIO S ■ ■ ■ Distributed Power Supplies Notebook Computers PDAs and Other Handheld Devices The LTC®3447 is a high efficiency monolithic synchronous current mode buck regulator. Using an I2C interface, the output voltage can be set between 0.69V and 2.05V using an internal 6-bit DAC. The buck regulator has optional external feedback resistors that can be used for setting the initial start up voltage. The feedback voltage reference for this start-up option is 0.6V. Once the voltage DAC is updated via the I2C, the buck regulator switches from external to internal feedback resistors. When there are no external resistors, the default start-up voltage is 1.38V. The switching frequency is internally set at 1MHz, allowing the use of small surface mount inductors and capacitors. In Burst Mode® operation, supply current is only 33µA, dropping to <1µA in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3447 ideally suited for single cell Li-Ion battery-powered applications. 100% duty cycle capability provides low dropout operation, extending battery life in portable systems. Automatic Burst Mode operation increases efficiency at light loads, further extending battery life. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131. U TYPICAL APPLICATIO VCCD 10k 10k PWREN C3 4.7µF VIN VIN PGOOD LTC3447 SW VCCD RUN SDA VOUT SCL FB SDA SCL GND * 600mA AT VIN = 3V 90 80 RPU1 20k EXPOSED PADDLE TO GROUND L1 3.3µH C1 10µF VOUT 0.69V TO 2.05V AT 600mA* R1 100k 70 100 60 50 40 10 30 20 R2 49.9k PULSE SKIP EFFICIENCY Burst Mode EFFICIENCY LOSS 10 0 1 3447 TA01 POWER LOSS (mW) I2C 1000 100 C2 4.7µF CERAMIC EFFICIENCY (%) VIN 2.5V TO 5.5V Efficiency and Power Loss vs Load Current (VIN = 3.6V) 10 100 LOAD CURRENT (mA) 1 1000 3447 TA01b 3447f 1 LTC3447 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) VIN, VCCD Voltages ....................................... –0.3V to 6V RUN, VOUT, FB Voltages .............................. – 0.3V to VIN SW Voltage ................................... –0.3V to (VIN + 0.3V) SCL, SDA Voltages ................................... – 0.3V to VCCD P-Channel Switch Source Current (DC) ...............800mA N-Channel Switch Sink Current (DC) ...................800mA Peak SW Sink and Source Current ...........................1.3A Operating Temperature Range (Note 2) ...–40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range...................–65°C to 125°C ORDER PART NUMBER TOP VIEW 10 SDA VOUT 1 GND 2 FB 3 PGOOD 4 7 RUN VIN 5 6 SW 11 LTC3447EDD 9 VCCD 8 SCL DD PACKAGE 10-LEAD (3mm x 3mm)PLASTIC DFN EXPOSED PAD IS GND (PIN 11) MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 43°C/W, θJC = 2.96°C/W DD PART MARKING LBKB Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified. SYMBOL RUN PGOOD RVOUT VOUT(MIN) VOUT(MAX) VOUT PARAMETER Run Threshold Reports Undervoltage Feedback Resistance Regulated Output Voltage Regulated Output Voltage Output Voltage Step Size (6-bits) CONDITIONS ΔVOUT Output Voltage Line Regulation VIN = 2.5V to 5.5V (Note 6) IPK Peak Inductor Current Output Voltage Load Regulation Input Voltage Range Input DC Bias Current Burst Mode Operation Active Mode Shutdown Duty Cycle < 35%, Wafer Level VLOADREG VIN IS fOSC Nominal Oscillator Frequency RPFET RNFET ILSW FB IFB RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET SW Leakage Optional Start-Up Feedback Voltage Feedback Input Current I2C Clock Logic Threshold I2C Clock Logic Hysteresis I2C Data Logic Threshold I2C Data Logic Hysteresis SCLTHR SCLHYST SDATHR SDAHYST MIN 0.3 3 PGOOD = 0.4V ● ● ● ● 0.75 ● (Note 4) ILOAD = 0A VOUT = 90%, ILOAD = 0A VRUN = 0V, VIN = 5.5V VOUT = 100% VOUT = 0V ISW = 100mA, Wafer Level ISW = –100mA, Wafer Level VRUN = 0V, VSW = 0V or 5V, VIN = 5V Regulated Feedback Voltage (Note 5) (Note 5) (Note 5) (Note 5) 0.669 1.989 20.3 ● TYP 1 MAX 1.5 460 0.69 2.05 21.6 0.711 2.112 22.9 0.2 0.2 1.2 1 %/V %/V 1 0.5 1.25 A % V 2.5 0.7 5.5 34 280 0.1 1 160 0.32 0.22 ±0.1 0.6 2.5 VCCD/2 300 VCCD/2 300 60 400 1 1.3 ±1 10 UNITS V mA kΩ V V mV µA µA µA MHz kHz Ω Ω µA V nA V mV V mV 3447f 2 LTC3447 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified. SYMBOL PARAMETER I2C Interface Timing fI2C, MAX Maximum I2C Operating Frequency tBUF Bus Free Time Between Stop and Start Condition tHD,RSTA Hold Time After (Repeated) Start Condition tSU,RSTA Repeated Start Condition Setup Time tSU,STOP Stop Condition Setup Time tHD,DIN Data Hold Time, Input tHD,DOUT Data Hold Time, Output tSU,DAT Data Setup Time tSP Pulse Width of Spikes Suppressed by Input Filter CONDITION MIN (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) 1.3 0.6 0.6 20 0 280 50 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3447E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature, TA, and the power dissipation, PD, according to the following formula: TJ = TA + PD • 43°C/W TYP 410 MAX UNITS 400 kHz µs µs µs µs ns ns ns ns 670 150 This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. Note 5: Determined by design, not production tested. Note 6: The LTC3447 is tested in a proprietary test mode that connects VOUT to FB. WU W TI I G DIAGRA SDA tBUF tSU, STA tSU, DAT tHD, DAT tHD, STA tSU, STO tLOW SCL tHD, STA tr START COMMAND tHIGH tf REPEATED START COMMAND STOP COMMAND START COMMAND 3447 F01 Figure 1. Timing Diagram 3447f 3 LTC3447 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency and Power Loss vs Load Current (VIN = 5.5V) 90 0.3 80 0.2 70 EFFICIENCY (%) INL 0.1 0 DNL – 0.1 20 – 0.4 10 – 0.5 0 30 DAC 20 40 50 60 LOSSMAX 10 100 60 50 LOSSMAX 40 1 20 10 100 LOAD CURRENT (mA) 1 1000 1 Output Voltage vs Load Current Bias Current vs Supply Voltage 2.10 0.80 2.05 DAC = MAX 0.75 350 10 LOSSMIN 30 VOUTMAX (V) LOSSMAX VIN = 3.6V VIN = 2.5V 2.00 DAC = MIN 0.70 VIN = 3.6V VIN = 2.5V 0.65 1.95 20 VOUTMIN (V) 60 POWER LOSS (mW) 100 BIAS CURRENT (µA) 300 VOUTMIN 40 10 100 LOAD CURRENT (mA) 3447 G02 VOUTMAX 50 1 1000 0 3447 GO1 80 70 10 LOSSMIN 10 1000 100 250 PULSE SKIP 200 150 100 50 10 0 1 10 100 LOAD CURRENT (mA) 1 1000 1.90 0 200 BURST 0 2.5 0.60 1000 600 800 400 LOAD CURRENT (mA) 3447 G03 4.5 3.5 SUPPLY VOLTAGE (V) 5.5 3447 G05 Frequency vs Supply Voltage 3447 G06 Bias Current and Shutdown Current vs Temperature Frequency vs Temperature 1.30 1.24 1.08 1.18 FREQUENCY (MHz) 1.06 1.04 1.02 1.00 0.98 1.12 1.06 1.00 0.94 0.88 0.96 0.82 0.94 0.76 0.92 2.5 3.5 4.5 SUPPLY VOLTAGE (V) 5.5 3447 G07 360 0.70 –40 –20 2.5 VIN = 5.5V VIN = 3.6V VIN = 2.5V 310 2.0 1.5 260 SHUTDOWN CURRENT 1.0 VIN = 5.5V 210 VIN = 3.6V SHUTDOWN CURRENT (µA) 1.10 3.0 BIAS CURRENT BIAS CURRENT (mA) 1.12 FREQUENCY (MHz) VOUTMIN 70 30 LOSSMIN EffIciency and Power Loss vs Load Current (VIN = 2.5V) EFFICIENCY (%) 100 VOUTMIN 3447 G04 90 VOUTMAX 80 40 – 0.3 10 90 50 30 1000 100 VOUTMAX 60 – 0.2 0 1000 EFFICIENCY (%) 100 0.4 POWER LOSS (mW) 0.5 EffIciency and Power Loss vs Load Current (VIN = 3.6V) POWER LOSS (mW) ERROR (LSB) DAC Nonlinearity 0.5 VIN = 2.5V 0 20 40 60 80 100 120 TEMPERATURE (°C) 3447 G08 160 –40 –20 0 20 40 60 80 100 120 0 TEMPERATURE (°C) 3447 G09 3447f 4 LTC3447 U W TYPICAL PERFOR A CE CHARACTERISTICS RDS(ON) vs Temperature Output Voltage vs Supply Voltage 0.60 0.55 0.55 2.055 0.50 0.50 2.050 0.710 2.045 0.705 2.040 0.700 PFET 0.40 0.35 NFET 0.30 0.25 0.20 2.5 3.5 5.5 4.5 VIN = 3.6V 0.45 PFET VOUTMAX (V) RDS(ON) (Ω) 0.45 2.060 0.40 0.35 NFET 0.720 0.715 DAC = MAX 2.035 0.695 DAC = MIN 0.30 2.030 0.690 0.25 2.025 0.685 0.20 –40 –20 0 SUPPLY VOLTAGE (V) 2.020 2.5 20 40 60 80 100 120 TEMPERATURE (°C) 3447 G10 Feedback Reference vs Supply Voltage 3447 G12 Feedback Voltage vs Temperature 610 0.680 5.5 3.5 4.5 SUPPLY VOLTAGE (V) 3447 G11 VOUTMIN (V) RDS(ON) (Ω) RDS(ON) vs Supply Voltage 0.60 Load Step (200mA to 400mA) 618 VOUT 612 50mV/DIV 605 FB (V) VFB (V) 606 600 600 LOAD CURRENT 594 200mA/DIV 595 588 590 2.5 3.5 4.5 SUPPLY VOLTAGE (V) 5.5 582 –40 –20 0 20 40 60 80 100 120 40µs/DIV TEMPERATURE (°C) 3447 G13 Soft-Start with No Load 3447 G15 3447 G15 VOUT(MIN) to VOUT(MAX) Transition VOUT(MAX) to VOUT(MIN) Transition PULSE SKIP MODE 500mV/DIV 500mV/DIV VOUT 500mV/DIV BURST MODE OPERATION VOUT 500mV/DIV VOUT 5V/DIV PGOOD INDUCTOR CURRENT 100mA/DIV 200mA/DIV 5V/DIV 5V/DIV 200mA/DIV INDUCTOR CURRENT INDUCTOR CURRENT 200µs/DIV 3447 G16 PGOOD 100µs/DIV 3447 G17 PGOOD 100µs/DIV 3447 G18 3447f 5 LTC3447 U U U PI FU CTIO S VOUT (Pin 1): Output Voltage Sensing Pin. An internal resistor divider provides the divided down feedback reference for comparison. SW (Pin 6): Switch Node Connector to Inductor. This pin connects the drains of the internal main and synchronous power MOSFET switches. GND (Pin 2): Ground for all Circuits Excluding the Internal Synchronous Power NFET. RUN (Pin 7): Run Control Input. Forcing pin above 1.5V enables the part. Forcing the pin below 0.3V shuts down the device. In shutdown, all functions are disabled drawing <1µA of supply current. Do not leave the RUN pin floating. FB (Pin 3): Feedback Sensing Pin for the Optional External Feedback Resistors. Must be tied to VIN if there are no external feedback resistors. SCL (Pin 8): I2C Clock Input. PGOOD (Pin 4): Fault Report. Open drain driver sinks current when VOUT is 10% out of tolerance. Blanking during DAC changes can be enabled via the I2C. VCCD (Pin 9): I2C Power Rail. SDA (Pin 10): I2C Data Input. VIN (Pin 5): Main Supply Pin. Must be closely decoupled to GND with a 2.2µF or greater capacitor. Exposed Pad (Pin 11): Ground. Must be connected to PCB ground for electrical contact and optimized thermal performance. W BLOCK DIAGRA VIN CIN RUN VOUT 6-BIT DAC VCCD + VDAC SDA I2C SCL BURST DAC SLEW SOFT-START SW SW BUCK VREF REGULATOR COUT 1.3R – BURST LOAD VFB MUX R BLANK PGOOD POWER GOOD REF UV REF OV REF R1 MUX FB R2 S DAC LTC3447 3447 BD Figure 2. LTC3447 High Level Block Diagram 3447f 6 LTC3447 U OPERATIO BUCK OPERATION VIN VFB PEAK CURRENT LEVEL REF EA VREF ICOMP RS LATCH OSC S Q R QB RS PFET SW LOGIC NFET BURST 50mA. When below this level, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 33µA, and the peak current level reference level is held at 150mA. The LTC3447 remains in this sleep state until the output voltage falls below the output voltage setting. Once this occurs, the regulator wakes up and allows the inductor to develop 150mA current pulses. For light loads, this will cause the output voltage to increase and the internal peak current reference to decrease. When the peak current reference falls to below 50mA, the part re-enters sleep mode and the cycle is repeated. This process repeats at a rate that is dependent on the load demand. Pulse Skipping Mode Operation IRCMP BUCK REGULATOR 3447 AI01 Figure 3. LTC3447 Buck Regulator Diagram Main Control Loop The LTC3447 uses current mode step-down architecture with both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch, is controlled by the output of error amplifier EA. When the load current increases, it causes a slight decrease in the feedback voltage, FB, relative to an internal reference voltage, which in turn, causes the EA amplifier’s output voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. Burst Mode Operation The LTC3447 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. Burst Mode operation can be disabled via the I2C interface. When Burst Mode operation is disabled, the regulator is in pulse skipping mode operation. During Burst Mode operation, the LTC3447’s internal circuits sense when the inductor peak current falls below At light loads, the inductor current may reach zero or reverse on each pulse. The bottom MOSFET is turned off by the current reversal comparator, IRCMP, and the switch voltage will ring. This is discontinuous mode operation, and is normal behavior for a switching regulator. At very light loads, the LTC3447 will automatically skip pulses in pulse skipping mode operation to maintain output regulation. This feature is enabled when the Burst Mode operation is disabled. Short-Circuit Protection When the output is shorted to ground, the frequency of the oscillator is reduced to about 160kHz. This frequency foldback ensures that the inductor current has more time to decay, thereby preventing thermal runaway. The oscillator’s frequency will progressively increase to 1MHz when VOUT rises above 0V. Dropout Operation When using the optional external feedback resistors, it is possible for VIN to approach the output voltage level. As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore, 3447f 7 LTC3447 U OPERATIO the user should calculate the power dissipation when the LTC3447 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information section). for duty cycles >40%; however, the LTC3447 uses a patent-pending scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Low Supply Operation DAC The LTC3447 will operate with input supply voltages as low as 2.5V, but the maximum allowable output current is reduced at this low voltage. Figure 4 shows the reduction in the maximum output current as a function of input voltage for various output voltages. The I2C interface is used to control the internal voltage DAC for the buck regulator. The output voltage range is 0.69V to 2.05V in 21.6mV steps. The default DAC setting is 100000 which equates to a 1.38V output voltage. Output voltage transitions begin once the I2C interface receives the STOP command. Slope Compensation and Inductor Peak Current Slew Rate Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current MAXIMUM LOAD CURRENT (mA) 1200 The LTC3447 has a slew rate of approximately 11mV/µs. The slew rate is controlled by the RC time constant of a low pass filter at the voltage DAC output. Figure 5 shows a typical transition from min to max DAC settings. TA = 25°C BURST MODE OPERATION VIN = 3.6V VOUT DAC = MIN 1100 500mV/DIV 1000 INDUCTOR CURRENT DAC = MAX 900 200mA/DIV 800 5V/DIV PGOOD 700 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 100µs/DIV 3447 F04 Figure 4. Maximum Load Current vs Supply Voltage Figure 5.Transition from DAC = MIN to DAC = MAX SDA 1-7 SCL 8 9 1-7 8 9 1-7 8 9 S START COMMAND P ADDRESS R/W ACK DATA ACK DATA ACK ST0P COMMAND 3447 TD02 Figure 6. Typical I2C Write Protocol 3447f 8 LTC3447 U OPERATIO External Start-Up Option The LTC3447 allows for the use of optional external resistors to determine the start-up voltage. Using this option, the start-up voltage can be set to levels inside or outside the DAC output’s operating range. The output voltage will be regulated at this value until the internal DAC is updated and a STOP command is received. Once the STOP command is received, the internal DAC will retain control of the output voltage until the part is disabled then enabled again. If this feature is not used, the feedback pin must be tied to VIN. I2C OPERATION n n n n n n n n Typical 2-wire serial I2C Serial interface Simple 2-wire interface Multiple devices on same bus Idle bus must have SDA and SCL lines high LTC3447 is write only Master controls bus Devices listen for unique address that precedes data General I2C Bus/SMBus Description I2C Bus and SMBus are reasonably similar examples of two wire, bidirectional, serial communications busses. Calling them two wire is not strictly accurate, as there is an implied third wire, which is the ground line. Large ground drops or spikes between the grounds of different parts on the bus can interrupt or disrupt communications, as the signals on the two wires are both inherently referenced to a ground which is expected to be common to all parts on the bus. Both bus types have one data line and one clock line which are externally pulled to a high voltage when they are not being controlled by a device on the bus. The devices on the bus can only pull the data and clock lines low, which makes it simple to detect if more than one device is trying to control the bus; eventually, a device will release a line and it will not pull high because another device is still holding it low. Pull-ups for the data and clock lines are usually provided by external discrete resistors, but external current sources can also be used. Since there are no dedicated lines to use to tell a given device if another device is trying to communicate with it, each device must have a unique address to which it will respond. The first part of any communication is to send out an address on the bus and wait to see if another device responds to it. After a response is detected, meaningful data can be exchanged between the parts. Typically, one device will control the clock line at least most of the time and will normally be sending data to the other parts and polling them to send data back to it, and this device is called the master. There can certainly be more than one master, since there is an effective protocol to resolve bus contentions, and nonmaster (slave) devices can also control the clock to delay rising edges and give themselves more time to complete calculations or communications (clock stretching). Slave devices need to be able to control the data line to acknowledge communications from the master, and some devices will need to able to send data back to the master; they will be in control of the data line while they are doing so. Many slave devices will have no need to stretch the clock signal and will have no ability to pull the clock line low, which is the case with the LTC3447. Data is exchanged in the form of bytes, which are 8-bit packets. Every byte needs to be acknowledged by the slave (data line pulled low) or not acknowledged by the master (data line left high), so communications are broken up into 9-bit segments, one byte followed by one bit for acknowledging. For example, sending out an address consists of 7-bits of device address, 1-bit that signals whether a read or write operation will be performed, and then 1 more bit to allow the slave to acknowledge. There is no theoretical limit to how many total bytes can be exchanged in a given transmission. I2C and SMBus are very similar specifications, SMBus having been derived from I2C. In general, SMBus is targeted toward low power devices (particularly battery powered ones) and emphasizes low power consumption, while I2C is targeted toward higher speed systems where the power consumption of the bus is not so critical. I2C has three different specifications for three different maximum speeds, these being standard mode (100kHz max), fast mode (400kHz max), and HS mode (3.4MHz max). Standard and fast mode are not radically different, but HS mode is very different from a hardware and software perspective and requires an initiating command at standard or fast speed before data can start transferring at HS speed. SMBus simply specifies a 100kHz maximum speed. 3447f 9 LTC3447 U OPERATIO be left HIGH by the slave. The master can then generate a STOP command to abort the transfer. The START and STOP Commands When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START command by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP command by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. If a slave receiver does acknowledge the slave address but, some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP command. The data line is also left high by the slave and master after a slave has transmitted a byte of data to the master in a read operation, but this is a not acknowledge that indicates that the data transfer is successful. Acknowledge The acknowledge signal is used for handshaking between the master and the slave. An acknowledge signal (LOW active) is generated by the slave lets the master know that the latest byte of information was received. The acknowledge-related clock pulse is generated by the master. The transmitter master releases the SDA line (HIGH) during the acknowledge clock pulse. The slave receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. Commands Supported The LTC3447 supports only write byte commands to a single register. During ACK bit periods, the LTC3447 will pull the data line low to acknowledge the master device. See Figure 7. Data Transfer Timing for Write Commands In order to help assure that bad data is not written into the part, data from a write command is only stored after a valid STOP command has been performed. When a slave receiver doesn’t acknowledge the slave address (for example, it’s unable to receive because it’s performing some real-time function), the data line must WRITE BYTE PROTOCOL 1 7 1 1 8 1 1 START 1100110 0 ACK XXXXXXXX ACK STOP SLAVE ADDRESS WRITE DATA I2C REGISTER DEFINITION MSB 7 DISABLE BURST (DEFAULT = 0) 6 5 4 3 2 1 0 LSB ENABLE BUCK BUCK BUCK BUCK BUCK BUCK PGOOD DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 BLANKING (DEFAULT = 1) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) 3447 F07 Figure 7. LTC3447’s Write I2C Protocol 3447f 10 LTC3447 U OPERATIO Table 1. I2C Fast-Mode Timing Specifications (for Reference) fI2C tBUF tHD,RSTA tSU,RSTA tSU,STOP tHD,DAT tSU,DAT tLOW tHIGH tSP tf tr I2C Operating Frequency Bus free time between Stop and Start Condition Hold Time after (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Pulse Width of Spikes Suppressed by Input Filter Clock, Data Fall Time 0 1.3 0.6 0.6 0.6 0 100 1.3 0.6 0 20 + 0.1 • CB 50 300 kHz µs µs µs µs ns ns µs µs ns ns Clock, Data Rise Time 20 + 0.1 • CB 300 ns 400 0.9 CB = Capacitance of one bus line. U W U U APPLICATIO S I FOR ATIO The basic LTC3447 application circuit is shown on the front page of the data sheet. External component selection is driven by the load requirement and begins with the selection of L1 followed by CIN and COUT. to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Selection Inductor Core Selection For most applications, the value of the inductor will fall in the range of 1µH to 4.7µH. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in Equation 1. A reasonable starting point for setting ripple current is ΔIL = 240mA (40% of 600mA). ⎞ ⎛ 1 V ∆IL = VOUT ⎜ 1 – OUT ⎟ (f)(L) ⎝ VIN(MAX) ⎠ (1) Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or perm alloy materials are small and don’t radiate much energy, but generally cost more than powdered-iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price versus size requirements and any radiated field/EMI requirements than on what the LTC3447 requires to operate. Table 2 shows some typical surface mount inductors that work well in LTC3447 applications. The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 920mA rated inductor should be enough for most applications (800mA + 120mA). For better efficiency, choose a low DC resistance inductor. Table 2. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 50mA. Lower inductor values (higher ΔIL) will cause this Manufacturer Part Number Sumida CDRH3D16/HP3R3 Sumida CR434R7 Murata LQH55DN2R2MO3 Toko D52LC-A914BYW-2R2M Value DCR Max DC Size (µH) (mΩ max) Current (A) W x L x H (mm3) 3.3 85 1.4 4.0 x 4.0 x 1.8 4.7 109 1.15 4.0 x 4.5 x 3.5 2.2 29 3.2 5.0 x 5.0 x 4.7 2.2 59 1.63 5.0 x 5.0 x 2.0 3447f 11 LTC3447 U W U U APPLICATIO S I FOR ATIO CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: 1/ 2 VOUT (VIN – VOUT )] [ CIN required IRMS ≅ IOMAX VIN (2) This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ΔVOUT is determined by: ⎛ 1 ⎞ ∆VOUT ≅ ∆IL ⎜ ESR + ⎟ ⎝ 8fC OUT ⎠ (3) where f = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3447’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Output Voltage Programming The LTC3447 has an internal resistor divider network tied to the OUT pin. The output voltage is controlled by a DAC (6-bit register) whose setting is programmed via the I2C interface. The DAC controls the VOUT range of 0.69V to 2.05V in 21.6mV steps. The default value for VOUT is 1.38V and is reset to this value whenever VIN comes up. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3447 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R 3447f 12 LTC3447 U W U U APPLICATIO S I FOR ATIO loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 8. 1 RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. POWER LOSS (mW) Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ΔILOAD • ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT, which generates a feedback error signal. 0.1 0.01 DAC = MAX DAC = MIN 0.001 0.1 1 10 100 LOAD CURRENT (mA) 1000 3447 F08 Figure 8. Power Loss vs Load Current The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to The regulator loop then acts to return VOUT to its steady state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. Thermal Considerations In most applications the LTC3447 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3447 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3447 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum 3447f 13 LTC3447 U W U U APPLICATIO S I FOR ATIO junction temperature of the part. The temperature rise is given by: TR = θJA • PD where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the temperature. possible? This capacitor provides the AC current to the internal power MOSFETs. 5. Keep the switching node, SW, away from the sensitive VOUT and FB nodes. 6. Keep the (–) plates of CIN and COUT as close as possible. The junction temperature, TJ, is given by: TJ = TA + TR R2 where TA is the ambient temperature. As an example, consider the LTC3447 when using an input voltage of 3.6V, an ambient temperature of 70°C, and a buck load current of 500mA. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 70°C is approximately 0.45Ω. Therefore, power dissipated by the part is: GND PLANE R1 C2 VOUT SDA GND VCCD FB SCL PGOOD RUN PD = ILOAD2 • RDS(ON) = 112.5mW For the DFN-10 package, the θJA is 43°C/W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.1125)(43) = 74.8°C which is well below the maximum junction temperature of 150°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). SW VIN VIN CIN L1 COUT GND PLANE VIA TO VOUT PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3447. These items are also illustrated graphically in Figures 9 and 10. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace, and the VIN trace should be kept short, direct and wide. 3447 F09 Figure 9. LTC3447 Suggested Layout SDA GND VCCD C2 R2 2. Does the VOUT pin connect directly to the output voltage reference? Ensure that there is no load current running from the output voltage and the VOUT sense pin. 3. Does the FB pin connect directly to the feedback voltage reference? Ensure that there is no load current running from the feedback reference voltage and the FB pin. VOUT R1 FB SCL PGOOD RUN VIN CIN SW COUT L1 VIN VOUT 4. Does the (+) plate of CIN connect to VIN as closely as 3447 F11 Figure 10. LTC3447 Layout Diagram 3447f 14 LTC3447 U W U U APPLICATIO S I FOR ATIO Design Example ⎛ ⎞ 1 ∆VOUT = 0.280 A⎜ 0.25Ω + ⎟= 8(1MHz)(4.7µF)⎠ ⎝ 70mV + 7.4mV = 77.4mV As a design example, assume the LTC3447 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The normal load current requirement is a maximum of 500mA at 1.4V, but most of the time it will be in standby mode, requiring only 200µA at 1V. Efficiency at both low and high load currents is important. Note that the majority of the ripple voltage is generated by the capacitor’s ESR. Most ceramic capacitors will have a typical ESR of 10mΩ or less. Selecting capacitors with low ESRs will significantly reduce the ripple voltage. To ensure that the ripple currents and voltages do not exceed desired expectations over the DAC output range, calculations with maximum VIN and minimum VOUT should be used. Note that either increasing the output voltage or decreasing VIN will result in a decrease of ripple current and voltage. Choosing a maximum ripple current, ΔIL, of 280mA, Equation 1 can be used to determine the size of the inductor that should be used. Efficiency can be improved by taking advantage of the LT3447’s Burst Mode operation. When entering the standby mode, ensure that the burst disable bit is set to 0 when the output voltage DAC is updated. Likewise, when entering a heavy current load mode, ensure the burst disable bit is set to 1 when the output voltage DAC is updated. Figure 11 shows the advantage of utilizing the Burst Mode function. 100 1 ⎛ 1.4V ⎞ L= • 1.4V⎜ 1 – ⎟ = 3.3µH ⎝ 4.2V ⎠ (1MHz)(280mA) STBY DAC(MAX) DAC(MAX) 90 EFFICIENCY (%) 80 A 3.3µH inductor works well for this application. For best efficiency choose a 640mA or greater inductor with less than 0.2Ω series resistance. 70 NORMAL 60 DAC(MIN) 50 40 30 20 CIN will require an RMS current of at least 0.25A, approximately ILOAD(MAX)/2, overtemperature (see Equation 2). For COUT, selecting a 4.7µF capacitor with an ESR of 0.25Ω yields the following ripple voltage using Equation 3. 10 BURST PSK DAC(MIN) 0 0.1 1 10 100 LOAD CURRENT (mA) 1000 3447 F11 Figure 11. Efficiency vs Load Current ( VIN = 4.2V) U PACKAGE DESCRIPTIO DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 0.38 ± 0.10 6 10 5 1 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.50 BSC 2.38 ±0.05 (2 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS (DD10) DFN 1103 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3447f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3447 U TYPICAL APPLICATIO Li-Ion Battery to 1.4V/1V Regulator Li Ion BATTERY 20k L1 3.3mH VIN CIN 4.7mF FB PGOOD I2C BUS VCCD 10k 10k VOUT = SW LTC3447 PWREN 4.7mF 1.4V AT 500mA IN NORMAL OPERATION 1V AT 200mA IN STBY MODE COUT 4.7mF VOUT RUN VCCD SDA SDA SCL SCL CIN, COUT: TDK C1608X5R0J475MT L1: SUMIDA CDRH3D16-3R3 GND EXPOSED PADDLE TO GROUND 3447 TA02 RELATED PARTS PART NUMBER LT1761 DESCRIPTION 100mA, Low Noise Micropower, LDO LT1762 150mA, Low Noise Micropower, LDO LT1763 500mA, Low Noise Micropower, LDO LTC1844 150mA, Very Low Dropout LDO LT1962 300mA, Low Noise Micropower, LDO LT3020 Low VIN (0.9V) Low VOUT (0.2V) VLDOTM LTC3405/LTC3405A LTC4055 300mA (IOUT), 1.5MHz Synchronous Step-Down DC/DC Converter 600mA (IOUT), 1.5MHz Synchronous Step-Down DC/DC Converter Dual 600mA, 1.5MHz Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz Synchronous Step-Down DC/DC Converter 2.5A (IOUT), 4MHz Synchronous Step-Down DC/DC Converter, 600mA, 1.5MHz Synchronous Step-Down DC/DC Converter with Two LDOs and PowerPathTM Manager Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger USB Power Manager and Li-Ion Battery Charger LTC4411/LTC4412 PowerPath Controllers in ThinSOT LTC3406/LTC3406B LTC3407 LTC3411 LTC3412 LTC3445 LTC3455 COMMENTS VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.30V, IQ = 20µA, ISD < 1µA, VOUT = Adj, 1.5V, 1.8V, 2V, 2.5V, 2.8V, 3V, 3.3V, 5V, ThinSOTTM Package. Low Noise < 20µVRMS(P-P), Stable with 1µF Ceramic Capacitors VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.30V, IQ = 25µA, ISD < 1µA, VOUT = Adj, 2.5V, 3V, 3.3V, 5V, MS8 Package. Low Noise < 20µVRMS(P-P) VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.30V, IQ = 30µA, ISD < 1µA, VOUT = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, S8 Package. Low Noise < 20µVRMS(P-P) VIN: 6.5V to 1.6V, VOUT(MIN) = 1.25V, Dropout Voltage = 0.08V, IQ = 40µA, ISD < 1µA, VOUT = Adj, 1.5V, 1.8V, 2.5V, 2.8V, 3.3V, ThinSOT Package. Low Noise < 30µVRMS(P-P), Stable with 1µF Ceramic Capacitors VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.27V, IQ = 30µA, ISD < 1µA, VOUT = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, MS8 Package. Low Noise < 20µVRMS(P-P) VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, Dropout Voltage = 0.15V, IQ = 120µA, ISD < 1µA, VOUT = Adj, DFN Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20µA, ISD < 1µA, ThinSOT Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20µA, ISD < 1µA, ThinSOT Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD < 1µA, MS10E, QFN Packages VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD < 1µA, MS10 Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD < 1µA, TSSOP16E Package VIN: 2.5V to 5.5V, VOUT = 0.85V to 1.55V, IQ = 27µA, ISD < 1µA, Two LDOs I2C Interface, Back-Up Battery Management, QFN24 VIN: 3V to 5.5V, Seamless Transition Between Input Sources and Li-Ion Battery, USB, 5V Wall Adapter, QFN24 Package Standalone Charger, Automatic Switchover when Input Supply is Removed More Efficient than Diode ORing ThinSOT, VLDO and PowerPath are trademarks of Linear Technology Corporation. 3447f 16 Linear Technology Corporation LT/TP 0505 500 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005