LTC7545A Improved Industry Standard Parallel 12-Bit Multiplying DAC U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ The LTC ® 7545A is a 12-bit multiplying digital-to-analog converter (DAC) with a microprocessor compatible parallel input. It is a superior pin compatible replacement for the industry standard AD7545A and AD7545. Improvements include better accuracy, better stability over temperature and supply variations and lower sensitivity to output amplifier offset. Improved Direct Replacement for AD7545A and AD7545 DNL and INL Over Temperature: ±0.5LSB Gain Error: ±1LSB Maximum 4-Quadrant Multiplication Single 5V or 15V Supply Low Power Consumption Low Cost This very versatile DAC is useful for 2-quadrant and 4-quadrant multiplying, programmable gain and filtering and single supply noninverting voltage output operation. UO APPLICATI ■ ■ ■ ■ S Parts are available in 20-pin PDIP and SO packages and commercial and industrial temperature grades. Process Control and Industrial Automation Software Controlled Gain Adjustment Digitally Controlled Filter and Power Supplies Automatic Test Equipment , LTC and LT are registered trademarks of Linear Technology Corporation. UO TYPICAL APPLICATI 2-Quadrant Multiplying DAC Has Less Than 0.5LSB (Typ) Total Unadjusted Error Integral Nonlinearity Over Temperature VIN 1.0 0.1µF WR CS 17 16 18 19 20 RFB VDD VREF 1 OUT1 LTC7545A AGND 2 DGND 4–15 3 33pF – LT ®1097 + VOUT INTEGRAL NONLINEARITY (LSB) 5V 0.5 TA = 85°C TA = 25°C 0 TA = –40°C –0.5 7545A TA01 –1.0 0 512 1024 1536 2048 2560 3072 3584 4095 DIGITAL INPUT CODE 7545A TA02 1 LTC7545A W U U W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO RATI GS VDD to AGND ............................................ –0.5V to 17V VDD to DGND ............................................. –0.5V to 17V AGND to DGND .............................. – 0.5V to VDD + 0.5V DGND to AGND .............................. – 0.5V to VDD + 0.5V VREF to AGND,DGND ............................................. ±25V RFB to AGND,DGND ............................................. . ±25V Digital Inputs to DGND ................. – 0.5V to VDD + 0.5V VOUT1 to AGND, DGND ................. – 0.5V to VDD + 0.5V Maximum Junction Temperature .......................... 150°C Operating Temperature Range Commercial (K, L Versions) .................... 0°C to 70°C Industrial (B, C Versions)................... –40° C to 85°C Storage Temperature Range ................ –65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW OUT1 1 20 RFB AGND 2 19 VREF DGND 3 18 VDD DB11 (MSB) 4 17 WR 16 CS DB10 5 DB9 6 15 DB0 (LSB) DB8 7 14 DB1 DB7 8 13 DB2 DB6 9 12 DB3 DB5 10 11 DB4 N PACKAGE 20-LEAD PDIP LTC7545ABN LTC7545ABSW LTC7545ACN LTC7545ACSW LTC7545AKN LTC7545AKSW LTC7545ALN LTC7545ALSW SW PACKAGE 20-LEAD PLASTIC SO WIDE TJMAX = 150°C, θJA = 100°C/W (N) TJMAX = 150°C, θJA = 130°C/W (SW) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VDD = 5V or 15V, VREF = 10V, VOUT1 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER LTC7545AK/AB MIN TYP MAX CONDITIONS LTC7545AL/AC MIN TYP MAX UNITS Accuracy Resolution INL DNL GE ILKG PSRR ● Integral Nonlinearity (Relative Accuracy) (Note 1) TA = 25°C TMIN to TMAX Differential Nonlinearity Guaranteed Monotonic TA = 25°C TMIN to TMAX TMIN to TMAX Gain Error (Note 2) TA = 25°C TMIN to TMAX Gain Temperature Coefficient (Note 3) ∆Gain/∆Temperature OUT1 Leakage Current (Note 4) TA = 25°C TMIN to TMAX Power Supply Rejection 12 12 Bits ● ±0.5 ±0.5 ±0.5 ±0.5 LSB LSB ● ±1 ±1 ±0.5 ±0.5 LSB LSB ● ±2 ±3 ±1 ±2 LSB LSB 5 ppm/°C 1 ● 5 1 ● ±10 ±50 ±10 ±50 ● ±0.002 ±0.002 nA nA %/% Reference Input RREF VREF Input Resistance (Note 5) ● 8 11 15 8 11 15 kΩ Output Current Settling Time (Notes 3, 6, 7) ● 1 1 µs Propagation Delay (Notes 3, 6, 8) ● 150 150 ns Digital-to-Analog Glitch Impulse (Notes 6, 9) ● 5 5 nV-sec Multiplying Feedthrough Error VREF = ±10V, 10kHz Sine Wave ● 5 5 mVP-P DB0 to DB11 = 0V, WR, CS = 0V COUT1 ● 30 70 30 70 pF DB0 to DB11 = VDD, WR, CS = 0V COUT1 ● 60 150 60 150 pF AC Performance Analog Outputs COUT 2 Output Capacitance (Note 3) LTC7545A ELECTRICAL CHARACTERISTICS VDD = 5V, VREF = 10V, VOUT1 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN ALL GRADES TYP MAX UNITS Digital Inputs VIH Digital Input High Voltage ● VIL Digital Input Low Voltage ● IIN Digital Input Current CIN Digital Input Capacitance 2.4 0.001 ● (Note 3) VIN = 0V V ● 0.8 V ±1 µA 8 pF Timing Characteristics (Note 3) tCS CS to WR Setup Time ● 100 ns tCH CS to WR Hold Time ● 0 ns tWR Write Pulse Width ● 100 ns tDS Data Setup Time ● 100 ns tDH Data Hold Time ● 5 ns ● 4.75 Power Supply VDD Supply Voltage IDD Supply Current All Digital Inputs = VIH or VIL All Digital Inputs = 0V or VDD ● ● 5 5.25 V 10 2 100 mA µA ALL GRADES TYP MAX UNITS VDD = 15V, VREF = 10V, VOUT1 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN Digital Inputs VIH Digital Input High Voltage ● VIL Digital Input Low Voltage ● 1.5 V IIN Digital Input Current ● ±1 µA CIN Digital Input Capacitance ● 8 pF (Note 3) VIN = 0V 13.5 V Timing Characteristics (Note 3) tCS CS to WR Setup Time ● 75 ns tCH CS to WR Hold Time ● 0 ns tWR Write Pulse Width ● 75 ns tDS Data Setup Time ● 60 ns tDH Data Hold Time ● 5 ns VDD Supply Voltage ● 14.25 IDD Supply Current Power Supply All Digital Inputs = VIH or VIL All Digital Inputs = 0V or VDD The ● denotes specificatons which apply over the full operating temperature range. Note 1: ±0.5LSB = ±0.012% of full scale. Note 2: Using internal feedback resistor. Note 3: Guaranteed by design, not subject to test. Note 4: IOUT1 with DAC register loaded to all 0s. ● ● 15 15.75 10 2 100 V mA µA Note 5: Typical temperature coefficient is 100ppm/°C. Note 6: OUT1 load = 100Ω in parallel with 13pF. Note 7: To 0.01% for a full-scale change, measured from the falling edge of WR, CS = 0V. Note 8: From digital input change to 90% of final analog output. Note 9: VREF = 0V. DAC register contents changed from all 0s to all 1s or all 1s to all 0s. 3 LTC7545A W BLOCK DIAGRAM 20k 20k 20k VREF 19 20 RFB 40k 40k 40k 40k 40k 40k 40k 10k 1 OUT1 2 AGND VDD 18 DECODER 3 DGND WR 17 LOAD INPUT DATA LATCHES CS 16 4 5 6 7 DB11 (MSB) DB10 DB9 DB8 • • • • • • • 15 DB0 (LSB) WU W TI I G DIAGRA tCS tCH CS tWR WR tDS DATA IN DB0 to DB11 tDH DATA VALID 7545A TD 4 7545A BD LTC7545A U TYPICAL APPLICATIONS N Unipolar Operation (2-Quadrant Multiplication) VREF –10V TO 10V 5V OR 15V 0.1µF 19 18 20 VDD VREF RFB 17 16 µP WR CS LTC7545A DB11 to DB0 4–15 OUT1 AGND DGND 3 33pF 1 – 2 + LT1097 VOUT 0V TO – VREF 7545A TA03 Table 1. Unipolar Binary Code Table DIGITAL INPUT BINARY NUMBER ANALOG OUTPUT IN DAC LATCH VOUT MSB LSB 1111 1111 1111 – VREF (4095/4096) 1000 0000 0000 – VREF (2048/4096) = – VREF/2 0000 0000 0001 – VREF (1/4096) 0000 0000 0000 0V 5 LTC7545A U TYPICAL APPLICATIONS N Bipolar Operation (4-Quadrant Multiplication) VREF –10V TO 10V R2 20K R3 20K 5V OR 15V 0.1µF 19 18 20 VDD VREF RFB 17 16 µP WR CS LTC7545A DB11–DB0 4–15 OUT1 AGND DGND 3 33pF – 1 2 R1 10K 1/2LT1112 + – 1/2LT1112 VOUT + 7545A TA04 Table 2. Bipolar Offset Binary Code Table DIGITAL INPUT BINARY NUMBER IN DAC LATCH MSB 1111 1000 1000 0111 0000 6 1111 0000 0000 1111 0000 LSB 1111 0001 0000 1111 0000 ANALOG OUTPUT VOUT VREF (2047/2048) VREF (1/2048) 0V –VREF (1/2048) –VREF (2048/2048) = –V REF LTC7545A U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package 20-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.040* (26.416) MAX 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 0.045 – 0.065 (1.143 – 1.651) 0.015 (0.381) MIN 0.065 (1.651) TYP 0.005 (0.127) MIN 0.100 ± 0.010 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) ( +0.635 8.255 –0.381 ) 0.125 (3.175) MIN Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0.018 ± 0.003 (0.457 ± 0.076) N20 0695 7 LTC7545A U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. SW Package 20-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.496 – 0.512* (12.598 – 13.005) 20 19 18 17 16 15 14 13 12 11 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 × 45° (0.254 – 0.737) 1 2 3 4 5 6 7 8 9 10 0.037 – 0.045 (0.940 – 1.143) 0.093 – 0.104 (2.362 – 2.642) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) TYP 0.004 – 0.012 (0.102 – 0.305) 0.014 – 0.019 (0.356 – 0.482) TYP S20 (WIDE) 0695 NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER LTC1257 LTC1450/LTC1450L LTC1451/LTC1452/LTC1453 LTC7541A LTC7543/LTC8143 LTC8043 8 DESCRIPTON Complete Serial I/O VOUT 12-Bit DAC Complete Parallel Input VOUT 12-Bit DACs Complete Serial I/O VOUT 12-Bit DACs Parallel I/O Multiplying IOUT 12-Bit DAC Serial I/O Multiplying IOUT 12-Bit DACs Serial I/O Multiplying IOUT 12-Bit DAC Linear Technology Corporation COMMENTS 5V to 15V Single Supply in 8-Pin SO and PDIP Rail-to-Rail VOUT, 3V/5V Single Supply, 12-Bit or (8 + 4) Bit Loading Rail-to-Rail VOUT, 3V/5V Single Supply in 8-Pin SO and PDIP 12-Bit Wide Parallel Input Clear Pin and Serial Data Output (LTC8143) 8-Pin SO and PDIP LT/GP 0596 10K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1996