SANYO LV0229XA

Ordering number : ENA2144
Monolithic Linear IC
LV0229XA
For Optical Pickups
Front Monitor OE-IC
Overview
The LV0229XA is a front monitor optoelectronic IC for optical pickups that has a built-in photo diode compatible with
three waveforms. LV0229XA is small size and type CSP packages.
Functions
• Pin photodiode compatible with three wavelengths incorporated.
• Gain adjustment (-5dB to +5dB in 256 steps) through serial communication.
• Amplifier to amplify differential output.
Features
• Photodiode compatible with three wavelengths incorporated, high-speed process employed.
• Compact, thin CSP package employed.
• Use AR coated glass for three-wavelength (One side).
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VCC
6
Allowable power dissipation
Pd
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-40 to +100
°C
substrate *1, Ta = 75°C
105
V
mW
*1: Glass epoxy both-side substrate 55mm × 45mm × 1mm, Copper foil area (head: about 85% tail: about 70%)
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,
safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives
in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any
guarantee thereof. If you should intend to use our products for new introduction or other application different
from current conditions on the usage of automotive device, communication device, office equipment, industrial
equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the
intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely
responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer ' s products or
equipment.
O3112NKPC 20121009-S00002 No.A2144-1/8
LV0229XA
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
Ratings
Conditions
min
Unit
typ
max
Operating supply voltage
VCC
4.5
5
5.5
V
Output load capacitance
Co
12
20
33
pF
Output load resistance
Zo
3
kΩ
Electrical and Optical Characteristics at Ta = 25°C, VCC = 5V, RL = 6kΩ, CL = 20pF
Parameter
Symbol
Conditions
Ratings
IV Gain
min
Current dissipation
ICC
Sleep current
Islp
Output voltage when shielded
Vc
At shielding
Output offset voltage
Vofs
At shielding, voltage between
Temperature dependence of offset voltage *1
Vofs
Ta = -10 to +75°C
Optical output voltage *1
VLC
Voltage between VOP-VON
VH1C
typ
9
Unit
max
14
19
mA
mA
0.2
0.5
1.85
2
2.15
-30
0
30
mV
μV/°C
V
VOP-VON
Low
λ = 780nm, G = 0dB
VH2C
VLD
VH1D
λ = 650nm, G = 0dB
VH2D
VLB
VH1B
λ = 405nm, G = 0dB
VH2B
Light output voltage adjustment range *1
G
-60
0
60
1.93
2.41
2.90
Middle
4.58
5.73
6.87
High
10.86
13.58
16.29
Low
2.03
2.54
3.05
Middle
4.82
6.02
7.23
High
11.42
14.28
17.13
Low
1.27
1.59
1.90
Middle
3.01
3.76
4.52
High
7.14
8.92
10.71
4.5
5
5.5
G = 0dB reference, absolute value of
mV/μW
dB
adjustment width
Output saturation voltage *1
VoD
Voltage between VOP-VON
Frequency characteristics *1, *2
FcC
-3dB (1MHz reference), λ = 780nm
2000
mV
40
60
60
85
50
70
60
85
50
70
Light input = 40μW (DC) + 20μW (AC)
FcD1
-3dB (1MHz reference), λ = 650nm
Light input = 40μW (DC) + 20μW (AC)
FcD2
-3dB (1MHz reference), λ = 650nm
Light input = 40μW (DC) + 20μW (AC)
FcB1
-3dB (1MHz reference), λ = 405nm
Light input = 40μW (DC) + 20μW (AC)
FcB2
-3dB (1MHz reference), λ = 405nm
Light input = 40μW (DC) + 20μW (AC)
Settling time *1
Tset
Response time *1
Tr, Tf
Low
Middle
High
Low
MHz
Middle
High
10
15
ns
4
10
ns
-1
0
1
%
%
Vo = 0.9Vp-p, output level 10 to 90%
fc = 10MHz, duty = 50%
Linearity *1
Lin
At output voltage 0.5V and 1.0V
(Between VOP-VON)
Light-output voltage temperature dependence
TC
λ = 780nm, 25°C reference
4
7
10
Voltage between VOP-VON *1, *3
TD
λ = 650nm, 25°C reference
-3
0
3
%
TB
λ = 405nm, 25°C reference
-4
-1
2
%
Item with *1 mark indicate the design reference value.
Item with *2 mark indicate the frequency characteristics when VOP and VON are applied individually.
The frequency characteristics are for the output voltage adjustment range is -5 to +5dB.
Item with *3 mark indicates the temperature dependence for the case of High / Middle / Low gain and for the case when the temperature is 25 to 75°C for the
output voltage adjustment range of -5 to +5dB.
[Expression of output voltage]
Vn = (sensitivity / 1.78) × 5221 / (5221 - 14 × GCAstep) × light intensity (μW)
No.A2144-2/8
LV0229XA
Package Dimensions
unit : mm (typ)
3446
BOTTOM VIEW
SIDE VIEW
1.23
B
0.225
C
0.225
C
B
A
0.67 MAX
A
0.39
0.225
0.45
1.35
1 2 3 4 5
0.2
1 2 3 4 5
TOP VIEW
0.08
(0.52)
SIDE VIEW
SANYO : ODCSP8(1.35X1.23)
Pin Assignment
1
A
2
3
SCLK
4
5
VCC
SEN
PD
B
SSEL
Pin No.
Pin name
A1
SCLK
Serial communication Clock pin
Function
A3
SEN
Serial communication Enable pin
A5
VCC
Power supply voltage pin
B2
SSEL
Register selection pin
SSEL = Low : Address 00 to 0Fh used
VOP
SSEL = High : Address 10 to 1Fh used
SSEL = Open : Address 70 to 7Fh used
C
SDIO
GND
TOP VIEW
VON
B4
VOP
Positive side output pin
C1
SDIO
Serial communication Data pin
C3
GND
GND pin
C5
VON
Negative side output pin
No.A2144-3/8
LV0229XA
PD assignment
0.615
1.35
0.26
1.23
Center of chip
Center of PD
PD Size
0.4 × 0.4
*PD size for reference to be used for design
(Unit : mm)
0.675
Block diagram and Test circuit diagram
VCC
SEN
SCLK
SDIO
SSEL
Control
Serial
0.1μF
VCC
High
Vref
Middle
Bias
Regulator
Low
Vref
+
VoVref
20pF
GND
6kΩ
+
20pF
Vo+
-
* Please place decoupling capacitors within 3mm from pin
No.A2144-4/8
LV0229XA
Resister table
Enable selection of the register group from the SSEL pin.
SSEL = Low
Address
7
6
5
4
Name
POWER
Default
00
00
11: Power on
00/01: High
00/01/10: Sleep
10: Middle
00h
Value
3
2
1
0
0
0
0
0
1
1
1
1
3
2
1
0
0
0
0
0
1
1
1
1
3
2
1
0
0
0
0
0
1
1
1
1
IV GAIN SEL
11: Low
Name
GAIN
Default
01h
1
1
1
1
Value
00000000 to 11111111
Name
0Eh
TEST1 (*1)
SSEL = High
Address
7
6
5
4
Name
POWER
Default
00
00
11: Power on
00/01: High
00/01/10: Sleep
10: Middle
10h
Value
IV GAIN SEL
11: Low
Name
GAIN
Default
11h
1
1
1
1
Value
00000000 to 11111111
Name
1Eh
TEST1 (*1)
SSEL = Open
Address
7
6
5
4
Name
POWER
Default
00
00
11: Power on
00/01: High
00/01/10: Sleep
10: Middle
70h
Value
IV GAIN SEL
11: Low
Name
Default
GAIN
71h
1
1
Value
Name
1
1
00000000 to 11111111
7Eh
TEST1 (*1)
*1 TEST1 are either the time when power is applied or “00000000” is set. Do not attempt to change “00000000” during operation.
“00000000” is returned when reading is made.
*2 No problem in terms of operation occurs even when writing is made to the address 02h to 0Dh & 0Fh, 12h to 1Dh & 1Fh and 72h to 7Dh & 7Fh.
“00000000” is returned when this address is read.
*3 When I performed address reading except the register group set by an SSEL terminal, I keep Hi-Z without paying a value.
No.A2144-5/8
LV0229XA
Serial protocol
WRITE timing chart
(HOST) SEN
1
2
3
4
5
6
7
A6
A5
A4
A3
A2
A1
8
9
10
LSB
MSB
A0
D7
11
12
13
14
15
16
(HOST) SCLK
MSB
A7
(HOST) SDIO
Mode
LSB
D6
D5
Address
D4
D3
D2
D1
D0
15
16
Data
(Output Data from Host)
READ timing chart
(HOST) SEN
1
2
3
4
5
6
7
8
A6
A5
A4
A3
A2
A1
LSB
A0
9
10
11
12
13
14
(HOST) SCLK
MSB
A7
(HOST) SDIO
Mode
Address
MSB
D7
SDIO
D6
D5
D4
D3
D2
D1
LSB
D0
Data
(Output Data from OP device)
SDIO pin load / CL = 20pF. The table below shows the design reference value.
Parameter
Symbol
SCL clock frequency Write
fSCL
Min.
Typ.
Max.
Unit
0
10
MHz
4
MHz
SCL clock frequency Read
fSCL
0
SDIO data setup time
tDSU
50
ns
SDIO data hold time
tDHO
50
ns
SDIO output delay
tDDLY
SEN “H” period
tENH
1.6
μs
SEN “L” period
tENL
200
ns
SCL rise time after SEN rise
tSTA
60
ns
SEN fall time after final SCL rise
tSTO
100
Serial input “H” voltage
VIH
2.4
10
80
ns
ns
VCC
V
Serial input “L” voltage
VIL
0.6
V
SDIO output “H” voltage
VOH
2.5
2.9
3.3
V
SDIO output “L” voltage
VOL
0
0.3
0.8
V
WRITE
tENL
tENH
(HOST) SEN
tSTA
tSTO
(HOST) SCLK
(HOST) SDIO
tDSU
tDHO
READ
(HOST) SEN
(HOST) SCLK
(HOST) SDIO
tDDLY
SDIO
No.A2144-6/8
LV0229XA
Pin
SDIO
Type
Equivalent circuit diagram
Input
3V
3V
Output
125kΩ
125kΩ
100kΩ
VOP
Output
VON
20Ω
SCLK
Input
3V
SEN
100kΩ
SSEL
Input
800kΩ
200kΩ
5kΩ
200kΩ
No.A2144-7/8
LV0229XA
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
Regarding monolithic semiconductors, if you should intend to use this IC continuously under high temperature,
high current, high voltage, or drastic temperature change, even if it is used within the range of absolute
maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a
confirmation.
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This catalog provides information as of October, 2012. Specifications and information herein are subject
to change without notice.
PS No.A2144-8/8