Ordering number : ENA0584 Bi-CMOS LSI LV5254LG Inverting Charge Pump Regulator IC Overview The LV5254LG is an inverting charge pump regulator IC. Functions • Inverting charge pump regulator Specifications Absolute Maximum Ratings at Ta = 25°C, SGND and PGND = 0V Parameter Symbol Input supply voltage VDD max VS pin input voltage Conditions Ratings SVDD = PVDD Unit 6.5 V VS max 6.5 V STBY pin input voltage STBY max 6.5 V S1 and S2 pin input voltage S1, S2 max 6.5 V Maximum output current IOUT 110 mA Operating temperature Topr -20 to +85 °C Storage temperature Tstg -40 to +125 °C Recommended Operating Conditions at Ta = 25°C, SGND and PGND = 0V Parameter Symbol Input supply voltage VDD VS pin input voltage VS Output current IOUT Conditions SVDD = PVDD Ratings Unit 3.5 to 6 V 1 to 4.5 V 100 mA Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 31407 MS PC 20060915-S00004 No.A0584-1/14 LV5254LG Electrical Characteristics (a) Electrical Characteristics Ta = 25°C, SVDD and PVDD = 4.6V, SGND and PGND = 0V, CLK = 2MHz, unless otherwise specified. Parameter Symbol Ratings Conditions min Output ripple Vrp typ Unit max C2, C5 = 1μF, IO = 60mA 20 mVp-p Iddstby Operating VDD current 1 Iddope1 IO = 0mA 2.2 mA Operating VDD current 2 Iddope2 IO = 60mA 3.2 mA Power efficiency Peff 1 μA Standby mode VDD current VDD = 4.6V, VOUT = -2.8V, IOUT = 60mA 57.5 Reference voltage VREF 1.262 Overcurrent protection threshold IOCP 115 1.300 % 1.339 V mA current Overcurrent protection latch off wait tOCP Fclk = 2MHz 6 Regulator output on time tregon Fclk = 2MHz 3.5 Internal clock frequency* fclk Thermal shutdown circuit operating TSD ms time ms 2 Design guarantee MHz °C 170 temperature Ω VOUT discharge resistance RDIS VS pin input resistance RVS 180 280 480 kΩ RSHD 100 170 300 kΩ VthH 1.6 VDD V VthL 0 0.3 V VthH 0.7VDD VDD V VthL 0 0.3 V STBY pin pull-down resistance STBY pin control voltage S1 and S2 pin control voltage 650 * : The charge pump operating frequency, Fcp, is the internal clock frequency divided by two, i.e. Fclk/2. (b) Output Characteristics Ta = 25°C, SVDD and PVDD = 4.6V, SGND and PGND = 0V, CLK = 2MHz, unless otherwise specified. Fixed Output Voltage (Vout = -2.8V) Mode Outputs a fixed voltage of -2.8V determined by an internal resistor. Parameter Symbol Ratings Conditions min Input supply voltage VDD SVDD = PVDD typ 4.37 Output voltage precision VOUT VDD = +4.37 to +4.83V IOUT = 60mA Maximum output current IOUT VDD = +4.37 to +4.83V VOUT = -2.8V -2.884 -2.8 Unit max 4.83 V -2.716 V 70 mA VS Mode Outputs a voltage that is -1 times the voltage VS input to the VS pin. Parameter Symbol Ratings Conditions min VS pin input voltage VS pin output voltage range VS VOUT typ 1 *1 -4.5 Unit max 4.5 V -1 V Output voltage precision VS = 1 to 2V, IOUT = 0 to 60mA -1.05VS -VS -0.95VS V Output voltage precision VS = 2 to 4.5V, IOUT = 0 to 60mA -1.03VS -VS -0.97VS V No.A0584-2/14 LV5254LG External Setting Mode Outputs a voltage determined by external resistors and the external reference voltage. See page 8, External Setting Mode Applications and the Output Voltage Setting Method for the method for setting the VOUT voltage. Parameter Symbol Ratings Conditions min Output voltage range VOUT *1 FB pin voltage VFB VDD = 5V, IOUT = 0 to 100mA FB pin current IFB VDD = 5V, IOUT = 0 to 100mA Unit typ max -4.5 -1 V -5 20 mV 200 nA 70 *1 : The VOUT range that can be set and the current drive capacity of the charge pump regulator are, in principle, determined by the relationship between the values of the VDD voltage and the set voltage. (See the "Relationship Between the Input and Output Voltages" ) Contact your SANYO Semiconductors representative for more detailed information. Logic Function Tables The pins S1 and S2 must be connected to VDD (high) or ground (low) according to the mode to be used. Mode Description S1 S2 High Low Mode 1 Outputs a fixed voltage of -2.8V determined by an internal resistor. Mode 2 Outputs a voltage that is -1 times the voltage VS input to the VS pin. Low High Mode 3 Outputs a voltage determined by an external resistor and the external reference voltage. High High Package Dimensions Bottom View Top View 3.0 2 3 1 0.5 3.0 4 5 0.5 0.5 E C B A 0.5 Pd max – Ta 0.8 Specified board : 50×40×0.8mm3 glass epoxy 4-layer (2S2P) printed circuit board 0.7 0.6 0.4 0.2 0 – 20 0 20 40 60 80 100 Ambient temperature, Ta – °C 0.05 0.0NOM Side View D 0.8 0.3 Allowable power dissipation, Pd max – mW unit : mm (typ) 3330 SANYO : FLGA24(3.0X3.0) No.A0584-3/14 LV5254LG Pin Assignment FLGA24 (3mm×3mm) E D C B S2 6 5 7 4 3 SVDD 9 SGND VREF 1 STBY S1 2 FB VS 2 VOUT 3 22 23 20 21 16 19 PVDD 11 4 10 14 C1+ 12 1 24 TEST 8 A 13 C1- PGND 15 17 C2 5 18 TOP VIEW Pin Descriptions Pin No. Pin 9 SVDD Small signal system VDD Functions 11 PVDD Power system VDD 1 SGND Small signal system ground 15 PGND Power system ground 13 C1+ Inversion capacitor connection (driver side) 17 C1- Inversion capacitor connection (charge transfer side) 18 C2 21 VOUT 24 VREF 22 FB Feedback pin 23 VS VS mode output setting 2 STBY 4 S1 Sensing mode selection 1 3 S2 Sensing mode selection 2 8 TEST Charge pump output Regulator output Band gap voltage output Standby mode control Test mode enable (normally not used) * : The test mode enable pin must be left open. (There is a built-in pull-down resistor, and this pin should always be low.) No.A0584-4/14 LV5254LG Block Diagram and Application Circuit Example 1 (Internal fixed-voltage mode) C4 = 10μF PVDD SVDD Charge Pump Thermal Shutdown OSC VDD C1+ C1 = 1μF C1Clock Driver SGND PGND Discharge VOUT VOUT Overcurrent Protection C5 = 1μF C2 Output Tr TEST C6 C2 = 1μF Error Amplifier + STBY VREF − FB OFF ON VREF C3 = 0.1μF S1 S2 VDD VS • Use ceramic capacitors for the external capacitors and connect them as close as possible to the IC. We recommend using class B devices with excellent temperature characteristics.) • Use capacitors with the same values for the charge pump capacitors C1 and C2. We recommend a capacitance of 1μF for C1 and C2. (See figure 4 on page 10) • SVDD and PVDD must be at the same potential. Short them together with the shortest possible line and use a ceramic capacitor with a value of 1μF or greater for C4 (which is inserted between this point and PGND). C4 must be mounted as close as possible to the IC. • C6 is a phase compensation capacitor. It is required for stable regulator operation. No.A0584-5/14 LV5254LG Application Circuit Example 2 (VS mode) C4 = 10μF PVDD SVDD Charge Pump Thermal Shutdown OSC VDD C1+ C1 = 1μF C1Clock Driver SGND PGND Discharge VOUT VOUT Overcurrent Protection C5 = 1μF C2 Output Tr TEST C6 C2 = 1μF Error Amplifier + STBY VREF − FB OFF ON VREF S1 VS S2 C3 = 0.1μF VS VDD Application Circuit Example 3 (External setting mode) C4 = 10μF PVDD SVDD Charge Pump Thermal Shutdown OSC VDD C1+ C1 = 1μF C1Clock Driver SGND PGND Discharge VOUT VOUT Overcurrent Protection C5 = 1μF C2 Output Tr TEST C2 = 1μF Error Amplifier R2 C6 + STBY VREF − FB R1 OFF ON VREF S1 S2 Vref_ext C3 = 0.1μF VS VDD No.A0584-6/14 LV5254LG Recommended Power On and Off Sequences VDD SVDD (pin 9) PVDD (pin 11) VS (pin 23) : VS mode or VREF_ext (external reference voltage) External setting mode STBY (pin 2) CP CLK (1MHz) (1) (2) (3) (4) (5) (6) (7) (8) (9) CP output C2 (pin 18) -VDD tpre : 0.5ms tsoft : 2ms ton : 1ms tregon : 3.5ms Regulator output VOUT (pin 21) VOUT (1) Apply the VDD voltage to the SVDD and PVDD pins. (2) If VS mode is used, apply the VS voltage. If external setting mode is used, apply the external reference voltage. (3) Start pre-charging the flying capacitor with a high-level input to the STBY pin. (4) Start charging the pump-up capacitor with the charge pump sub-driver (soft start). (5) Switch to the charge pump driver. This starts charging of the pump-up capacitor by the main driver. (6) Regulator output starts. (7) Stop IC drive by applying a low-level input to the STBY pin to start VOUT output discharge operation by the internal discharge transistor. (This operates when the STBY pin is low.) (8) If VS mode is used, shut down the VS voltage, and if external setting mode is used, shut down the external reference voltage. (9) Shut down the VDD voltage. No.A0584-7/14 LV5254LG Overcurrent Protection Operation This IC includes a function that protects against overcurrent in VOUT. If the VOUT output is shorted and a large current flows, the IC will latch and stop the output. To recover from this stopped state, set the STBY pin low and then set it high again. External Setting Mode Applications and the Output Voltage Setting Method In the LV5254's external setting mode, the output voltage is set by the external resistors R1 and R2 and by the external reference voltage, Vref_ext. In this mode, the output voltage is expressed by equation (1). The second term in equation (1) is the error amplifier's offset component and the third term is the offset component due to the feedback current. The voltage precision achieved by an application can be determined by considering the tolerances of the parameters in equation (1). R1 Vref_ext VFB C6 IFB R2 FB VOUT VOUT C5 R2 R1+R2 VOUT = -R1 ⋅Vref_ext+ R1 ⋅VFB-R2⋅IFB … (1) No.A0584-8/14 LV5254LG Relationship Between the Input and Output Voltages Equation (2) gives the relationship between the input voltage and output voltage. In the LV5254, a charge pump circuit generates VC2, which is the VIN level inverted, and generates the output voltage VOUT by regulating that inverted voltage. In this case, due to the charge pump block impedance Ron, the voltage drop IO × Ron (where IO is the load current) is generated. (* Here we are ignoring the capacitor loss components in the charge pump capacitors C1 and C2.) The LV5254's current capacity is expressed by equation (3). At this time, the impedance Ron increases with temperature. Thus the current capacity decreases with increasing temperature. Input voltage VIN CP output voltage VC2 CP Regulator output VOUT Regulator Ron × IOUT ΔVreg Voltage drop due to the charge pump block impedance Voltage drop in the regulator block IOUT Load current Iout VOUT = VC2+ΔVreg = (-VIN+Ron×IOUT)+ΔVreg … (2) VOUT : Output voltage, VIN : Input voltage, IOUT : Load current, Ron : Charge pump block impedance, ΔVreg : Regulator voltage drop IO [max] = (VIN+VOUT-ΔVreg [min]) / Ron … (3) IO [max] : Maximum load current, ΔVreg [min] : Minimum regulator voltage drop Ron – Ta 19 VDD = 5V CP on-resistance, Ron – Ω 18 17 16 15 14 13 12 – 20 0 20 40 60 80 90 Ambient temperature, Ta – °C Figure 1 : Charge Pump Block Impedance Temperature Characteristics : Assumed Worst Case (C1, C2 = 1μF) No.A0584-9/14 LV5254LG Next, consider figure 2, which shows the relationship between the input voltage VIN and the charge pump block impedance Ron at Ta = 85°C, which is the maximum temperature for which operation is guaranteed. At Ta = 85°C, if ΔVreg [min] = 0.3V (inferred worst case value), the LV5254's maximum output current can be expressed as equation (4). IO [max] = (VIN+VOUT-0.3) / Ron … (4) The current capacity shown in figure 3 can be determined from the characteristics in figure 2 when VOUT is set to be -3V. IO max – VIN Ron – VIN Figure 2 Figure 3 120 25 23 21 19 17 15 3.5 4 Ta = 85°C Maximum output current, IO max – mΑ CP on-resistance, Ron – Ω Ta = 85°C 4.5 5 5.5 100 80 60 40 20 0 3.5 6 4 4.5 5 5.2 Input voltage, VIN – V Input voltage, VIN – V Figure 2 : Charge Pump Block Impedance Input Voltage Characteristics (Ta = 85°C) : Assumed Worst Case (C1, C2 = 1μF) Figure 3 : Maximum Output Current - Input Voltage Characteristics when VOUT = -3V (Ta = 85°C) : Assumed Worst Case (C1, C2 = 1μF) Caution : The characteristics values presented in this reference documentation are nothing other than inferred worst-case values. No guarantee or warranty is made with respect to these values. Loss in the Charge Pump Capacitors Voltage loss occurs in the pump capacitors C1 and C2 in the charge pump circuit. Figure 4 shows the charge pump output vs. load current characteristics (with the C1 and C2 value as a parameter) at room temperature when VDD = 5V. Note that the load regulation becomes worse as the value of the capacitors C1 and C2 is reduced. To minimize the loss in these capacitor, we recommend using a value of 1μF for C1 and C2. Charge Pump Output – Load Current Characteristics Charge pump output, VC2 – V – 3.6 – 3.8 F 2μ –4 2 ,C = C1 – 4.2 0.2 , C1 = C2 2 ,C F 1μ F 7μ .4 =0 C1 – 4.4 – 4.6 – 4.8 –5 0 20 40 60 80 100 Load current, IO – mA Figure 4 : Charge Pump Output - Load Current Characteristics when VDD = 5V, data provided for reference purposes. No.A0584-10/14 LV5254LG IC start and stop 1. Startup waveform (External setting mode) Ta = 27°C VDD = 5V IOUT = 0mA Ta = 27°C VDD = 5V IOUT = 60mA 1 STBY 1.6V STBY 2.00V/S VREF 1 2 2 1 STBY VREF 1.6V STBY 2.00V/S 1 2 2 VREF 1.00V/S VREF 1.00V/S 3,4 3 VOUT 2.00V/S -2.9V VOUT 3,4 3 VOUT 2.00V/S -2.9V VOUT -4.4V -5V C2 CP output 4 C2 2.00V/S 4msec C2 CP output 4 C2 2.00V/S 4msec 1ms/s 1ms/s (a) No load - Startup waveform (b) 50Ω - Startup waveform 2. Falling waveform (External setting mode) Ta = 27°C VDD = 5V IOUT = 0mA Ta = 27°C VDD = 5V IOUT = 60mA 1 1 STBY 2.00V/S 1 2 2 VREF 1.00V/S STBY 2 2 VREF 1.00V/S VOUT 3,4 VOUT 2.00V/S 1 VREF 0V 3 STBY 2.00V/S VREF 0V VOUT 3,4 3 -2.9V VOUT 2.00V/S -2.9V STBY -4.4V -5V 4 C2 2.00V/S C2 CP output 3msec C2 CP output 4 C2 2.00V/S 3msec 1ms/s 1ms/s (a) No load - Falling waveform (b) 50Ω - Falling waveform Internal fixed mode - Regulator Load regulation - Internal fixed mode VDD = 4.6V Efficiency - Internal fixed mode VDD = 4.6V – 2.7 70 – 2.725 Ta = 90°C 60 – 2.75 Room temperature Output voltage, VOUT – V Output voltage, VOUT – V VDD = 4.6V Room temperature Ta = -20°C – 2.775 Ta = 90°C – 2.8 – 2.825 – 2.85 Ta = -20°C 50 40 30 20 10 – 2.875 – 2.9 0 0 10 20 30 40 50 Load current, IOUT – mA 60 70 0 10 20 30 40 50 60 70 Load current, IOUT – mA No.A0584-11/14 LV5254LG VS mode - Regulator VS mode (VS = 1V) Load regulation VDD = 5V VS mode (VS = 2.5V) Load regulation VDD = 5V – 0.95 – 2.4 Output voltage, VOUT – V Output voltage, VOUT – V – 0.9 – 2.45 Ta = 0°C Ta = 30°C Ta = 60°C –1 Ta = 90°C Ta = -30°C Ta = 30°C Ta = 60°C Ta = 90°C – 2.5 – 2.55 – 1.05 – 1.1 – 2.6 0 20 40 60 80 100 0 20 Load current, IOUT – mA VS mode (VS = 3.3V) Load regulation VDD = 5V 60 80 100 VS mode (VS = 4.5V) Load regulation VDD = 6V Ta = 60°C Ta = 30°C – 4.45 Ta = 0°C Ta = 90°C – 3.3 – 4.4 Output voltage, VOUT – V Output voltage, VOUT – V Ta = 60°C Ta = 30°C – 3.25 40 Load current, IOUT – mA – 3.2 Ta = -30°C – 3.35 Ta = 0°C Ta = 90°C – 4.5 Ta = -30°C – 4.55 – 3.4 – 4.6 0 20 40 60 80 0 20 Load current, IOUT – mA VS mode (VS = 2.5V) Line regulation characteristics IOUT = 60mA 60 80 VS mode (VS = 1V) Line regulation characteristics IOUT = 60mA – 0.95 Output voltage, VOUT – V – 2.475 – 0.975 Ta = Room temperature Ta = -30°C Ta = 90°C – 2.5 – 2.525 – 2.55 4.5 40 Load current, IOUT – mA – 2.45 Output voltage, VOUT – V Ta = 0°C Ta = -30°C Ta = -30°C –1 Ta = 90°C Ta = Room temperature – 1.025 5 5.5 Intput voltage, VDD – V 6 – 1.05 3.5 4 4.5 5 5.5 6 Intput voltage, VDD – V No.A0584-12/14 LV5254LG External Setting Mode Applications and the Output Voltage Setting Method VDD = 5V R1 = 82kΩ R2 = 240kΩ Vref_ext = 1V Output voltage, VOUT – V – 2.89 – 2.9 Ta = 60°C – 2.91 Line regulation characteristics IOUT = 60mA VDD = 5V R1 = 82kΩ R2 = 240kΩ Vref_ext = 1V – 2.89 – 2.9 Ta = 0°C Ta = 30°C – 2.91 Ta = 30°C Ta = -30°C – 2.92 Ta = 90°C – 2.93 – 2.88 Output voltage, VOUT – V Load regulation characteristics – 2.88 – 2.92 Ta = -30°C Ta = 60°C Ta = 90°C – 2.93 Ta = 0°C – 2.94 – 2.94 – 2.95 0 10 20 30 40 50 60 70 80 90 100 Load current, IOUT – mA – 2.95 4.5 5 5.5 6 Intput voltage, VDD – V Overcurrent protection function detection current value, Ilim – mA Overcurrent protection function detection current value Overcurrent protection - Ambient temperature dependence characteristics 180 170 VDD = 6V VDD = 5.5V 160 VDD = 5V VD D = 4.5V VD = D 4V 150 VDD = 3.5 V 140 130 120 110 100 – 40 – 20 0 20 40 60 80 100 Ambient temperature, Ta – °C No.A0584-13/14 LV5254LG SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2007. Specifications and information herein are subject to change without notice. PS No.A0584-14/14