ESMT M13S128168A-5T

ESMT
M13S128168A
Revision History
Revision 0.1 (15 Jan. 2002)
- Original
Revision 0.2 (19 Nov. 2002)
-changed ordering information & DC/AC characteristics
Revision 0.1
Revision 0.2
M13S128168A - 5T
M13S128168A - 6T
M13S128168A - 6T
M13S128168A - 7.5AB
Revision 0.3 (8 Aug. 2003)
-Change IDD6 from 3mA to 5mA.
Revision 0.4 (27 Aug. 2003)
-Change ordering information & DC / AC characteristics.
Revision 1.0 (21 Oct. 2003)
-Modify tWTR from 2tck to 1tck.
Revision 1.1 (10 Nov. 2003)
-Correct some refresh interval that is not revised.
-Correct some CAS Lantency that is not revised.
Revision 1.2 (12 Jan. 2004)
-Correct IDD1; IDD4R and IDD4W test condition.
-Correct tRCD; tRP unit
-Add tCCD spec.
-Add tDAL spec.
Revision 1.3 (12 Mar. 2004)
-Add Cas Latency=2; 2.5
Revision 1.4 (23 Jun. 2005)
-Add Pb-free to ordering information
-Modify IDD0 and IDD1 spec
-Modify some AC timing unit from tCK to ns.
Revision 1.5 (29 May. 2006)
-Delete CL2 ; CL2.5
-Modify tREFI
-Delete Non-pb-free form ordering information
Revision 1.6 (3 Jan. 2007)
-Add CL2.5
Revision 1.7 (12 Apr. 2007)
-Add BGA package
Revision 1.8 (01 Jun. 2007)
-Delete CL 2.5
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
1/49
ESMT
M13S128168A
DDR SDRAM
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Features
z
JEDEC Standard
z
Internal pipelined double-data-rate architecture, two data access per clock cycle
z
Bi-directional data strobe (DQS)
z
On-chip DLL
z
Differential clock inputs (CLK and CLK )
z
DLL aligns DQ and DQS transition with CLK transition
z
Quad bank operation
z
CAS Latency : 3
z
Burst Type : Sequential and Interleave
z
Burst Length : 2, 4, 8
z
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z
Data I/O transitions on both edges of data strobe (DQS)
z
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z
Data mask (DM) for write masking only
z
VDD = 2.375V ~ 2.75V, VDDQ = 2.375V ~ 2.75V
z
Auto & Self refresh
z
15.6us refresh interval (64ms refresh period, 4K cycle)
z
SSTL-2 I/O interface
z
66pin TSOPII package
Ordering information :
PRODUCT NO.
MAX FREQ
M13S128168A -5TG
200MHz
M13S128168A -6TG
166MHz
M13S128168A -5BG
200MHz
M13S128168A -6BG
166MHz
Elite Semiconductor Memory Technology Inc.
VDD
PACKAGE
2.5V
TSOPII
COMMENTS
Pb-free
Pb-free
2.5V
BGA
Pb-free
Pb-free
Publication Date : Jun. 2007
Revision : 1.8
2/49
ESMT
M13S128168A
Functional Block Diagram
Clock
Generator
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Mode Register &
Extended Mode
Register
Bank A
CAS
WE
DM
Column Decoder
Latch Circuit
RAS
Column
Address
Buffer
&
Refresh
Counter
Control Logic
CS
Command Decoder
Sense Amplifier
Data Control Circuit
CLK, CLK
DLL
Input & Output
Buffer
Address
Row Decoder
CLK
CLK
CKE
DQS
DQ
DQS
Pin Arrangement
x16
VDD
DQ 0
VDDQ
DQ 1
DQ 2
VSSQ
DQ 3
DQ 4
VDDQ
DQ 5
DQ 6
VSSQ
DQ 7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
Elite Semiconductor Memory Technology Inc.
x16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ 9
VDDQ
DQ 8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Publication Date : Jun. 2007
Revision : 1.8
3/49
ESMT
M13S128168A
60 Ball BGA
1
2
3
7
8
9
A
VSSQ
DQ15
VSS
VDD
DQ0
VDDQ
B
DQ14
VDDQ
DQ13
DQ2
VSSQ
DQ1
C
DQ12
VSSQ
DQ11
DQ4
VDDQ
DQ3
D
DQ10
VDDQ
DQ9
DQ6
VSSQ
DQ5
E
DQ8
VSSQ
UDQS
LDQS
VDDQ
DQ7
F
VREF
VSS
UDM
LDM
VDD
NC
G
CLK
CLK
WE
CAS
H
NC
CKE
RAS
CS
J
A11
A9
BA1
BA0
K
A8
A7
A0
A10/AP
L
A6
A5
A2
A1
M
A4
VSS
VDD
A3
Pin Description
(M13S128168A)
Pin Name
A0~A11,
BA0,BA1
DQ0~DQ15
Function
Pin Name
Function
Address inputs
- Row address A0~A11
- Column address A0~A8
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
LDM, UDM
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
Data-in/Data-out
CLK, CLK
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
VDDQ
Supply Voltage for GDQ
VSS
Ground
VSSQ
Ground for DQ
VDD
Power
VREF
Reference Voltage for SSTL-2
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
NC
No connection
LDQS, UDQS
Elite Semiconductor Memory Technology Inc.
CKE
Clock input
CS
Clock enable
Chip select
Publication Date : Jun. 2007
Revision : 1.8
4/49
ESMT
M13S128168A
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
Voltage on VDDQ supply relative to VSS
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
TBD
W
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 °C )
Parameter
Symbol
Min
Max
Unit
Supply voltage
VDD
2.375
2.75
V
I/O Supply voltage
VDDQ
2.375
2.75
V
I/O Reference voltage
VREF
0.49*VDDQ
0.51*VDDQ
V
1
I/O Termination voltage (system)
VTT
VREF - 0.04
VREF + 0.04
V
2
Input logic high voltage
VIH (DC)
VREF + 0.15
VDDQ + 0.3
V
Input logic low voltage
VIL (DC)
-0.3
VREF - 0.15
V
Input Voltage Level, CLK and CLK inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
Input Differential Voltage, CLK and CLK inputs
VID (DC)
0.36
VDDQ + 0.6
V
II
-5
5
μA
Output leakage current
IOZ
-5
5
μA
Output High Current (Normal strength driver)
(VOUT =VDDQ-0.373V, min VREF, min VTT)
IOH
-16.8
mA
Output Low Current (Normal strength driver)
(VOUT = 0.373V)
IOL
+16.8
mA
Output High Current (Weak strength driver)
(VOUT =VDDQ-0.763V, min VREF, min VTT)
IOH
-9
mA
Output Low Current (Weak strength driver)
(VOUT = 0.763V)
IOL
+9
mA
Input leakage current
Note
3
Notes 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF .
3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
5/49
ESMT
M13S128168A
DC Specifications
Parameter
Symbol
Version
Test Condition
-5
-6
Unit Note
Operation Current
(One Bank Active)
IDD0
tRC = tRC (min) tCK = tCK (min)
Active – Precharge
170
145
mA
Operation Current
(One Bank Active)
IDD1
Burst Length = 2 tRC = tRC (min), CL=
2.5 IOUT = 0mA, Active-ReadPrecharge
175
150
mA
Precharge Power-down Standby
Current
IDD2P
CKE ≤ VIL(max), tCK = tCK (min), All
banks idle
40
40
mA
Idle Standby Current
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK =
tCK (min)
115
95
mA
IDD3P
All banks ACT, CKE ≤ VIL(max), tCK =
tCK (min)
50
45
mA
Active Standby Current
IDD3N
One bank; Active-Precharge, tRC =
tRAS(max),
tCK = tCK (min)
120
110
mA
Operation Current (Read)
IDD4R
Burst Length = 2, CL= 2.5 , tCK = tCK
(min), IOUT = 0Ma
245
215
mA
Operation Current (Write)
IDD4W
Burst Length = 2, CL= 2.5 , tCK = tCK
(min)
240
200
mA
270
250
mA
5
5
mA
Active
Current
Power-down
Standby
Auto Refresh Current
IDD5
tRC ≥ tRFC(min)
Self Refresh Current
IDD6
CKE ≤ 0.2V
1
Note 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
Input Different Voltage, CLK and CLK inputs
VID(AC)
Input Crossing Point Voltage, CLK and CLK inputs
VIX(AC)
Max
Unit
Note
V
VREF - 0.31
V
0.7
VDDQ+0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(VDD = 2.375V~2.75V, VDDQ =2.375V~2.75V, TA = 25 °C , f = 1MHz)
Parameter
Symbol
Min
Max
Unit
CIN1
2.5
3.5
pF
Input capacitance (CLK, CLK )
CIN2
2.5
3.5
pF
Data & DQS input/output capacitance
COUT
4.0
5.5
pF
Input capacitance (DM)
CIN3
4.0
5.5
pF
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE )
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
6/49
ESMT
M13S128168A
AC Operating Test Conditions
Parameter
Value
Unit
0.5*VDDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
1.0
V/ns
VREF+0.31/VREF-0.31
V
Input timing measurement reference level
VREF
V
Output timing reference level
VTT
V
Input reference voltage for clock (VREF)
Input levels (VIH/VIL)
AC Timing Parameter & Specifications
(VDD = 2.375V~2.75V, VDDQ=2.375V~2.75V, TA =0 °C to 70 °C )(Note)
Parameter
Symbol
-5
-6
min
max
min
max
tCK
5.0
10
6.0
10
ns
Access time from CLK/ CLK
tAC
-0.7
+0.7
-0.7
+0.7
ns
CLK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CLK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
Data strobe edge to clock edge
tDQSCK
-0.6
+0.6
-0.6
+0.6
ns
Clock to first rising edge of DQS delay
tDQSS
0.75
1.25
0.75
1.25
tCK
Data-in and DM setup time (to DQS)
tDS
0.45
-
0.45
-
ns
Data-in and DM hold time (to DQS)
tDH
0.45
-
0.45
-
ns
DQ and DM input pulse width (for each input)
tDIPW
1.75
-
1.75
-
ns
Input setup time (fast slew rate)
tIS
0.75
-
0.75
-
ns
Input hold time (fast slew rate)
tIH
0.75
-
0.75
-
ns
Input setup time (slow slew rate)
tIS
0.8
-
0.8
-
ns
Input hold time (slow slew rate)
tIH
0.8
-
0.8
-
ns
tIPW
2.2
-
2.2
-
ns
DQS input high pulse width
tDQSH
0.4
0.6
0.4
0.6
tCK
DQS input low pulse width
tDQSL
0.4
0.6
0.4
0.6
tCK
DQS falling edge to CLK rising-setup time
tDSS
0.2
-
0.2
-
tCK
DQS falling edge from CLK rising-hold time
tDSH
0.2
-
0.2
-
tCK
Data strobe edge to output data edge
tDQSQ
-
0.45
-
0.45
ns
tHZ
-0.7
+0.7
-0.7
+0.7
ns
tLZ
-0.7
+0.7
-0.7
+0.7
ns
Clock Period
CL3
Control and Address input pulse width
Data-out high-impedance window from
CLK/ CLK
Data-out low-impedance window from
CLK/ CLK
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
7/49
ESMT
M13S128168A
AC Timing Parameter & Specifications-continued
Parameter
Symbol
Half Clock Period
DQ-DQS output hold
time
-5
-6
min
max
min
max
tHP
tCLmin or tCHmin
-
tCLmin or tCHmin
-
ns
tQH
tHP-0.45
-
tHP-0.5
-
ns
ACTIVE to PRECHARGE
command
tRAS
40
120Kns
42
120Kns
ns
Row Cycle Time
tRC
60
-
60
-
ns
AUTO REFRESH Row Cycle
Time
tRFC
70
-
72
-
ns
ACTIVE to READ,WRITE
delay
tRCD
18
-
18
-
ns
PRECHARGE command
period
tRP
18
-
18
-
ns
ACTIVE to READ with
AUTOPRECHARGE
command
tRAP
18
120K
18
120K
ns
ACTIVE bank A to ACTIVE
bank B command
tRRD
10
-
12
-
ns
Write recovery time
tWR
2
-
2
-
tCK
Write data in to READ
command delay
tWTR
1
-
1
-
tCK
Col. Address to Col. Address
delay
tCCD
1
-
1
-
tCK
Average periodic refresh
interval
tREFI
-
15.6
-
15.6
us
Write preamble
tWPRE
0.25
-
0.25
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
tWPRES
0
-
0
-
ns
Load Mode Register /
Extended Mode register
cycle time
tMRD
2
-
1
-
tCK
Exit self refresh to READ
command
tXSRD
200
-
200
-
tCK
Exit self refresh to
non-READ command
tXSNR
75
-
75
-
ns
Autoprecharge write
recovery+Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
Clock to DQS write preamble
setup time
Elite Semiconductor Memory Technology Inc.
(tWR/tCK)
+
(tRP/tCK)
tCK
Publication Date : Jun. 2007
Revision : 1.8
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ESMT
M13S128168A
Command Truth Table
COMMAND
CKEn-1 CKEn CS
RAS
CAS
WE
DM
BA0,1
A10/AP
A11,
A9~A0
Note
Register
Extended MRS
H
X
L
L
L
L
X
OP CODE
1,2
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1,2
L
L
L
H
X
X
L
H
H
H
H
X
X
X
X
X
Auto Refresh
Refresh
Entry
Self
Refresh
Read &
Column
Address
Auto Precharge Disable
Write &
Column
Address
Auto Precharge Disable
H
3
L
H
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
L
H
X
L
H
L
L
X
V
Auto Precharge Enable
Bank Selection
All Banks
Active Power Down
H
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
X
X
X
L
V
V
V
Entry
H
L
Exit
L
H
Entry
H
L
Precharge Power Down
Mode
Exit
L
DM
H
No Operation Command
H
H
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
H
X
X
X
L
H
H
H
X
3
3
Row Address
L
Auto Precharge Enable
Burst Stop
3
L
Exit
Bank Active & Row Addr.
Precharge
H
Column
Address
Column
Address
X
V
L
X
H
4
4
4
4,6
7
X
5
X
X
X
X
X
V
X
X
X
8
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 1 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”..
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1 : Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
9/49
ESMT
M13S128168A
Basic Functionality
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & VREF).
2. Start clock and maintain stable condition for a minimun of 200us.
3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
*1 5. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the
rest address pins, A1~A11 and BA1)
*1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.
(To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
*2 7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional
200 cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
P o we r u p & In i t i a l i z a t i o n S e q u e n c e
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CLK
tRP
Command
p re c ha rg e
A ll B a nk s
tRFC
tRP
E MRS
MRS
Dll Reset
p re c ha rg e
A ll B a nks
1s t A uto
Re f re s h
tRFC
2nd A uto
Re f re s h
Mode
Register Set
Any
Command
min . 200 Cycl e
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
10/49
ESMT
M13S128168A
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety
of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS
setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0
(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of
address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock
cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is
divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read
latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal
MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
BA1
BA0
0
0
A11
A10
A9
RFU
A8
A7
DLL
TM
A6
A5
A4
CAS Latency
A3
A2
BT
A1
A0
Burst Length
A8
DLL Reset
A7
Mode
A3
Burst Type
0
No
0
Normal
0
Sequential
1
Yes
1
Test
1
Interleave
Address Bus
Mode Register
Burst Length
CAS Latency
BA1 BA0
0
0
0
1
Operating Mode
MRS Cycle
EMRS Cycle
A6
0
0
0
1
1
1
Elite Semiconductor Memory Technology Inc.
A5
0
0
1
0
1
1
A4
0
1
1
1
0
1
Latency
Reserve
Reserve
3
Reserve
Reserve
Reserve
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Latency
Sequential Interleave
Reserve
Reserve
2
2
4
4
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Publication Date : Jun. 2007
Revision : 1.8
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ESMT
M13S128168A
Burst Address Ordering for Burst Length
Burst
Length
Starting
Address (A2, A1,A0)
xx0
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
2
4
8
Sequential Mode
Interleave Mode
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is
enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S128168A also support a weak drive strength
option, intended for lighter load and/or point-to-point environments.
Mode Register Set
0
1
2
3
4
5
6
7
8
CLK
CLK
*1
Mod e
Register Set
Precharg e
Al l Ba n k s
COMMAND
tCK
An y
Com m an d
t R P* 2
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
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ESMT
M13S128168A
Extended Mode Register Set (EMRS)
The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not
defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode
register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR SDRAM should be in all bank
precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0~A11 and BA1 in
the same cycle as CS , RAS , CAS and WE going low is written in the extended mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state.
A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set
to low for proper EMRS operation. Refer to the table for specific codes.
BA1 BA0
0
A11
A10
1
A9
A8
A7
A6
A5
A4
A3
A2
RFU : Must be set “0”
A1
A0
D.I.C
DLL
Output Driver Strength Control
BA1
BA0
Operaing Mode
0
0
MRS Cycle
0
1
EMRS Cycle
A0
DLL Enable
0
Normal
0
Enable
1
Weak
1
Disable
*QFC is not used; don’t care.
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ESMT
M13S128168A
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge
each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is
precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued.
After tRP from the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by Bank address bits
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A Only
0
0
1
Bank B Only
0
1
0
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs.
The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and
NOP the device should finish the current operation when this command is issued.
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M13S128168A
Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the
clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank
Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min).
Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank.
The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank
delay time (tRRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
0
1
2
CLK
CLK
Addr ess
Ban k A
Ro w Ad d r .
Ban k A
Col. Add r .
RAS-CAS d el ay (tRCD)
Command
Ban k A
Activate
NOP
Write A
wi th Au t o
Precharg e
Ban k A
Ro w . Ad d r .
Bank B
Ro w Ad d r .
RAS-RAS d el ay (tRRD)
Bank B
Activate
NOP
Bank A
Activate
ROW Cycle Time (tRC)
: Don't Care
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table.
The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of
the burst will be determined by the values programmed during the MRS command.
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ESMT
M13S128168A
Essential Functionality for DDR SDRAM
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is
issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from
the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM
until the burst length is completed.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
CL K
CL K
CO M M A N D
READ A
N OP
NO P
NOP
NO P
N OP
N OP
N OP
NO P
D QS
C AS L at enc y =3
DQ ' s
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ESMT
M13S128168A
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst
write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge
enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be
supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
CLK
CLK
CO MM AND
NOP
W RITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDSH
tDSS
tDQSS
DQS
tWPST
tWPRES
DQ's
Din0
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Din1
Din2
Din3
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ESMT
M13S128168A
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
CLK
CLK
COMMAND
READ A
READ B
NO P
NOP
NO P
NO P
NOP
NOP
NO P
DQS
CAS Latency= 3
Dou t A 0 Dou t A 1 Dou t B 0 Dou t B 1 Dout B 2 Dou t B 3
DQ's
tCCD
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) clocks ［RU means round up to the nearest integer］ before
the Write command.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
CLK
CLK
COMMAND
READ
Bu r st S t op
NOP
NO P
W RITE
NO P
NOP
NOP
NOP
DQS
CAS Latency= 3
DQ's
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Din 0
Din 1 Din 2
Din 3
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ESMT
M13S128168A
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
CLK
CLK
1tCK
COMMAND
READ
Prech arg e
NO P
NOP
NOP
NOP
NOP
NOP
NOP
DQS
CAS Latency= 3
DQ's
Dou t 0 Dou t 1 Dou t 2 Dou t 3 Dou t 4 Dou t 5 Dou t 6 Dou t 7
Int erru pt ed by precharg e
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the
Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and
when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last
data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank
after tRP.
3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.
During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a
Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with
autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which
does not interrupt the burst.
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ESMT
M13S128168A
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
CLK
CL K
1tCK
C OMM AN D
N OP
WR IT E A
WR IT E B
NO P
N OP
N OP
NO P
N OP
N OP
D QS
D Q's
D in A 0
D in A 1
Di n B 0
D in B 1
Di n B 2
D in B 3
tCCD
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst
and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum
delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
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M13S128168A
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one
clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered,
any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is
required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated
will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write
command.
<Burst Length = 8, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
CLK
CLK
COMM AND
NO P
W RITE
NO P
NOP
Rea d
NOP
NOP
NO P
NOP
tWTR
tDQSSmax
DQ S
tWPRES
CAS Latency= 3
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
DQ's
tDQSSmin
Dou t 0 Dou t 1
tWTR
DQ S
tWPRES
CAS Latency= 3
DQ's
Din 0 Din 1 Din 2
Din 3 Din 4 Din 5 Din 6 Din 7
Dou t 0 Dou t 1
DM
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into
the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where
the Write to Read delay is 1 clock cycle is disallowed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
controller) in time to allow the buses to turn around before the SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs is ignored by the SDRAM.
5. It is illegal for a Read command interrupt a Write with autoprecharge command.
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M13S128168A
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column
access is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is
asserted, any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
0
1
2
3
4
5
6
7
8
CLK
CLK
COMM AND
NOP
WRITE A
NOP
NOP
NOP
NOP
Precharge
WRITE B
NO P
tDQSSmax
DQS
tWR
Din a0 Din a1 Dina2 Dina3 Din a4 Din a5 Din a6 Din a7
DQ's
Dinb0
tWR
tDQSSmin
DQS
DQ's
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
Dinb0 Dinb1
DM
Precharge timing for Write operations in DRAMs requires enough time to allow “Write recovery” which is the time required by a
DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used
to indicate the required of time between the last valid write operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is
sampled by the input clock. Inside the SDRAM, the data path is eventually synchronizes with the address path by switching clock
domains from the data strobe clock domain to the input clock domain.
This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery
parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock
edge that strobes in the precharge command.
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ESMT
M13S128168A
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DQ, is used to mask input data during the
time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the
DQS input is still required to strobe in the state of DM.
The minimum time for write recovery is defined by tWR.
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where
tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the
Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as
the earliest possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with
autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command
which does not interrupt the burst.
Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
(CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read
operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and
DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The
burst stop command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
0
1
2
3
4
5
6
7
8
CL K
CL K
C OMMAN D
READ A
B u rs t S t op
N OP
N OP
N OP
N OP
N OP
N OP
N OP
D QS
C A S Lat e n cy = 3
D Q' s
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ESMT
M13S128168A
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1.
2.
3.
4.
5.
6.
The BST command may only be issued on the rising edge of the input clock, CLK.
BST is only a valid command during Read burst.
BST during a Write burst is undefined and shall not be used.
BST applies to all burst lengths.
BST is an undefined command during Read with autoprecharge and shall not be used.
When terminating a burst Read command, the BST command must be issued LBST ( “BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask
latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
0
1
2
3
4
5
6
7
8
CLK
CLK
CO MM AND
DQS
DQ's
W RITE
NOP
NOP
NOP
NOP
Din 4 Din 5
Din 6
NOP
NOP
NOP
NOP
tDQSS
Din 0
Din 1
Din 2
Din 3
Din 7
DM
masked by DM = H
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ESMT
M13S128168A
Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock
later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be
delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (tRP) has been satisfied
<Burst Length = 4, CAS Latency = 3>
CL K
0
1
2
3
4
5
6
7
8
C LK
C O M M A ND
Ba nk A
A CT I VE
N OP
R ea d A
A ut o P re cha rg e
N OP
N OP
N OP
N OP
N OP
N OP
t R AP
D QS
C A S Lat en cy = 3
D Q' s
D o ut 0 Do u t 1 Do u t 2 Do u t 3
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
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ESMT
M13S128168A
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
CLK
CLK
COMM AND
Ban k A
ACTIVE
NOP
W r i te A
Auto Pr ec har g e
NOP
NOP
NOP
NOP
NOP
NOP
DQS
*B an k c an be reac t ivat ed at
com p let ion of t RP
Dout 0 Dout 1 Dout 2 Dout 3
DQ's
tWR
tRP
In te rn al p re ch ar g e s ta r t
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of
the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the tRFC(min).
A maximum of eight consecutive AUTO REFRSH commands (with tRFCmin) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6μm.
CLK
CLK
COMMAND
Au t o
Refresh
PRE
CMD
CKE = High
tRP
Elite Semiconductor Memory Technology Inc.
tRFC
Publication Date : Jun. 2007
Revision : 1.8
26/49
ESMT
M13S128168A
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the
clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the
self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce
power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP
command and then asserting CKE high for longer than tXSRD for locking of DLL.
CLK
CLK
Sel f
Ref resh
COMM AND
Au to
Refresh
Rea d
CKE
tXSNR
tXSRD
Power down
Power down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is
referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE.
For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that case, the DLL must
be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However,
power-down duration is limited by the refresh requirements of the device, so in most applications, the self-refresh mode is preferred
over the DLL disable power-down mode. In the power-down, CKE LOW and a stable clock signal must be maintained at the inputs
of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is
registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.
CLK
CLK
tIS
tIS
CKE
COMM AND
VALID
NOP
No c ol um n
ac es s
Ent er p ow er - dow n
in pr ogr am
m ode
Elite Semiconductor Memory Technology Inc.
NOP
VALID
Exi t po w e r - do w n
m ode
Publication Date : Jun. 2007
Revision : 1.8
27/49
ESMT
M13S128168A
Functional Truth Table.
Current
IDLE
ROW ACTIVE
Address
Command
Action
CS
RAS
CAS
WE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
Burst Stop
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL*2
L
L
H
H
BA, RA
Active
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE / PREA
NOP*4
L
L
L
H
X
Refresh
AUTO-Refresh*5
L
L
L
L
Op-Code Mode-Add
MRS
Mode Register Set*5
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
Burst Stop
NOP
L
H
L
H
BA, CA, A10
READ / READA
Begin Read, Latch CA,
Determine Auto -precharge
L
H
L
L
BA, CA, A10
WRITE / WRITEA
Begin Write, Latch CA,
Determine Auto -precharge
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Precharge/Precharge All
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
Burst Stop
Terminate Burst
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L
H
L
L
BA, CA, A10
WRITE / WRITEA
ILLEGAL
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
READ
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
28/49
ESMT
Current State
WRITE
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
M13S128168A
Address
Command
Action
CS
RAS
CAS
WE
H
X
X
X
X
DESEL
NOP (Continue Burst to end)
L
H
H
H
X
NOP
NOP (Continue Burst to end)
L
H
H
L
BA
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
Terminate Burst With DM=High,
Latch CA, Begin Read, Determine
Auto-Precharge*3
L
H
L
L
BA, CA, A10
WRITE/WRITEA
Terminate Burst, Latch CA,
Begin new Write, Determine
Auto-Precharge*3
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Terminal Burst
Precharge
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to end)
L
H
H
H
X
NOP
NOP (Continue Burst to end)
L
H
H
L
BA
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ
READ*7
L
H
L
L
BA, CA, A10
WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ
ILLEGAL
L
H
L
L
BA, CA, A10
WRITE
Write
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
Elite Semiconductor Memory Technology Inc.
With
DM=High,
Publication Date : Jun. 2007
Revision : 1.8
29/49
ESMT
Current State
PRE-CHARGIN
G
ROW
ACTIVATING
WRITE
RECOVERING
M13S128168A
Address
Command
Action
CS
RAS
CAS
WE
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
BA
Burst Stop
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL*2
L
L
H
H
BA, RA
Active
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
NOP*4 (Idle after tRP)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (ROW Active after tRCD)
L
H
H
H
X
NOP
NOP (ROW Active after tRCD)
L
H
H
L
BA
Burst Stop
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL*2
L
L
H
H
BA, RA
Active
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
Burst Stop
ILLEGAL*2
L
H
L
H
BA, CA, A10
READ
ILLEGAL*2
L
H
L
L
BA, CA, A10
WRITE
WRITE
L
L
H
H
BA, RA
Active
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
30/49
ESMT
Current State
RE-FRESHING
MODE
REGISTER
SETTING
M13S128168A
Address
Command
Action
CS
RAS
CAS
WE
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
BA
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
BA
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS
ILLEGAL
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Don’t Care
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL of any bank is not idle.
6. Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be
performed.
7. Refer to “Read with Auto Precharge: for more detailed information.
ILLEGAL = Device operation and / or data integrity are not guaranteed.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
31/49
ESMT
Current State
SELF-REFRESHING*
1
POWER DOWN
ALL BANKS IDLE*2
M13S128168A
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Add
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self-Refresh
L
H
L
H
H
H
X
Exit Self-Refresh
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down (Idle after tPDEX)
L
L
X
X
X
X
X
NOP (Maintain Power Down)
H
H
X
X
X
X
X
Refer to Function True Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Exit Power Down
H
L
L
H
H
H
X
Exit Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
L
L
X
X
X
X
Refer to Current State = Power Down
H
H
X
X
X
X
X
Refer to Function True Table
X
Action
NOP (Maintain Self-Refresh)
ANY STATE other
than listed above
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Don’t Care
Note :
1. CKE Low to High transition will re-enable CLK, CLK and other inputs asynchronously. A minimum setup time must be
satisfied before issuing any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from All Bank Idle state.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
32/49
ESMT
M13S128168A
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
tCL
tCK
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
tHP
Note1
HIGH
CKE
tIS
CS
tIH
RAS
CAS
BA0,BA1
BAa
BAb
BAa
Cb
A10/ AP
ADDR
(A0~ An )
WE
tDQSCK
tRPRE
DQS
tDQSCK
tRPST
tDQSS
tWPRE
Hi-Z
tDQSL
tWPST
Hi-Z
tDQSH
tDQSQ
tAC
tLZ
Da0
DQ
Da1
Da2
Da3
tWPRES
tDS tDH tDS tDH
tHZ
Hi-Z
Db0
Db1 Db2
Db3
Hi-Z
tQH
DM
COMMAND
READ
WRITE
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
33/49
ESMT
M13S128168A
Multi Bank Interleaving READ (@BL=4, CL=3)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
34/49
ESMT
M13S128168A
Multi Bank Interleaving WRITE (@BL=4)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
35/49
ESMT
M13S128168A
Read with Auto Precharge (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAa
A10/AP
ADDR
(A0~ An )
Ra
Ra
Ca
WE
Au t o p r e ch ar g e s t a r t
tRP
Note1
DQS(CL=3)
DQ(CL=3)
Q a0
Q a1
Qa2
Q a3
Q a4
Q a5
Q a6
Q a7
DM
CO MM AND
Note 1.
READ
ACTIVE
The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
36/49
ESMT
M13S128168A
Write with Auto Precharge (@BL=8)
Note 1.
The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
37/49
ESMT
M13S128168A
Read Interrupted by Precharge (@BL=8)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
38/49
ESMT
M13S128168A
Read Interrupted by a Read (@BL=8, CL=3)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
39/49
ESMT
M13S128168A
Read Interrupted by a Write & Burst stop (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAb
Ca
Cb
A10/ AP
ADDR
(A0~ An )
WE
DQS
DQ
Qa0
Q b0
Q a1
Qb1
Q b2
Q b3
Q b4
Qb5
Q b6
Q b7
DM
COMMAND
READ
Burst
Stop
Elite Semiconductor Memory Technology Inc.
WRITE
Publication Date : Jun. 2007
Revision : 1.8
40/49
ESMT
M13S128168A
Write followed by Precharge (@BL=4)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAa
A1 0 / A P
ADDR
(A0~ An)
Ca
WE
tWR
DQS
Da0
DQ
Da1
Da2
Da3
DM
COMMAND
WRITE
Elite Semiconductor Memory Technology Inc.
PRE
CHARGE
Publication Date : Jun. 2007
Revision : 1.8
41/49
ESMT
M13S128168A
Write Interrupted by Precharge & DM (@BL=8)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
42/49
ESMT
M13S128168A
Write Interrupted by a Read (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAb
Ca
Cb
A1 0/ AP
ADDR
(A0~ An )
WE
DQ S
Da0
DQ
Da1
Da2
Da3
Da4
Da5
Q b0
Q b1
Q b2
Qb3
Q b4
Q b5
Ma s k ec d b y D M
DM
tWTR
COMMAND
WRITE
Elite Semiconductor Memory Technology Inc.
READ
Publication Date : Jun. 2007
Revision : 1.8
43/49
ESMT
M13S128168A
DM Function (@BL=8) only for write
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
A10/ AP
ADDR
(A0~ An)
Ca
WE
DQS( CL= 3 )
DQ(CL=3)
Q a0
Q a1
Q a2
Q a3
Q a4
Q a5
Q a6
Q a7
DM
COMMAND
WRITE
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Publication Date : Jun. 2007
Revision : 1.8
44/49
ESMT
M13S128168A
Power up & Initialization Sequence
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CLK
Hi gh l ev el i s r equ i r ed
CKE
CS
RAS
CAS
WE
BA0
BA1 ,A 9, A1 1
A10 /AP
A8
A7
AD DR ES S KEY
A1 ~ A 6
A0
Min im um 200 Cycle
High-Z
DQ
tRP
tRP
tRFC
tRFC
M i n i m u m o f 2 R ef r es h Cyc le s a r e r e qu ir ed
High-Z
DQS
Precharge
All B an k
EMRS
DLL Enable
Any
Com man d
Precharge
All Ban k
Power & Cl ock m us t be
stable f or 200us
MRS
DLL Reset
Elite Semiconductor Memory Technology Inc.
1st Auto Ref r es h
2nd Auto Ref r esh
Mode R es i st er Set
: Don 't Car e
Publication Date : Jun. 2007
Revision : 1.8
45/49
ESMT
M13S128168A
Mode Register Set
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CLK
tCK
CKE
CS
RAS
CAS
WE
BA0, BA1
A10 /AP
ADDR ESS KEY
ADDR
(A0~An)
DM
tRP
tMRD
High-Z
DQ
High-Z
DQS
Precharge
Command
All Ban k
Any
Com man d
M ode R egis ter Set
Command
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Publication Date : Jun. 2007
Revision : 1.8
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ESMT
PACKING
66-LEAD
Symbol
A
A1
A2
b
b1
c
c1
D
ZD
E
E1
e
L
L1
θ°
θ1°
M13S128168A
DIMENSIONS
TSOP(II)
Dimension in inch
Min
Norm
Max
0.047
0.002
0.004
0.006
0.037
0.039
0.041
0.009
0.015
0.009
0.012
0.013
0.005
0.008
0.0047
0.005
0.006
0.875 BSC
0.028 REF
0.455
0.463
0.471
0.400 BSC
0.026 BSC
0.016
0.02
0.024
0.031 REF
10°
10°
15°
15°
20°
20°
Elite Semiconductor Memory Technology Inc.
DRAM(400mil)
Dimension in mm
Min
Norm
Max
1.2
0.05
0.1
0.15
0.95
1
1.05
0.22
0.38
0.22
0.3
0.33
0.12
0.21
0.12
0.127
0.16
22.22 BSC
0.71 REF
11.56
11.76
11.96
10.16 BSC
0.65 BSC
0.4
0.5
0.6
0.80 REF
10°
10°
15°
15°
20°
20°
Publication Date : Jun. 2007
Revision : 1.8
47/49
ESMT
M13S128168A
PACKING
DIMENSIONS
60-BALL
DDR SDRAM
Symbol
A
A1
A2
Φb
D
E
D1
E1
e
e1
( 8x13 mm )
Dimension in mm
Min
Norm
Max
1.20
0.30
0.35
0.40
0.80
0.40
0.45
0.50
7.90
8.00
8.10
12.90
13.00
13.10
6.40
11.0
0.80
1.00
Dimension in inch
Min
Norm
Max
0.047
0.012
0.014
0.016
0.031
0.016
0.018
0.020
0.311
0.315
0.319
0.508
0.512
0.516
0.252
0.433
0.031
0.039
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
48/49
ESMT
M13S128168A
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without notice.
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may directly affect human lives or cause physical injury or property damage. If
products described here are to be used for such kinds of application, purchaser
must do its own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
49/49