Micro Networks M2004-01 An Integrated Circuit Systems Company Preliminary Specifications M2004-01 Frequency Synthesizer DESCRIPTION The M2004-01 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Translator in a 9mm x 9mm surface mount package. The internal high “Q” SAW filter provides low jitter signal performance and determines the maximum output frequency of the VCSO. A programmable output divider can divide the VCSO frequency to achieve an output as low as 38.88MHz. The input to the Frequency Translator is provided by selecting between one of two output reference clocks. The output frequency is an integer multiple of the input reference frequency. FEATURES Output Clock Frequency up to 700MHz Differential LVPECL Outputs Internal Low-jitter SAW-based Oscillator Parallel and serial control of the output and feedback dividers is provided via the configuration logic. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock. Intrinsic Jitter <1ps rms (12kHz - 20MHz) Jitter Attenuation of Input Reference Clock Dual Input MUX Parallel Programming Tunable Loop Filter Response The M2004-01 is available at SONET/SDH and 10GbE frequencies up to 700MHz. Differential LVPECL Outputs 3.3V Operation Small 9mm x 9mm SMT Package APPLICATIONS ABSOLUTE MAX RATINGS SONET / SDH / 10GbE System Synchronization Inputs, VI : ................................................. -0.5 to VCC+0.5V Output, VO : ................................................. -0.5 to VCC+0.5V Supply Voltage, VDD : ......................................................... 4.6 V Storage Temperature, TSTO : ............................ -45°C to +100°C Add / Drop Muxes, Access and Edge Switches Line Card System Clock Cleaner / Translator Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Optical Module Clock Cleaner / Translator ISO 9001 Registered Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 1 fax: 508-852-8456 www.micronetworks.com Micro Networks M2004-01 Preliminary Specifications An Integrated Circuit Systems Company FUNCTIONAL BLOCK DIAGRAM The internal PLL will adjust the VCSO output frequency to be M times the selected input reference clock frequency. Note that the product of M x input frequency must be such that it falls within the “lock” range of the VCSO. The N output divider can be programmed to divide the VCSO output frequency by 1, 2, 4, or 8 and provide a 50% output duty cycle. RLOOP CLOOP REF_CLK1 REF_CLK0 RLOOP CLOOP RPOST nOP_IN OP_OUT nOP_OUT nVC Phase Detector RIN MUX When the N output divider is included, the complete relationship for the output frequency is defined as: FOUT= F VCSO = F REF_CLK x M N N External Loop Filter Components CPOST OP_IN F VCSO = F REF_CLK x M RPOST CPOST M2004-01 The relationship between the VCSO frequency, the input REF_CLK , and the M divider is defined as follows: VC The M value and the required logic states of M0 through M5 are shown in Table 5B, Programmable VCSO Frequency Function Table. (i.e. For an output frequency of 622.0800MHz and an input frequency of 19.44MHz the M value would be 32 and the N value would be 1. SAW Delay Line 1 0 RIN Loop Filter Amplifier REF_SEL Phase Shifter VCSO M Divider M = 3-1023 FOUT nFOUT N Divider N = 1,2,4,8 S_DATA S_CLK S_LOAD nP_LOAD Serial / Parallel Configuration Register 6 M5:0 2 N1:0 MR Similarly, for an output frequency of 311.04MHz and an input frequency of 19.44 MHz the M value would be 32 and the N value would be 2.) Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divider and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The M2004-01 supports both parallel and serial operating modes for programming the M divider and N output divider. Figure 1 shows the timing diagram for each mode. In the parallel mode the nP_LOAD input is initially LOW. The data on inputs M0 through M5 and N0 and N1 is passed directly to the M divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. FIGURE 1 S_DATA Low Low Null N1 N0 Null Null Null M5 M4 M3 M2 M1 M0 S_CLK S_LOAD Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 2 fax: 508-852-8456 www.micronetworks.com Micro Networks M2004-01 An Integrated Circuit Systems Company Preliminary Specifications FUNCTIONAL DESCRIPTION LOOP FILTER FIGURE 2 The M2004-01 requires the use of an external loop filter via the provided filter pins. Due to the differential design, the implementation requires two identical RC filters as shown in Figure 2. Rloop Cloop Rpost nVc OP_IN Cpost nOP_OUT OP_OUT Cpost Vc nOP_IN Rloop Cloop Rpost TABLE 1. RECOMMENDED LOOP FILTER VALUES REF_CLK Frequency VCSO Frequency M N FOUT Rloop Cloop Rpost Cpost 19.44MHz 622.0800MHz 32 1 622.0800MHz 5kΩ 1MF 50kΩ 100pf Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 3 fax: 508-852-8456 www.micronetworks.com Micro Networks M2004-01 Preliminary Specifications An Integrated Circuit Systems Company PIN DESCRIPTIONS TABLE 2 Pin Number 1, 2, 3 GND Name I/O GND Configuration 4, 9 OP_IN, nOP_IN Analog I/O Used for external loop filter. See Figure 2. 5, 8 nOP_OUT, OP_OUT Analog I/O Used for external loop filter. See Figure 2 6, 7 nVC, VC Input 10, 14, 26 GND GND Power Supply Ground 11, 19, 33 VDD Power Positive Supply Pins 12, 13 N0, N1 Input VCSO Pull - down Description Power Supply Ground Differential Control Voltage Input Pair Determines the output divider value as defined in table 3C. LVCMOS / LVTTL interface levels. 15, 16 FOUT, nFOUT Output Unterminated Differential output, 3.3V LVPECL levels. 17 MR Input Pull - down Logic HIGH resets the reference frequency and N output dividers. Logic LOW enables the outputs. LVCMOS / LVTTL interface levels. 18 S_CLOCK Input Pull - down Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. 20 S_DATA Input Pull - down Shift register serial input. Data is sampled on the rising edge of S_CLOCK. 21 S_LOAD Input Pull - down Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels 22 nP_LOAD Input Pull - down Parallel load input. Determines when data present at M5:M0 is loaded into Mdivider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. 23 REF_ CLK 1 Input Pull - down Input reference clock. LVCMOS / LVTTL interface levels. 24 REF_ CLK 0 Input Pull - down Input reference clock. LVCMOS / LVTTL interface levels. 25 REF_SEL Input Pull - down Selects between the different reference clock inputs as the PLL reference source. See table 3D. LVCMOS / LVTTL interface levels. 27, 28, 29, 30, 31 M0, M1, M2, M3, M4 Input Pull - down M divider inputs. Data is latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/ LVTTL interface levels. 32 M5 34, 35, 36 DNC Input Pull - down Do not connect. Internal test pins must be left floating. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 4 fax: 508-852-8456 www.micronetworks.com Micro Networks M2004-01 An Integrated Circuit Systems Company Preliminary Specifications PIN CHARACTERISTICS TABLE 4 Symbol Parameter Test Conditions Min Typical Max Units 4 pF CIN Input Capacitance RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ PARALLEL & SERIAL MODES FUNCTION TABLE 5A MR nP Load M Inputs N H X X X X X X Conditions Reset, Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M S Load S Clock S Data divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. L H X X L Data ↑ Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK L H X X L ↑ Data Contents of the shift register are passed to the M divider and N output divider. L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H ↑ Data S_DATA passed directly to M divider as it is clocked. Note: L = Low; H = High; X = Don’t care; ↑ = Rising Edge Transition; ↓ = Falling Edge Transition PROGRAMMABLE VCSO FREQUENCY FUNCTION TABLE 5B VCSO Frequency (MHz) 32 16 8 4 2 1 M Divide M5 M4 M3 M2 M1 M0 325 13 0 0 1 1 0 1 350 14 0 0 1 1 1 0 375 15 0 0 1 1 1 1 400 16 0 1 0 0 0 0 • • • • • • • • • • • • • • • • 600 24 0 1 1 0 0 0 625 25 0 1 1 0 0 1 650 26 0 1 1 0 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to a reference frequency of 25MHz. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 5 fax: 508-852-8456 www.micronetworks.com Micro Networks M2004-01 Preliminary Specifications An Integrated Circuit Systems Company PARALLEL MODE FUNCTION SERIAL MODE FUNCTION TABLE 5D TABLE 5C Inputs N Divider Output Frequency (MHz) N1 N0 Value Min Max Inputs REF SEL Reference 0 0 1 311 700 0 DIFF_REF 0 1 2 155.5 350 1 REF_CLK 1 0 4 77.75 175 1 1 8 38.875 87.5 POWER SUPPLY DC CHARACTERISTICS Symbol Parameter Test Conditions VDD Power Supply Voltage IDD Power Supply Current Min Typ Max Units 3.135 3.3 3.465 V 162 mA VCC= 3.3V ± 5%, TA= 0°C to 70°C LVCMOS/LVTTL DC CHARACTERISTICS Symbol VIH Input High Parameter REF_SEL, S_LOAD, S_ DATA, S_CLOCK Voltage nP_LOAD, N0:N1, M0:M5, MR Test Conditions REF_CLK0, REF_CLK1 VIL Input Low REF_SEL, S_LOAD, S_DATA, S_CLOCK Voltage nP_LOAD, N0:N1, M0:M5, MR REF_CLK0, REF_CLK1 IIH Min 2 Max Units VCC + 0.3 V 2 VCC + 0.3 V -0.3 0.8 V -0.3 1.3 V Input High M5 VDD = VIN = 3.465V 5 µA Current N0, N1, MR, M0:M4, S_CLOCK, VDD = VIN = 3.465V 150 µA S_DATA, S_LOAD, nP_LOAD, REF_SEL, REF_CLK0, REF_CLK1 IIL Input Low M5 VDD = 3.465, VIN = 0V -150 µA Current N0, N1, MR, M0:M4, S_CLOCK, VDD = 3.465, VIN = 0V -5 µA 2.6 V S_DATA, S_LOAD, nP_LOAD, REF_SEL, REF_CLK0, REF_CLK1 VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 0.5 V Note 1: Outputs terminated with 50Ω to VCC/2. See parameter Measurement section, 3.3V Output Load Test Circuit. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 6 fax: 508-852-8456 www.micronetworks.com Micro Networks M2004-01 An Integrated Circuit Systems Company Preliminary Specifications LVPECL DC CHARACTERISTICS Symbol Parameter Signal Min Max Units VOH Output High Voltage: Note 1 FOUT, nFOUT VDD – 1.4 Vcc – 1.0 V VOL Output Low Voltage: Note 1 FOUT, nFOUT VDD – 2.0 Vcc – 1.7 V Peak-to-Peak Output Voltage Swing FOUT, nFOUT 0.6 0.85 V VSWING Note 1: Output terminated with 50Ω to VDD–2.V INPUT FREQUENCY CHARACTERISTICS Symbol Parameter FIN Input Frequency Test Conditions Min Max 10 166 MHz 50 MHz REF_CLK0, REF_CLK1 S_CLOCK Units VCC = 3.3V± 5%, TA = 0°C to 70°C AC CHARACTERISTICS Symbol FOUT ØNOISE Parameter Typ 38.88 Max 700 Units MHz Single Side Band 1kHz offset -72 dBc/Hz Phase Noise 10kHz offset -94 dBc/Hz 100kHz offset -123 dBc/Hz 12kHz to 20 MHz 0.69 ps 50 % Jitter (RMS) odc Output Duty Cycle (Note 1) Min Output Frequency J (t) tR Test Conditions Output Rise Time FOUT = 155MHz 20% to 80%, each 350 450 550 ps for output pairs FOUT = 311MHz output of pair measured 325 425 500 ps FOUT0, nFOUT0 & FOUT = 622MHz is terminated into 50Ω 200 275 350 ps FOUT1, nFOUT1 load biased at Vcc-2V tF Output Fall Time FOUT = 155MHz 20% to 80%, each 350 450 550 ps (Note 1) for output pairs FOUT = 311MHz output of pair measured 325 425 500 ps FOUT0, nFOUT0 & FOUT = 622MHz is terminated into 50Ω 200 275 350 ps FOUT1, nFOUT1 tS tH Setup Time Hold Time tLOCK PLL Lock Time tPW load biased at Vcc-2V M, N, to nP_LOAD 5 ns S_DATA to S_CLK 5 ns S_CLK to S_LOAD 5 ns M,N, to nP_LOAD 5 ns S_DATA to S_CLK 5 ns S_CLK to S_LOAD 5 ns 1 ms Output Pulse TBD ns Width TBD ns Note: The output frequencies of 155MHz, 311MHz and 622MHz were chosen for device characterization as these are common optical network clock frequencies. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 7 fax: 508-852-8456 www.micronetworks.com Micro Networks M2004-01 Preliminary Specifications An Integrated Circuit Systems Company PARAMETER MEASUREMENT INFORMATION INPUT AND OUTPUT RISE AND FALL TIME 80% 80% V 20% 20% Clock Inputs and Outputs SWING t t R F ODC & tPERIOD Pulse Width t t odc = t PERIOD PW PERIOD SETUP AND HOLD TIME S_DATA tHOLD S_CLOCK tSET-UP S_LOAD tSET-UP M[5:0] N[1:0] tHOLD nP_LOAD tSET-UP Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 8 fax: 508-852-8456 www.micronetworks.com Micro Networks M2004-01 An Integrated Circuit Systems Company Preliminary Specifications TEST EVALUATION BOARD J3 9-PIN D CONNECTOR Pin Signal 1 MR 3 SW1 Position 1 REF Select 2 M5 3 M4 4 M3 5 M2 6 M1 7 M0 8 N/C S_CLOCK Off REF_CLK0 “1” “0” “0” “0” “0” “0” N/C 5 S_DATA On REF_CLK1 “0” “1” “1” “1” “1” “1” N/C 7 S_LOAD 9 nP_LOAD Micro Networks 324 Clark Street JP1: N0 JP2: N1 Logic “1” when installed Logic “0” when installed Worcester, MA 01606 tel: 508-852-5400 9 fax: 508-852-8456 www.micronetworks.com Micro Networks M2004-01 Preliminary Specifications An Integrated Circuit Systems Company MECHANICAL DIMENSIONS & PIN CONFIGURATION .354 [9.0] .110 [2.8] #19 #27 #28 #18 .354 [9.0] [ ] #10 #36 ORIENTATION TAB Pin #1 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 .200 [5.1] .025 [0.6] C CL .041 [1.0] R.006 [R0.2] .007 [0.2] Designation GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN GND VDD NO N1 GND FOUT nFOUT MR Pin# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34, 35, 36 Designation S_CLOCK VDD S_DATA S_LOAD nP_LOAD REF_CLK1 REF_CLK0 REF_SEL GND M0 M1 M2 M3 M4 M5 VDD N/C Dimensions are in inches, (dimensions) are in mm. ORDERING INFORMATION PART NUMBER Available VCSO Frequencies 622.0800 669.1281 625.0000 669.3266 627.3296 672.1600 644.5313 690.5692 666.5143 693.4830 M2004-01-622.0800 Series Model VCSO Center Frequency (i.e. 622.0800MHz) Micro Networks makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are non-infringing on any valid US or foreign patents. Micro Networks assumes no liability as a result of the use of said specifications and reserves the right to make changes to specifications without notice. Contact your nearest Micro Networks sales representative office for the latest specifications. Micro Networks An Integrated Circuit Systems Company 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 European Sales Headquarters Hertogsingel 20 6214 AD Maastricht The Netherlands tel: +31-43-32-70912 fax: +31-43-32-70715 Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com www.micronetworks.com 10 Rev. 13.0