STMICROELECTRONICS M29W004T

M29W004T
M29W004B
4 Mbit (512Kb x8, Boot Block)
Low Voltage Single Supply Flash Memory
NOT FOR NEW DESIGN
M29W004T and M29W004B are replaced
respectively by the M29W004BT and
M29W004BB
2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 100ns
FAST PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M29W004T: EAh
– Device Code, M29W004B: EBh
TSOP40 (N)
10 x 20 mm
Figure 1. Logic Diagram
DESCRIPTION
The M29W004 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V VCC supply. For
Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against programing and erase on programming equipment,
and temporarily unprotected to make changes in
June 1999
This is information on a product still in production but not recommended for new designs.
VCC
19
8
A0-A18
DQ0-DQ7
W
E
M29W004T
M29W004B
RB
G
RP
VSS
AI02063
1/30
M29W004T, M29W004B
Figure 2. TSOP Pin Connections
A16
A15
A14
A13
A12
A11
A9
A8
W
RP
NC
RB
A18
A7
A6
A5
A4
A3
A2
A1
1
10
11
Table 1. Signal Names
A17
VSS
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
G
VSS
E
A0
40
M29W004T
M29W004B
31
30
20
21
A0-A18
Address Inputs
DQ0-DQ7
Data Input/Outputs, Command Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset / Block Temporary Unprotect
RB
Ready/Busy Output
VCC
Supply Voltage
VSS
Ground
cycles of commands to a Command Interface using
standard microprocessor write timings.
The device is offered in TSOP40 (10 x 20mm)
package.
Organisation
The M29W004 is organised as 512K x8. The memory uses the address inputs A0-A18 and the Data
Input/Outputs DQ0-DQ7. Memory control is provided by Chip Enable E, Output Enable G and Write
Enable W inputs.
AI02064
Warning: NC = Not Connected.
DESCRIPTION (Cont’d)
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written to the device in
A Reset/Block Temporary Unprotection RP tri-level
input provides a hardware reset when pulled Low,
and when held High (at VID) temporarily unprotects
blocks previously protected allowing them to be
programed and erased. Erase and Program operations are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
TA
Ambient Operating Temperature
Value
(3)
Unit
–40 to 85
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
Input or Output Voltages
–0.6 to 5
V
Supply Voltage
–0.6 to 5
V
A9, E, G, RP Voltage
–0.6 to 13.5
V
VIO
(2)
VCC
V(A9, E, G, RP)
(2)
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
2/30
M29W004T, M29W004B
Memory Blocks
The devices feature asymmetrically blocked architecture providing system memory integration. Both
M29W004T and M29W004B devices have an array
of 11 blocks, one Boot Block of 16K Bytes, two
Parameter Blocks of 8K Bytes, one Main Block of
32K Bytes and seven Main Blocks of 64K Bytes.
The M29W004T has the Boot Block at the top of
the memory address space and the M29W004B
locates the Boot Block starting at the bottom. The
memory maps are showed in Figure 3. Each block
can be erased separately, any combination of
blocks can be specified for multi-block erase or the
entire chip may be erased. The Erase operations
are managed automatically by the P/E.C. The block
erase operation can be suspended in order to read
from or program to any block not being ersased,
and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unprotected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write command, Output Disable, Standby, Reset, Block Prot e ct i on , U n pr ot e ct ion , Pro t ect ion Ve rif y,
Unprotection Verify and Block Temporary Unprotection. See Tables 4 and 5.
Command Interface
Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Program/Erase Controller instructions. The ’Command’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command sequence will reset the device to Read Array mode.
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signature
or Block Protection Status), Program, Block Erase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all timing and verification of the Program and Erase
operations. The Status Register Data Polling, Toggle, Error bits and the RB output may be read at
any time, during programming or erase, to monitor
the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all instructions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection, the instructions for Program and Block or Chip Erase require
further command inputs. For a Program instruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data from
another block or to program data in another block,
and then resumed.
When power is first applied or if Vcc falls below
VLKO, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A18). The address inputs for
the memory array are latched during a write operation on the falling edge of Chip Enable E or Write
Enable W. In Word-wide organisation the address
lines are A0-A18. When A9 is raised to VID, either
a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block
Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1, A6,
A12 and A15.
Data Input/Outputs (DQ0-DQ7). The input is data
to be programmed in the memory array or a command to be written to the C.I. Both are latched on
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputs are disabled and when RP is at a Low level.
Chip Enable (E). The Chip Enable input activates
the memory control logic, input buffers, decoders
and sense amplifiers. E High deselects the memory
and reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to VID during the Block Unprotection operation.
3/30
M29W004T, M29W004B
Figure 3. Memory Map and Block Address Table (x8)
M29W004T
7FFFFh
M29W004B
7FFFFh
16K BOOT BLOCK
7C000h
7BFFFh
64K MAIN BLOCK
70000h
6FFFFh
64K MAIN BLOCK
8K PARAMETER BLOCK
7A000h
79FFFh
60000h
5FFFFh
64K MAIN BLOCK
8K PARAMETER BLOCK
78000h
77FFFh
50000h
4FFFFh
64K MAIN BLOCK
32K MAIN BLOCK
40000h
3FFFFh
70000h
6FFFFh
64K MAIN BLOCK
64K MAIN BLOCK
30000h
2FFFFh
60000h
5FFFFh
64K MAIN BLOCK
64K MAIN BLOCK
20000h
1FFFFh
50000h
4FFFFh
64K MAIN BLOCK
64K MAIN BLOCK
40000h
3FFFFh
30000h
2FFFFh
10000h
0FFFFh
32K MAIN BLOCK
64K MAIN BLOCK
08000h
07FFFh
64K MAIN BLOCK
20000h
1FFFFh
06000h
05FFFh
8K PARAMETER BLOCK
64K MAIN BLOCK
10000h
0FFFFh
8K PARAMETER BLOCK
04000h
03FFFh
64K MAIN BLOCK
00000h
16K BOOT BLOCK
00000h
AI02093
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to VID level during
Block Protection and Unprotection operations.
Write Enable (W). This input controls writing to the
Command Register and Address and Data latches.
Ready/Busy Output (RB). Ready/Busy is an
open-drain output and gives the internal state of the
P/E.C. of the device. When RB is Low, the device
is Busy with a Program or Erase operation and it
will not accept any additional program or erase
instructions except the Erase Suspend instruction.
When RB is High, the device is ready for any Read,
Program or Erase operation. The RB will also be
High when the memory is put in Erase Suspend or
Standby modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and protected block(s) temporary unprotection functions.
Reset of the memory is acheived by pulling RP to
VIL for at least tPLPX. When the reset pulse is given,
4/30
if the memory is in Read or Standby modes, it will
be available for new operations in tPHEL after the
rising edge of RP. If the memory is in Erase, Erase
Suspend or Program modes the reset will take
tPLYH during which the RB signal will be held at VIL.
The end of the memory reset will be indicated by
the rising edge of RB. A hardware reset during an
Erase or Program operation will corrupt the data
being programmed or the sector(s) being erased.
See Table 14 and Figure 9.
Temporary block unprotection is made by holding
RP at VID. In this condition previously protected
blocks can be programmed or erased. The transition of RP from VIH to VID must slower than tPHPHH.
When RP is returned from VID to VIH all blocks
temporarily unprotected will be again protected.
See Table 15 and Figure 9.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
M29W004T, M29W004B
Table 3A. M29W004T Block Address Table
Address Range
A18
A17
A16
A15
A14
A13
00000h-0FFFFh
0
0
0
X
X
X
10000h-1FFFFh
0
0
1
X
X
X
20000h-2FFFFh
0
1
0
X
X
X
30000h-3FFFFh
0
1
1
X
X
X
40000h-4FFFFh
1
0
0
X
X
X
50000h-5FFFFh
1
0
1
X
X
X
60000h-6FFFFh
1
1
0
X
X
X
70000h-77FFFh
1
1
1
0
X
X
78000h-79FFFh
1
1
1
1
0
0
7A000h-7BFFFh
1
1
1
1
0
1
7C000h-7FFFFh
1
1
1
1
1
X
Table 3B. M29W004B Block Address Table
Address Range
A18
A17
A16
A15
A14
A13
00000h-03FFFh
0
0
0
0
0
X
04000h-05FFFh
0
0
0
0
1
0
06000h-07FFFh
0
0
0
0
1
1
08000h-0FFFFh
0
0
0
1
X
X
10000h-1FFFFh
0
0
1
X
X
X
20000h-2FFFFh
0
1
0
X
X
X
30000h-3FFFFh
0
1
1
X
X
X
40000h-4FFFFh
1
0
0
X
X
X
50000h-5FFFFh
1
0
1
X
X
X
60000h-6FFFFh
1
1
0
X
X
X
70000h-7FFFFh
1
1
1
X
X
X
5/30
M29W004T, M29W004B
DEVICE OPERATIONS
See Tables 4, 5 and 6.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
Write. Write operations are used to give Instruction
Commands to the memory or to latch input data to
be programmed. A write operation is initiated when
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whichever occurs last.
Commands and Input Data are latched on the rising
edge of W or E whichever occurs first.
Output Disable. The data outputs are high impedance when the Output Enable G is High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
Automatic Standby. After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumption is reduced to the CMOS
standby value, while outputs still drive the bus.
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for STMicroelectronics is 20h, the device code is EAh for
the M29W004T (Top Boot) and EBh for the
M29W004B (Bottom Boot). These codes allow programming equipment or applications to automatically match their interface to the characteristics of
the M29W004. The Electronic Signature is output
by a Read operation when the voltage applied to
A9 is at VID and address input A1 is Low. The
manufacturer code is output when the Address
input A0 is Low and the device code when this
input is High. Other Address inputs are ignored.
The Electronic Signature can also be read, without
raising A9 to VID, by giving the memory the Instruction AS.
6/30
Block Protection. Each block can be separately
protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or
erase operations. This mode is activated when both
A9 and G are raised to VID and an address in the
block is applied on A13-A18. The Block Protection
algorithm is shown in Figure 14. Block protection is
initiated on the edge of W falling to VIL. Then after
a delay of 100µs, the edge of W rising to VIH ends
the protection operations. Block protection verify is
achieved by bringing G, E, A0 and A6 to VIL and A1
to VIH, while W is at VIH and A9 at VID. Under these
conditions, reading the data output will yield 01h if
the block defined by the inputs on A13-A18 is
protected. Any attempt to program or erase a protected block will be ignored by the device.
Block Temporary Unprotection. Any previously
protected block can be temporarily unprotected in
order to change stored data. The temporary unprotection mode is activated by bringing RP to VID.
During the temporary unprotection mode the previously protected blocks are unprotected. A block
can be selected and data can be modified by
executing the Erase or Program instruction with the
RP signal held at VID. When RP is returned to VIH,
all the previously protected blocks are again protected.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9, G and E are at
VID and A12, A15 at VIH. The Block Unprotection
algorithm is shown in Figure 15. Unprotection is
initiated by the edge of W falling to VIL. After a delay
of 10ms, the unprotection operation will end. Unprotection verify is achieved by bringing G and E to
VIL while A0 is at VIL, A6 and A1 are at VIH and A9
remains at VID. In these conditions, reading the
output data will yield 00h if the block defined by the
inputs A13-A18 has been succesfully unprotected.
Each block must be separately verified by giving its
address in order to ensure that it has been unprotected.
M29W004T, M29W004B
Table 4. User Bus Operations (1)
Operation
E
G
W
RP
A0
A1
A6
A9
A12
A15
DQ0-DQ7
Read Byte
VIL
VIL
VIH
VIH
A0
A1
A6
A9
A12
A15
Data Output
Write Byte
VIL
VIH
VIL
VIH
A0
A1
A6
A9
A12
A15
Data Input
Output Disable
VIL
VIH
VIH
VIH
X
X
X
X
X
X
Hi-Z
Standby
VIH
X
X
VIH
X
X
X
X
X
X
Hi-Z
X
X
X
VIL
X
X
X
X
X
X
Hi-Z
Block
Protection(2,4)
VIL
VID
VIL Pulse
VIH
X
X
X
VID
X
X
X
Blocks
Unprotection(4)
VID
VID
VIL Pulse
VIH
X
X
X
VID
VIH
VIH
X
Block
Protection
Verify(2,4)
VIL
VIL
VIH
VIH
VIL
VIH
VIL
VID
A12
A15
Block
Protect
Status (3)
Block
Unprotection
Verify(2,4)
VIL
VIL
VIH
VIH
VIL
VIH
VIH
VID
A12
A15
Block
Protect
Status (3)
Block
Temporary
Unprotection
X
X
X
VID
X
X
X
X
X
X
X
Reset
Notes: 1.
2.
3.
4.
X = VIL or VIH
Block Address must be given on A13-A18 bits.
See Table 6.
Operation performed on programming equipment.
Table 5. Read Electronic Signature (following AS instruction or with A9 = VID)
Org.
Wordwide
Bytewide
E
G
W
A0
A1
Other
Addresses
DQ0DQ7
VIL
VIL
VIH
VIL
VIL
Don’t Care
20h
M29W004T
VIL
VIL
VIH
VIH
VIL
Don’t Care
EAh
M29W004B
VIL
VIL
VIH
VIH
VIL
Don’t Care
EBh
VIL
VIL
VIH
VIL
VIL
Don’t Care
20h
M29W004T
VIL
VIL
VIH
VIH
VIL
Don’t Care
EAh
M29W004B
VIL
VIL
VIH
VIH
VIL
Don’t Care
EBh
Code
Device
Manufact. Code
Device Code
Manufact. Code
Device Code
Table 6. Read Block Protection with AS Instruction
E
G
W
A0
A1
A13-A18
Other
Addresses
DQ0-DQ7
Protected Block
VIL
VIL
VIH
VIL
VIH
Block Address
Don’t Care
01h
Unprotected Block
VIL
VIL
VIH
VIL
VIH
Block Address
Don’t Care
00h
Code
7/30
M29W004T, M29W004B
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands written to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Protection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The instructions require from 1 to 6 cycles, the first or first
three of which are always write operations used to
initiate the instruction. They are followed by either
further write cycles to confirm the first command or
execute the command immediately. Command sequencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security.
Instructions are initialised by two initial Coded cycles which unlock the Command Interface. In addition, for Erase, instruction confirmation is again
preceded by the two Coded cycles.
Status Register Bits
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase command execution will automatically output these five
Status Register bits. The P/E.C. automatically sets
Table 7. Commands
Hex Code
8/30
Command
00h
Invalid/Reserved
10h
Chip Erase Confirm
20h
Reserved
30h
Block Erase Resume/Confirm
80h
Set-up Erase
90h
Read Electronic Signature/
Block Protection Status
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After completion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be performed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to ’0’ for about 100µs, and then return to the
previous addressed memory data value. See Figure 11 for the Data Polling flowchart and Figure 10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
on a block being erased and the data value on other
blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behaviour as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6). When Programming or Erasing
operations are in progress, successive attempts to
read DQ6 will output complementary data. DQ6 will
toggle following toggling of either G, or E when G
is low. The operation is completed when two successive reads yield the same output data. The next
read will output the bit last programmed or a ’1’ after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are protected, DQ6 will toggle for about 100µs and then
return back to Read. DQ6 will be set to ’1’ if a Read
operation is attempted on an Erase Suspend block.
When erase is suspended DQ6 will toggle during
programming operations in a block different to the
block in Erase Suspend. Either E or G toggling will
cause DQ6 to toggle. See Figure 12 for Toggle Bit
flowchart and Figure 13 for Toggle Bit waveforms.
M29W004T, M29W004B
Table 8. Instructions (1)
Mne.
RD (2,4)
Instr.
Read/Reset
Memory
Array
Cyc.
1+
1st Cyc. 2nd Cyc. 3rd Cyc.
Addr.
(3,7)
Data
3+
Addr. (3,7)
Addr.
Auto Select
(3,7)
Addr. (3,7)
Program
Block Erase
6
Addr. (3,7)
Data
CE
Chip Erase
6
Addr.
(3,7)
Data
ES (10)
ER
Erase
Suspend
Erase
Resume
5555h
2AAAh
5555h
AAh
55h
F0h
5555h
2AAAh
5555h
AAh
55h
90h
5555h
2AAAh
5555h
AAh
55h
A0h
5555h
2AAAh
5555h
5555h
2AAAh
AAh
55h
80h
AAh
55h
30h
5555h
2AAAh
5555h
5555h
2AAAh
5555h
AAh
55h
80h
AAh
55h
10h
4
Data
BE
1
Addr. (3,7)
Data
1
Addr.
Data
6th Cyc.
7th Cyc.
Read Memory Array until a new write cycle is initiated.
3+
Data
PG
5th Cyc.
F0h
Data
AS (4)
X
4th Cyc.
X
B0h
(3,7)
X
30h
Read Memory Array until a new write cycle
is initiated.
Read Electronic Signature or Block
Protection Status until a new write cycle is
initiated. See Note 5 and 6.
Program
Address Read Data Polling or Toggle Bit
until Program completes.
Program
Data
Block
Additional
Address Block (8)
30h
Note 9
Read until Toggle stops, then read all the data needed from any
Block(s) not being erased then Resume Erase.
Read Data Polling or Toggle Bits until Erase completes or Erase
is suspended another time
Notes: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation (See Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles.
5. Signature Address bits A0, A1 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output
Device code.
6. Block Protection Address: A0 at VIL, A1 at VIH and A13-A18 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A15-A18 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status
can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling
or Toggle bit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
9/30
M29W004T, M29W004B
Table 9. Status Register Bits
DQ
7
Name
Data
Polling
Logic Level
’1’
Erase Complete or erase
block in Erase Suspend
’0’
Erase On-going
DQ
Program Complete or data
of non erase block during
Erase Suspend
DQ
Program On-going
’-1-0-1-0-1-0-1-’
6
Toggle Bit
DQ
’-1-1-1-1-1-1-1-’
5
4
3
Error Bit
Erase or Program On-going
Program Complete
Erase Complete or Erase
Suspend on currently
addressed block
Note
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
’1’
Program or Erase Error
’0’
Program or Erase On-going
’1’
Erase Timeout Period Expired
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES).
’0’
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
This bit is set to ’1’ in the case of
Programming or Erase failure.
Reserved
Erase
Time Bit
’-1-0-1-0-1-0-1-’
2
Definition
Toggle Bit
1
DQ
1
Reserved
0
Reserved
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the
currently addressed block
(when DQ5 = ’1’).
Indicates the erase status and allows to
identify the erased block
Program on-going, Erase
on-going on another block or
Erase Complete
Erase Suspend read on
non Erase Suspend block
Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
10/30
M29W004T, M29W004B
Table 10. Polling and Toggle Bits
Mode
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Note 1
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Program
confirmation command. The Coded cycles consist
of writing the data AAh at address 5555h during the
first cycle. During the second cycle the Coded
cycles consist of writing the data 55h at address
2AAAh. A0 to A14 are valid, other address lines are
’don’t care’. The Coded cycles happen on first and
second cycles of the command write or on the
fourth and fifth cycles.
Instructions
See Table 8.
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
N/A
Note: 1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. It can also be used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
during program operation and when erase is complete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block erase
or program, the block in which the error occured or
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also appear if a user tries to program a ’1’ to a location that
is previously programmed to ’0’. Other Blocks may
still be used. The error bit resets after a Read/Reset
(RD) instruction. In case of success of Program or
Erase, the error bit will be set to ’0’ .
Erase Timer Bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50µs to 90µs, DQ3 returns
to ’1’.
Coded Cycles
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by the
two Coded cycles. Subsequent read operations will
read the memory array addressed and output the
data read. A wait state of 10µs is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 5555h
for command set-up. A subsequent read will output
the manufacturer code and the device code or the
block protection status depending on the levels of
A0 and A1 The manufacturer code, 20h, is output
when the addresses lines A0 and A1 are Low, the
device code, EAh for Top Boot, EBh for Bottom
Boot is output when A0 is High with A1 Low.
The AS instruction also allows access to the block
protection status. After giving the AS instruction, A0
and A6 are set to VIL with A1 at VIH, while A13-A18
define the address of the block to be verified. A read
in these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 5555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or E and the Data
to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the address being programmed.
The two Coded cycles unlock the Command Interface. They are followed by an input command or a
11/30
M29W004T, M29W004B
Table 11. AC Measurement Conditions
Figure 5. AC Testing Load Circuit
Input Rise and Fall Times
≤ 10ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
0.8V
1N914
1.5V
Figure 4. AC Testing Input Output Waveform
3.3kΩ
DEVICE
UNDER
TEST
3V
OUT
CL = 30pF or 100pF
1.5V
0V
CL includes JIG capacitance
AI01417
AI01968
Table 12. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 13. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
Supply Current (Read) Byte
E = VIL, G = VIH, f = 6MHz
10
mA
ICC1
Supply Current (Read) Word
E = VIL, G = VIH, f = 6MHz
10
mA
ICC3
Supply Current (Standby)
E = VCC ± 0.2V
50
µA
Byte program, Block or
Chip Erase in progress
20
mA
ICC4 (1)
Supply Current (Program or Erase)
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.3
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage CMOS
VID
A9 Voltage (Electronic Signature)
IID
A9 Current (Electronic Signature)
VLKO
Supply Voltage (Erase and
Program lock-out)
Note: 1. Sampled only, not 100% tested.
12/30
IOL = 4mA
IOH = –100µA
VCC –0.4V
11.0
A9 = VID
2.0
V
12.0
V
100
µA
2.3
V
M29W004T, M29W004B
Table 14A. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W004T / M29W004B
Symbol
Alt
Parameter
Test
Condition
-90
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
tELQX (1)
tLZ
Chip Enable Low to Output Transition
G = VIL
(2)
tCE
Chip Enable Low to Output Valid
G = VIL
tGLQX (1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
tGLQV (2)
tOE
Output Enable Low to Output Valid
E = VIL
tEHQX
tOH
Chip Enable High to Output Transition
G = VIL
tHZ
Chip Enable High to Output Hi-Z
G = VIL
tGHQX
tOH
Output Enable High to Output
Transition
E = VIL
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
E = VIL
tAXQX
tOH
Address Transition to Output
Transition
E = VIL,
G = VIL
tELQV
tEHQZ
(1)
tPLYH (1,3)
Unit
VCC = 3.0V to 3.6V VCC = 2.7V to 3.6V
CL = 30pF
CL = 30pF
Min
tAVAV
-100
Max
90
Min
100
90
0
ns
100
0
90
0
0
0
0
0
0
0
ns
ns
30
0
10
ns
ns
30
30
ns
ns
40
30
ns
ns
100
35
tRRB
RP Low to Read Mode
tREADY
Max
ns
ns
10
µs
tPHEL
tRH
RP High to Chip Enable Low
50
50
ns
tPLPX
tRP
RP Pulse Width
500
500
ns
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
3. To be considered only if the Reset pulse is given while the memory is in Erase mode.
13/30
M29W004T, M29W004B
Table 14B. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W004T / M29W004B
Symbol
Alt
Parameter
Test
Condition
-120
-150
Unit
VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V
Min
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
tELQX (1)
tLZ
Chip Enable Low to Output Transition
G = VIL
tELQV (2)
tCE
Chip Enable Low to Output Valid
G = VIL
tGLQX (1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
tGLQV (2)
tOE
Output Enable Low to Output Valid
E = VIL
tEHQX
tOH
Chip Enable High to Output Transition
G = VIL
tHZ
Chip Enable High to Output Hi-Z
G = VIL
tGHQX
tOH
Output Enable High to Output
Transition
E = VIL
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
E = VIL
tAXQX
tOH
Address Transition to Output
Transition
E = VIL,
G = VIL
tEHQZ
(1)
tPLYH (1,3)
Max
120
Min
150
120
0
ns
150
0
120
0
0
0
0
0
0
0
ns
ns
40
0
10
ns
ns
40
30
ns
ns
55
30
ns
ns
150
50
tRRB
RP Low to Read Mode
tREADY
Max
ns
ns
10
µs
tPHEL
tRH
RP High to Chip Enable Low
50
50
ns
tPLPX
tRP
RP Pulse Width
500
500
ns
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV.
3. To be considered only if the Reset pulse is given while the memory is in Erase mode.
14/30
Note: Write Enable (W) = High.
DQ0-DQ7
G
E
A0-A18
ADDRESS VALID
AND CHIP ENABLE
tAVQV
tGLQV
OUTPUT ENABLE
tGLQX
tELQX
tELQV
VALID
tAVAV
DATA VALID
VALID
tGHQZ
tGHQX
tEHQX
tEHQZ
tAXQX
AI02094
M29W004T, M29W004B
Figure 6. Read Mode AC Waveforms
15/30
M29W004T, M29W004B
Table 15A. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W004T / M29W004B
Symbol
Alt
-90
-100
VCC = 3.0V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 30pF
Parameter
Min
Max
Min
Unit
Max
tAVAV
tWC
Address Valid to Next Address Valid
90
100
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
45
50
ns
tDVWH
tDS
Input Valid to Write Enable High
45
50
ns
tWHDX
tDH
Write Enable High to Input Transition
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
ns
tWPH Write Enable High to Write Enable Low
30
30
ns
tWHWL
tAVWL
tAS
Address Valid to Write Enable Low
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
45
50
ns
Output Enable High to Write Enable Low
0
0
ns
tGHWL
tVCHEL
tVCS
VCC High to Chip Enable Low
50
50
µs
tWHGL
tOEH
Write Enable High to Output Enable Low
0
0
ns
500
500
ns
500
500
ns
tPHPHH (1,2)
tPLPX
tWHRL
(1)
tPHWL
(1)
tVIDR RP Rise Time to VID
tRP
RP Pulse Width
tBUSY Program Erase Valid to RB Delay
tRSP
RP High to Write Enable Low
90
4
90
4
ns
µs
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two Coded cycles. The Block
Erase Confirm command 30h is similarly written on
the sixth cycle after another two Coded cycles.
During the input of the second command an address within the block to be erased is given and
latched into the memory. Additional block Erase
Confirm commands and block addresses can be
written subsequently to erase other blocks in parallel, without further Coded cycles. The erase will
start after the erase timeout period (see Erase
Timer Bit DQ3 description). Thus, additional Erase
16/30
Confirm commands for other blocks must be given
within this delay. The input of a new Erase Confirm
command will restart the timeout period. The status
of the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running, if
DQ3 is ’1’, the timeout has expired and the P/E.C.
is erasing the Block(s). If the second command
given is not an erase confirm or if the Coded cycles
are wrong, the instruction aborts, and the device is
reset to Read Array. It is not necessary to program
the block with 00h as the P/E.C. will do this automatically before to erasing to FFh. Read operations
M29W004T, M29W004B
Table 15B. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W004T / M29W004B
Symbol
Alt
-120
-150
VCC = 2.7V to 3.6V
VCC = 2.7V to 3.6V
Parameter
Min
tAVAV
tWC
Address Valid to Next Address Valid
tELWL
tCS
tWLWH
Max
Min
Unit
Max
120
150
ns
Chip Enable Low to Write Enable Low
0
0
ns
tWP
Write Enable Low to Write Enable High
50
65
ns
tDVWH
tDS
Input Valid to Write Enable High
50
65
ns
tWHDX
tDH
Write Enable High to Input Transition
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
ns
tWPH Write Enable High to Write Enable Low
30
35
ns
tWHWL
tAVWL
tAS
Address Valid to Write Enable Low
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
50
65
ns
Output Enable High to Write Enable Low
0
0
ns
tGHWL
tVCHEL
tVCS
VCC High to Chip Enable Low
50
50
µs
tWHGL
tOEH
Write Enable High to Output Enable Low
0
0
ns
500
500
ns
500
500
ns
tPHPHH
(1,2)
tPLPX
tWHRL (1)
tPHWL
(1)
tVIDR RP Rise Time to VID
tRP
RP Pulse Width
tBUSY Program Erase Valid to RB Delay
tRSP
RP High to Write Enable Low
90
4
90
4
ns
µs
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Chip Erase (CE) Instruction. This instruction uses
six write cycles. The Erase Set-up command 80h
is written to address 5555h on the third cycle after
the two Coded cycles. The Chip Erase Confirm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts and
the device is reset to Read Array. It is not necessary
to program the array with 00h first as the P/E.C. will
automatically do this before erasing it to FFh. Read
operations after the sixth rising edge of W or E
output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7
returns ’0’, then ’1’ on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
after the sixth rising edge of W or E output the
status register status bits.
During the execution of the erase by the P/E.C., the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/Reset RD instruction is necessary in order to
reset the P/E.C.
17/30
M29W004T, M29W004B
Figure 7. Write AC Waveforms, W Controlled
tAVAV
A0-A18
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
AI02095
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
stop when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has been
an Erase Failure.
Erase Suspend (ES) Instruction. The Block
Erase operation may be suspended by this instruction which consists of writing the command B0h
without any specific address. No Coded cycles are
required. It permits reading of data from another
block and programming in another block while an
erase operation is in progress. Erase suspend is
accepted only during the Block Erase instruction
execution. Writing this command during Erase
timeout will, in addition to suspending the erase,
terminate the timeout. The Toggle bit DQ6 stops
toggling when the P/E.C. is suspended. The Toggle
18/30
bits will stop toggling between 0.1µs and 15µs after
the Erase Suspend (ES) command has been written. The device will then automatically be set to
Read Memory Array mode. When erase is suspended, a Read from blocks being erased will
output DQ2 toggling and DQ6 at ’1’. A Read from
a block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instructions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in both DQ2 and DQ6 toggling
when the data is being programmed. A Read/Reset
command will definitively abort erasure and result
in invalid data in the blocks being erased.
M29W004T, M29W004B
Table 16A. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W004T / M29W004B
Symbol
Alt
-90
-100
VCC = 3.0V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 30pF
Parameter
Min
Max
Min
Unit
Max
tAVAV
tWC
Address Valid to Next Address Valid
90
100
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
45
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
45
5
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
20
20
ns
tAVEL
tAS
Address Valid to Chip Enable Low
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
45
50
ns
Output Enable High Chip Enable Low
0
0
ns
tGHEL
tVCHWL
tVCS
VCC High to Write Enable Low
50
50
µs
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
0
ns
tPHPHH (1,2)
tVIDR
RP Rise TIme to VID
500
500
ns
tPLPX
tRP
RP Pulse Width
500
500
ns
tEHRL
(1)
tBUSY
Program Erase Valid to RB Delay
tPHWL
(1)
tRSP
RP High to Write Enable Low
90
4
90
4
ns
µs
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
POWER SUPPLY
Power Up
The memory Command Interface is reset on power
up to Read Array. Either E or W must be tied to VIH
during Power Up to allow maximum security and
the possibility to write a command on the first rising
edge of E and W. Any write cycle initiation is
blocked when Vcc is below VLKO.
Supply Rails
Normal precautions must be taken for supply voltage decoupling; each device in a system should
have the VCC rail decoupled with a 0.1µF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC program and erase currents required.
19/30
M29W004T, M29W004B
Table 16B. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W004T / M29W004B
Symbol
Alt
-150
VCC = 2.7V to 3.6V
VCC = 2.7V to 3.6V
Min
tAVAV
tWC
Address Valid to Next Address Valid
tWLEL
tWS
tELEH
Unit
-120
Parameter
Max
Min
Max
120
150
ns
Write Enable Low to Chip Enable Low
0
0
ns
tCP
Chip Enable Low to Chip Enable High
50
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
50
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
20
20
ns
tAVEL
tAS
Address Valid to Chip Enable Low
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
50
50
ns
Output Enable High Chip Enable Low
0
0
ns
tGHEL
tVCHWL
tVCS
VCC High to Write Enable Low
50
50
µs
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
0
ns
tVIDR
RP Rise TIme to VID
500
500
ns
RP Pulse Width
500
500
ns
tPHPHH
(1,2)
tPLPX
tRP
tEHRL (1)
tBUSY
Program Erase Valid to RB Delay
tRSP
RP High to Write Enable Low
tPHWL
(1)
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
20/30
90
4
90
4
ns
µs
M29W004T, M29W004B
Figure 8. Write AC Waveforms, E Controlled
tAVAV
VALID
A0-A18
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
AI02096
Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
Figure 9. Read and Write AC Characteristics, RP Related
E
tPHEL
W
tPHWL
RB
RP
tPLPX
tPHPHH
tPLYH
AI02091
21/30
M29W004T, M29W004B
Table 17A. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W004T / M29W004B
Symbol
tWHQ7V
tEHQ7V
tQ7VQV
tWHQV
tEHQV
-90
-100
VCC = 3.0V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 30pF
Parameter
Unit
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
10
2400
10
2400
ms
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled)
1.0
30
1.0
30
sec
Chip Enable High to DQ7 Valid
(Program, E Controlled)
10
2400
10
2400
µs
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled)
1.0
30
1.0
30
sec
40
ns
Q7 Valid to Output Valid (Data Polling)
35
Write Enable High to Output Valid (Program)
10
2400
10
2400
µs
Write Enable High to Output Valid (Chip Erase)
1.0
30
1.0
30
sec
Chip Enable High to Output Valid (Program)
10
2400
10
2400
µs
Chip Enable High to Output Valid (Chip Erase)
1.0
30
1.0
30
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
Table 17B. Data Polling and Toggle Bit AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
(1)
M29W004T / M29W004B
Symbol
tWHQ7V
tEHQ7V
tQ7VQV
tWHQV
tEHQV
-150
VCC = 2.7V to 3.6V
VCC = 2.7V to 3.6V
Unit
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
10
2400
10
2400
ms
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled)
1.0
30
1.0
30
sec
Chip Enable High to DQ7 Valid
(Program, E Controlled)
10
2400
10
2400
µs
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled)
1.0
30
1.0
30
sec
55
ns
Q7 Valid to Output Valid (Data Polling)
50
Write Enable High to Output Valid (Program)
10
2400
10
2400
µs
Write Enable High to Output Valid (Chip Erase)
1.0
30
1.0
30
sec
Chip Enable High to Output Valid (Program)
10
2400
10
2400
µs
Chip Enable High to Output Valid (Chip Erase)
1.0
30
1.0
30
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
22/30
-120
Parameter
DQ0-DQ6
DQ7
W
G
E
A0-A18
LAST WRITE
CYCLE OF
PROGRAM
OR ERASE
INSTRUCTION
DATA POLLING
READ CYCLES
tWHQ7V
tEHQ7V
tELQV
tAVQV
tQ7VQV
IGNORE
DQ7
DATA POLLING (LAST) CYCLE
tGLQV
ADDRESS (WITHIN BLOCKS)
VALID
VALID
DATA OUTPUT VALID
AI02097
MEMORY
ARRAY
READ CYCLE
M29W004T, M29W004B
Figure 10. Data Polling DQ7 AC Waveforms
23/30
M29W004T, M29W004B
Figure 11. Data Polling Flowchart
Figure 12. Data Toggle Flowchart
START
START
READ
DQ2, DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
NO
NO
YES
NO
DQ5
=1
DQ5
=1
YES
YES
READ DQ7
DQ7
=
DATA
NO
DQ2, DQ6
=
TOGGLE
YES
READ DQ2, DQ6
YES
DQ2, DQ6
=
TOGGLE
NO
FAIL
NO
YES
PASS
FAIL
PASS
AI01369
AI01873
Table 18. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VCC = 2.7V to 3.6V)
M29W004T / M29W004B
Parameter
Unit
Typ
Typical after
100k W/E Cycles
Chip Erase (Preprogrammed)
1.5
1.7
sec
Chip Erase
6.7
7.0
sec
Boot Block Erase
0.7
sec
Parameter Block Erase
0.6
sec
Main Block (32Kb) Erase
0.9
sec
Main Block (64Kb) Erase
1.4
sec
Chip Program (Byte)
8.2
8.2
sec
Byte Program
10
10
µs
Min
Program/Erase Cycles (per Block)
24/30
100,000
cycles
DATA
TOGGLE
READ CYCLE
Note: All other timings are as a normal Read cycle.
LAST WRITE
CYCLE OF
PROGRAM
OF ERASE
INSTRUCTION
DQ0-DQ1,DQ3-DQ5,DQ7
DQ6,DQ2
W
G
E
A0-A18
DATA TOGGLE
READ CYCLE
IGNORE
STOP TOGGLE
tWHQV
tEHQV
tAVQV
MEMORY ARRAY
READ CYCLE
VALID
VALID
tGLQV
tELQV
VALID
AI02098
M29W004T, M29W004B
Figure 13. Data Toggle DQ6, DQ2 AC Waveforms
25/30
M29W004T, M29W004B
Figure 14. Block Protection Flowchart
START
BLOCK ADDRESS
on A13-A18
W = VIH
Set-up
n=0
G, A9 = VID,
E = VIL
Wait 4µs
W = VIL
Protect
Wait 100µs
W = VIH
E, G = VIH
Verify
VERIFY BLOCK PROTECTION
A0, A6 = VIL; A1 = VIH; A9 = VID
A13-A18 IDENTIFY BLOCK
E = VIL
Wait 4µs
G = VIL
Wait 60ns
VERIFY BLOCK
PROTECT STATUS
DATA
=
01h
NO
YES
A9 = VIH
NO
++n
= 25
PASS
YES
A9 = VIH
FAIL
AI02099B
26/30
M29W004T, M29W004B
Figure 15. All Blocks Unprotecting Flowchart
START
PROTECT
ALL BLOCKS
n=0
Set-up
W = VIH
E, G, A9 = VID
A12, A15 = VIH
Wait 4µs
W = VIL
Wait 10ms
Unprotect
W = VIH
E, G = VIH
Verify
E, A0 = VIL; A1, A6 = VIH; A9 = VID
A13-A18 IDENTIFY BLOCK
NEXT
BLOCK
Wait 4µs
G = VIL
Wait 60ns
VERIFY BLOCK
PROTECT STATUS
NO
NO
++n
= 1000
YES
DATA
=
00h
YES
LAST
BLK.
NO
YES
A9 = VIH
A9 = VIH
FAIL
PASS
AI02100C
27/30
M29W004T, M29W004B
ORDERING INFORMATION SCHEME
Example:
M29W004T
-90
N
1
TR
Operating Voltage
W
Option
2.7V to 3.6V
Array Matrix
TR Tape & Reel
Packing
Speed
T
Top Boot
-90 90ns
B
Bottom Boot
-100 100ns
Temp. Range
Package
N
TSOP40
10 x 20mm
-120 120ns
1
0 to 70 °C
5
–20 to 85 °C
6
–40 to 85 °C
-150 150ns
M29W004T and M29W004B are replaced respectively by the new version M29W004BT and
M29W004BB
Devices are shipped from the factory with the memory content erased (to FFh).
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
28/30
M29W004T, M29W004B
TSOP40 Normal Pinout - 40 lead Plastic Thin Small Outline, 10 x 20mm
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
1.20
Max
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
B
0.17
0.27
0.007
0.011
C
0.10
0.21
0.004
0.008
D
19.80
20.20
0.780
0.795
D1
18.30
18.50
0.720
0.728
E
9.90
10.10
0.390
0.398
–
–
–
–
L
0.50
0.70
0.020
0.028
α
0°
5°
0°
5°
N
40
e
0.50
0.020
40
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
29/30
M29W004T, M29W004B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
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30/30