M39832 Single Chip 8 Mbit (1Mb x8 or 512Kb x16) Flash and 256 Kbit Parallel EEPROM Memory PRELIMINARY DATA 2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPARATIONS FLASH ARRAY – Boot block (Top or Bottom location) – Parameter and Main blocks – Selectable x8/x16 Data Bus (BYTE pin). EEPROM ARRAY – x8 Data Bus only. 120ns ACCESS TIME (Flash and EEPROM array) WRITE, PROGRAM and ERASE STATUS BITS CONCURRENT MODE (Read Flash while writing to EEPROM) 100,000 ERASE/WRITE CYCLES 10 YEARS DATA RETENTION LOW POWER CONSUMPTION – Stand-by mode: 100µA – Automatic Stand-by mode 64 bytes ONE TIME PROGRAMMABLE MEMORY (x8 Data Bus only) STANDARD EPROM/OTP MEMORY PACKAGE EXTENDED TEMPERATURE RANGES TSOP48 (NE) 12 x 20 mm Figure 1. Logic Diagram VCC 19 15 A0-A18 DQ0-DQ14 W DESCRIPTION The M39832 is a memory device combining Flash and EEPROM into a single chip and using single supply voltage. The memory is mapped in two arrays: 8 Mbit of Flash memory and 256 Kbit of EEPROM memory. Each space is independant for writing, in concurrent mode the Flash Memory can be read while the EEPROM is being written. An additional 64 bytes of EPROM are One Time Programmable. The M39832 EEPROM memory array is organized in byte only (regardless on the BYTE pin). It may be written by byte or by page of 64 bytes and the integrity of the data can be secured with the help of the Software Data Protection (SDP). EE DQ15A–1 M39832 BYTE EF ERB G FRB RP VSS February 1999 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. AI00844 1/36 M39832 Figure 2. TSOP Pin Connections A15 A14 A13 A12 A11 A10 A9 A8 ERB EE W RP NC NC FRB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 12 13 48 M39832 24 37 36 25 Table 1. Signal Names A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS EF A0 AI00845 Warning: NC = Not Connected. DESCRIPTION (cont’d) The M39832 Flash Memory array can be configured as 1Mb x8 or 512Kb x16 with the BYTE input pin. The M39832-T and M39832-B feature asymetrically blocked architecture providing system memory integration. Both M39832-B and M39832-T devices have a Flash array of 19 blocks, one Boot Block of 16 KBytes or 8 KWords, two Parameter Blocks of 8 KBytes or 4 KWords, one Main Block of 32 KBytes or 16 KWords and fifteen Main Blocks of 64 KBytes or 32 KWords. The M39832-T has the Boot Block at the top of the memory address space and the M39832-B locates the Boot Block starting at the bottom. The memory maps are showed in Figures 3A and 3B. Each block can be erased separately,any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically. The block erase operation can be sus- 2/36 A0-A18 Address Inputs DQ0-DQ7 Data Input/Outputs, Commands Input DQ8-DQ14 Data Input/Outputs DQ15A–1 Data Input/Outputs or Address Input EE EEPROM Array Enable EF Flash Array Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect ERB EEPROM Ready/Busy Output FRB Flash Ready/Busy Output BYTE Flash Array Byte/Word Organization VCC Supply Voltage VSS Ground pended in order to read from or program to any block not being ersased, and then resumed. Block protection provides additional data security. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application. The Flash memory array is functionally compatible with the M29W800 Single Voltage Flash Memory device. During a Program or Erase cycle in the Flash array or during a Write in the EEPROM array, status bits available on certain DQn pins provide information on the M39832 internal logic. PIN DESCRIPTION Byte/Word Organization Select (BYTE). The BYTE input selects the output configuration for the Flash array: Byte-wide (x8) mode or Word-wide (x16) mode. The EEPROM array and the 64 Bytes OTP Row are always accessed Byte-wide (x8). When BYTE is High, the Word-wide mode is selected for the Flash array (x16) and the data are read and programmed on DQ0-DQ15. The Flash array is accessed with A0-A18 Adrress lines. In this mode, data in the EEPROM array (x8) are read and programmed on DQ0-DQ7 and the array is accessed with A0-A14. The 64 bytes OTP are read and programmed on DQ0-DQ7 and are accessed with A0-A5 and A6 = 0. When BYTE is Low, the Byte-wide mode is selected for the Flash array (x8) and the data are read and M39832 Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature –40 to 85 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltages –0.6 to 5 V Supply Voltage –0.6 to 5 V A9, G, EF Voltage –0.6 to 13.5 V TA VCC VA9, VG, VEF (2) Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns. programmed on DQ0-DQ7. In this mode, DQ8DQ14 are at high impedance and DQ15A–1 is the LSB address bit, making the Flash array to be accessed with A–1-A18 Adress lines. In this mode, data in the EEPROM array (x8) are read and programmed on DQ0-DQ7 and the array is accessed with A–1-A13. The 64 bytes OTP are read and programmed on DQ0-DQ7 and are accessed with A-1 - A4 and A6 = 0. Address Inputs (A0-A18). The address inputs for the memory array are latched during a write operation on the falling edge at Chip Enable (EE or EF) or Write Enable W. In Word-wide organisation the address lines are A0-A18, in Byte-wide organisation DQ15A–1 acts as an additional LSB address line. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1, A6, A12 and A15. Data Input/Output (DQ0-DQ7). T he se I nputs/Outputs are used in the Byte-wide and Wordwide organisations. The input is data to be programmed in the memory array or a command to be written. Both are latched on the rising edge of Chip Enable (EE or EF) or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable (EE or EF) and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RP is at a Low level. Data Input/Outputs (DQ8-DQ14 and DQ15A–1). These Inputs/Outputs are additionally used in the Word-wide organisation. When BYTE is High DQ8- DQ14 and DQ15A–1 act as the MSB of the Data Input or Output, functioning as described for DQ0DQ7 above, and DQ8 - DQ15 are ’don’t care’ for command inputs or status outputs. When BYTE is Low, DQ8-DQ14 are high impedance, DQ15A–1 is the Address A–1 input. Memory Array Enable (EE and EF). The Memory Array Enable (EE or EF) activates the memory control logic, input buffers, decoders and sense amplifiers. When the EE input is driven high, the EEPROM memory array is not selected; when the EF input is driven high, the Flash memory array is not selected. Attempts to access both EEPROM and Flash arrays (EE low and EF low) are forbidden. Switching between the two memory array enables (EE and EF) must not be made on the same clock cycle, a delay of greater than tEHFL must be inserted. The M39832 is in standby when both EF and EE are High (when no internal Erase or programming is running). The power consumption is reduced to the standby level and the outputs are in the high impedance state, independent of the Output Enable G or Write Enable W inputs. After 150ns of inactivity and when the addresses are driven at CMOS levels, the chip automatically enters a pseudo standby mode where consumption is reduced to the CMOS standby value, while the outputs continue to drive the bus. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. The data outputs are in the high impedance state when the Output Enable G is High. During Block Protect and Block Unprotect operations, the G input must be forced to VID level (12V + 0.5V) (for Flash memory array only). 3/36 M39832 Figure 3A. Top Boot Block Memory Map and Block Address Table TOP BOOT BLOCK Word-Wide Byte-Wide 7FFFFh FFFFFh Byte-Wide Word-Wide FFFFFh 7FFFFh FC000h FBFFFh 7E000h 7DFFFh FA000h F9FFFh 7D000h 7CFFFh F8000h F7FFFh 7C000h 7BFFFh F0000h 78000h 16K BOOT BLOCK 78000h 77FFFh F0000h EFFFFh 70000h 6FFFFh E0000h DFFFFh 68000h 67FFFh D0000h CFFFFh 60000h 5FFFFh C0000h BFFFFh 58000h 57FFFh B0000h AFFFFh 50000h 4FFFFh A0000h 9FFFFh 48000h 47FFFh 90000h 8FFFFh 40000h 3FFFFh 80000h 7FFFFh 38000h 37FFFh 70000h 6FFFFh 30000h 2FFFFh 60000h 5FFFFh 28000h 27FFFh 50000h 4FFFFh 20000h 1FFFFh 40000h 3FFFFh 18000h 17FFFh 30000h 2FFFFh 10000h 0FFFFh 20000h 1FFFFh 08000h 07FFFh 10000h 0FFFFh 00000h 00000h 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 8K PARAMETER BLOCK 8K PARAMETER BLOCK 32K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK AI01725B 4/36 M39832 Figure 3B. Bottom Boot Block Memory Map and Block Address Table BOTTOM BOOT BLOCK Word-Wide Byte-Wide 7FFFFh FFFFFh 78000h 77FFFh F0000h EFFFFh 70000h 6FFFFh E0000h DFFFFh 68000h 67FFFh D0000h CFFFFh 60000h 5FFFFh C0000h BFFFFh 58000h 57FFFh B0000h AFFFFh 50000h 4FFFFh A0000h 9FFFFh 48000h 47FFFh 90000h 8FFFFh 40000h 3FFFFh 80000h 7FFFFh 38000h 37FFFh 70000h 6FFFFh 30000h 2FFFFh 60000h 5FFFFh 28000h 27FFFh 50000h 4FFFFh 20000h 1FFFFh 40000h 3FFFFh 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 64K MAIN BLOCK 18000h 17FFFh 30000h 2FFFFh 10000h 0FFFFh 20000h 1FFFFh 08000h 07FFFh 10000h 0FFFFh 00000h 00000h 64K MAIN BLOCK 64K MAIN BLOCK Byte-Wide Word-Wide 0FFFFh 07FFFh 08000h 07FFFh 04000h 03FFFh 06000h 05FFFh 03000h 02FFFh 04000h 03FFFh 02000h 01FFFh 00000h 00000h 32K MAIN BLOCK 8K PARAMETER BLOCK 8K PARAMETER BLOCK 16K BOOT BLOCK AI01731B 5/36 M39832 Table 3A. M39832-T Block Address Table Address Range (x8) Address Range (x16) A18 A17 A16 A15 A14 A13 A12 00000h-0FFFFh 00000h-07FFFh 0 0 0 0 X X X 10000h-1FFFFh 08000h-0FFFFh 0 0 0 1 X X X 20000h-2FFFFh 10000h-17FFFh 0 0 1 0 X X X 30000h-3FFFFh 18000h-1FFFFh 0 0 1 1 X X X 40000h-4FFFFh 20000h-27FFFh 0 1 0 0 X X X 50000h-5FFFFh 28000h-2FFFFh 0 1 0 1 X X X 60000h-6FFFFh 30000h-37FFFh 0 1 1 0 X X X 70000h-7FFFFh 38000h-3FFFFh 0 1 1 1 X X X 80000h-8FFFFh 40000h-47FFFh 1 0 0 0 X X X 90000h-9FFFFh 48000h-4FFFFh 1 0 0 1 X X X A0000h-AFFFFh 50000h-57FFFh 1 0 1 0 X X X B0000h-BFFFFh 58000h-5FFFFh 1 1 1 1 X X X C0000h-CFFFFh 60000h-67FFFh 1 1 0 0 X X X D0000h-DFFFFh 68000h-6FFFFh 1 1 0 1 X X X E0000h-EFFFFh 70000h-77FFFh 1 1 1 0 X X X F0000h-F7FFFh 78000h-7BFFFh 1 1 1 1 0 X X F8000h-F9FFFh 7C000h-7CFFFh 1 1 1 1 1 0 0 FA000h-FBFFFh 7D000h-7DFFFh 1 1 1 1 1 0 1 FC000h-FFFFFh 7E000h-7FFFFh 1 1 1 1 1 1 X 6/36 M39832 Table 3B. M39832-B Block Address Table Address Range (x8) Address Range (x16) A18 A17 A16 A15 A14 A13 A12 00000h-03FFFh 00000h-01FFFh 0 0 0 0 0 0 X 04000h-05FFFh 02000h-02FFFh 0 0 0 0 0 1 0 06000h-07FFFh 03000h-03FFFh 0 0 0 0 0 1 1 08000h-0FFFFh 04000h-07FFFh 0 0 0 0 1 X X 10000h-1FFFFh 08000h-0FFFFh 0 0 0 1 X X X 20000h-2FFFFh 10000h-17FFFh 0 0 1 0 X X X 30000h-3FFFFh 18000h-1FFFFh 0 0 1 1 X X X 40000h-4FFFFh 20000h-27FFFh 0 1 0 0 X X X 50000h-5FFFFh 28000h-2FFFFh 0 1 0 1 X X X 60000h-6FFFFh 30000h-37FFFh 0 1 1 0 X X X 70000h-7FFFFh 38000h-3FFFFh 0 1 1 1 X X X 80000h-8FFFFh 40000h-47FFFh 1 0 0 0 X X X 90000h-9FFFFh 48000h-4FFFFh 1 0 0 1 X X X A0000h-AFFFFh 50000h-57FFFh 1 0 1 0 X X X B0000h-BFFFFh 58000h-5FFFFh 1 0 1 1 X X X C0000h-CFFFFh 60000h-67FFFh 1 1 0 0 X X X D0000h-DFFFFh 68000h-6FFFFh 1 1 0 1 X X X E0000h-EFFFFh 70000h-77FFFh 1 1 1 0 X X X F0000h-FfFFFh 78000h-7FFFFh 1 1 1 1 X X X 7/36 M39832 Table 4. Basic Operations EF EE G W Operation VIL VIH VIL VIH Read in Flash Array VIH VIL VIL VIH Read in EEPROM Array VIL VIH VIH VIL Write in Flash Array VIH VIL VIH VIL Write in EEPROM Array VIL VIH VIH VIH Output Disable, DQn = Hi-Z VIH VIL VIH VIH Output Disable, DQn = Hi-Z VIH VIH X X Standby, DQn = Hi-Z Note: X = VIL or VIH. Write Enable (W). Addresses are latched on the falling edge of W, and Data Inputs are latched on the rising edge of W. EEPROM Ready/Busy (ERB). The EEPROM Ready/Busy pin outputs the status of the device when the EEPROM memory array is under the write condition – ERB = ’0’: internal writing is in process, – ERB = ’1’: no internal writing in in process. This status pin can be used when reading (or fetching opcodes) in the Flash memory array. The EEPROM Ready/Busy output uses an open drain transistor, allowing therefore the use of the M39832 in multi-memory applications with all Ready/Busy outputs connected to a single Ready/Busy line (OR-wired with an external pull-up resistor). Flash Ready/Busy (FRB). Flash Ready/Busy is an open-drain output and gives the internal state of Flash array. When FRB is Low, the Flash array is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. When FRB is High, the Flash array is ready for any Read, Program or Erase operation. The FRB will also be High when the Flash array is put in Erase Suspend or Standby modes. Reset/Block Temporary Unprotect Input (RP). The RP Input provides hardware reset of the Flash array and temporary unprotection of the protected Flash block(s). Reset of the Flash array is acheived by pulling RP to VIL for at least tPLPX. When the reset pulse is given while the Flash array is in Read or Standby modes, it will be available for new operations in tPHEL after the rising edge of RP. If the Flash array is in Erase, Erase Suspend or Program modes the reset will take tPLYH during 8/36 which the FRB signal will be held at VIL. The end of the Flash array reset will be indicated by the rising edge of FRB. A hardware reset during an Erase or Program operation will corrupt the data being programmed or the block(s) being erased. See Table 14 and Figure 9. Temporary block unprotection is made by holding RP at VID. In this conditio n, previously protected blocks can be programmed or erased. The transition of RP from VIH to VID must be slower than tPHPHH. See Table 15 and Figure 9. When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected. OPERATIONS An operation is defined as the basic decoding of the logic level applied to the control input pins (EF, EE, G, W) and the specified voltages applied on the relevant address pins. These operations are detailed in Table 3. Read. Both Chip Enable and Output Enable (that is EF and G or EE and G) must be low in order to read the output of the memory. Read operations are used to output the contents from the Flash or EEPROM array, the Manufacturer identifier, the Flash Block protection Status, the Flash Identifier, the EEPROM identifier or the OTP row content. Notes: – The Chip Enable input mainly provides power control and should be used for device selection. The Output Enable input should be used to gate data onto the output in combination with active EF or EE input signals. – The data read depends on the previous instruction entered into the memory. M39832 Table 5A. Flash Instructions (EF=0, EE=1) Mne. Instr. 1st Cyc. Cyc. 1+ Addr. (3,7) X Data Read/Reset RD (2,4) Memory Array Addr. 3+ Auto Select 3+ 5555h AAAAh Word 5555h 2AAAh 5555h AAh 55h F0h Byte AAAAh 5555h AAAAh Word 5555h 2AAAh 5555h AAh 55h 90h Byte AAAAh 5555h AAAAh Program Word 5555h 2AAAh 5555h AAh 55h A0h Byte AAAAh 5555h AAAAh AAAAh 5555h Word 5555h 2AAAh 5555h 5555h 2AAAh AAh 55h 80h AAh 55h 30h Byte AAAAh 5555h AAAAh AAAAh 5555h AAAAh Word 5555h 2AAAh 5555h 5555h 2AAAh 5555h AAh 55h 80h AAh 55h 10h (3,7) Program 4 Data Addr. BE Block Erase 6 Flash Array Erase Addr. 6 ES (10) ER Erase Suspend 1 Erase Resume 1 Read Electronic Signature or Block Protection Status until a new write cycle is initiated. See Note 5 and 6. Read Data Polling or Address Toggle Bit until Program completes. Program Data Block Address (3,7) Data Addr. (3,7) Data Addr. (3,7) Data 7th Cyc. Read Memory Array until a new write cycle is initiated. (3,7) Data FAE 6th Cyc. AAAAh Data PG 5th Cyc. Byte (3,7) Addr. 4th Cyc. Read Memory Array until a new write cycle is initiated. (3,7) Addr. AS 3rd Cyc. F0h Data (4) 2nd Cyc. X B0h X 30h Additiona l Block (8) 30h Note 9 Read until Toggle stops, then read all the data needed from any Block(s) not being erased then Resume Erase. Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time Notes: 1. Commands not interpreted in this table will default to read array mode. 2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new operation (see Table 14 and Figure 9). 3. X = Don’t Care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles. 5. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Flash code. 6. Block Protection Address: A0, at VIL, A1 at VIH and A15-A18 within the Block will output the Block Protection status. 7. For Coded cycles address inputs A11-A18 are don’t care. 8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended. 9. Read Data Polling, Toggle bits or FRB until Erase completes. 10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 9/36 M39832 Table 5B. EEPROM Instructions (EE=0, EF=1) Mne. WOTP Instr. (2) Write OTP Row 1st Cyc. Cyc. >3 Addr. Byte Word Data ROTP (2) Read OTP Row Return from OTP Read RT SSDP (4) SDP Enable >3 SSDP SDP Disable 2AAAh 3rd Cyc. 5555h 5555h 2AAAh 5555h AAh 55h B0h 2AAAh 5555h Byte 5555h Word 5555h 2AAAh 5555h Data AAh 55h 90h Addr. X (1) Data F0h Addr. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc. Addr 1 Addr 2 Addr 3 Addr 4 Byte 2 Byte 3 Byte 4 Addr 2 Addr 3 Addr 4 Byte 2 Byte 3 Byte 4 Byte 1 Addr 1 Byte 1 1 ≥3 Addr. Byte 5555h 2AAAh 5555h Word 5555h 2AAAh 5555h AAh 55h A0h Byte 5555h 2AAAh 5555h 5555h 2AAAh 5555h Word 5555h 2AAAh 5555h 5555h 2AAAh 5555h AAh 55h 80h AAh 55h 20h Data (5) 5555h 2nd Cyc. 6 Addr. Data Notes: 1. X = Don’t Care. 2. Once the WOTP has been initiated (first 3 Cycles), from 1 up to 64 bytes can be written in one single write cycle (See Write OTP chapter in following pages). 3. Once the ROTP has been initiated (first 3 Cycles), from 1 up to 64 bytes of the OTP can be read (See Read OTP chapter in following pages). The RT (Return) instruction MUST be sent to the device to exit ROTP mode. 4. Once SDP is set (SSDP instruction sent once), it is necessary to send SSDP prior to any byte or page to be written in the EEPROM array (See Figure 4 and EEPROM array Software Data Protection chapter in following pages). 5. See Figure 5 and EEPROM array Software Data Protection chapter in following pages. 10/36 M39832 Table 6. User Bus Operations (1) Operation Block Protection(2,4) EE EF G W RP BYTE A0 A1 A6 A9 A12 A15 DQ15 A–1 DQ8DQ14 DQ0-DQ7 VIH VIL VID VIL Pulse VIH X X X X VID X X X X X Blocks VIH VID VID Unprotection(4) VIL Pulse VIH X X X X VID VIH VIH X X X Block Protection Verify(2,4) VIH VIL VIL VIH VIH X VIL VIH VIL VID A12 A15 X X Block Protect Status (3) Block Unprotection Verify(2,4) VIH VIL VIL VIH VIH X VIL VIH VIH VID A12 A15 X X Block Protect Status (3) Block Temporary Unprotection VIH X X VID X X X X X X VIH VIL VIH VIL A0 A1 VIL VID X X A–1 X 64 Bytes User Defined VIH VIL VIH VIH A0 A1 VIL VID X X X X 64 Bytes User Defined VIL VIH VIH VIL A0 A1 VIL VID X X A–1 X 64 Bytes User Defined VIL VIH VIH VIH A0 A1 VIL VID X X X X 64 Bytes User Defined Write the EEPROM Identifier (5) Read the EEPROM Identifier (5) Notes: 1. 2. 3. 4. 5. X X X X X VIL VIH VIL VIH X = VIL or VIH Block Address must be given on A12-A18 bits. See Table 8. Operation performed on programming equipment. The 65 Bytes User defined EEPROM Identifier are accessed on DQ0-DQ7 with A0 to A5 when BYTE = 1 (x16) or with A–1 to A4 when BYTE = 0 (x8) Table 7. Read Electronic Signature (following AS instruction or with A9 = VID) Org. Wordwide Code A1 Other Addresses DQ15 A–1 DQ8DQ14 DQ0DQ7 VIH VIL VIL Don’t Care 0 00h 20h VIL VIH VIH VIH VIL Don’t Care 0 00h D7h VIH VIL VIL VIH VIH VIH VIL Don’t Care 0 00h 5Bh VIH VIL VIL VIH VIL VIL VIL Don’t Care Don’t Care Hi-Z 20h M39832-T VIH VIL VIL VIH VIL VIH VIL Don’t Care Don’t Care Hi-Z D7h M39832-B VIH VIL VIL VIH VIL VIH VIL Don’t Care Don’t Care Hi-Z 5Bh Device EE EF G VIH VIL VIL VIH M39832-T VIH VIL M39832-B Manufacturer Flash Manufacturer Bytewide W BYTE A0 Flash 11/36 M39832 Table 8. Read Block Protection with AS Instruction (EF = 0, EE = 1) E G W A0 A1 A12-A18 Other Addresses DQ0-DQ7 Protected Block VIL VIL VIH VIL VIH Block Address Don’t Care 01h Unprotected Block VIL VIL VIH VIL VIH Block Address Don’t Care 00h Code Table 9. Status Bit DQ 7 Name Data Polling Logic Level ’1’ Erase Complete or erase block in Erase Suspend ’0’ Erase On-going DQ Program Complete or data of non erase block during Erase Suspend DQ Program On-going ’-1-0-1-0-1-0-1-’ 6 Toggle Bit DQ ’-1-1-1-1-1-1-1-’ 5 4 3 Error Bit Erase or Program On-going Program Complete Erase Complete or Erase Suspend on currently addressed block Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. Successive reads output complementary data on DQ6 while Programming or Erase operations are on-going. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. ’1’ Program or Erase Error ’0’ Program or Erase On-going ’1’ Erase Timeout Period Expired P/E.C. Erase operation has started. Only possible command entry is Erase Suspend (ES). ’0’ Erase Timeout Period On-going An additional block to be erased in parallel can be entered to the P/E.C. This bit is set to ’1’ in the case of Programming or Erase failure. Reserved Erase Time Bit ’-1-0-1-0-1-0-1-’ 2 Definition Toggle Bit 1 DQ 1 Reserved 0 Reserved Chip Erase, Erase or Erase Suspend on the currently addressed block. Erase Error due to the currently addressed block (when DQ5 = ’1’). Indicates the erase status and allows to identify the erased block Program on-going, Erase on-going on another block or Erase Complete Erase Suspend read on non Erase Suspend block Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. 12/36 M39832 Figure 4. EEPROM SDP Enable Flowcharts SDP Set Page Write Instruction SDP not Set WRITE AAh in Address 5555h WRITE AAh in Address 5555h WRITE 55h in Address 2AAAh WRITE 55h in Address 2AAAh WRITE A0h in Address 5555h Page Write Instruction WRITE A0h in Address 5555h WRITE is enabled SDP is set SDP ENABLE ALGORITHM WRITE Data to be Written in any Address Write in Memory Write Data + SDP Set after tWC AI01698B Write. A Write operation can be used for two goals: – either write data in the EEPROM memory array – or enter a sequence of bytes or word composing an instruction. The reader should note that Programming a Flash byte or word is an instruction (see Instructions paragraph). Writing data requires: – the Chip Enable (either EE or EF) to be Low – the Write Enable (W) to be Low with Output Enable (G) High. Addresses in Flash array (or EEPROM array) are latched on the falling edge of W or EF (EE) whichever occurs last; the data to be written in Flash array (EEPROM array) is latched on the rising edge of W or EF (EE) whichever occurs first. Specific Read and Write Operations. Device specific data is accessed through operations decoding the VID level applied on A9 and the logic levels applied on address inputs (A0, A1, A6). These specific operations are: – Read the Manufacturer identifier – Read the Flash identifier – Define and Read the Flash Block protection status – Read the EEPROM identifier – Write the EEPROM identifier Note: The OTP row (64 bytes) is accessed with a specific software sequence detailed in the paragraph "Write in OTP row". Instructions An instruction is defined as a sequence of specific Write operations. Each received byte or word is sequentially decoded (and not executed as standard Write operations) and the instruction is executed when the correct number of bytes or word are properly received and the time between two consecutive bytes or words is shorter than the time-out value. The sequencing of any instruction must be followed exactly, any invalid combination of instruction bytes or word or time-out between two consecutive bytes or word will reset the device logic into a Read memory state (when addressing the Flash array) or directly decoded as a single operation when addressing the EEPROM array. For efficient decoding of the instruction, the two first bytes or words of an instruction are the coded cycles and are followed by a command confirmation byte or word. 13/36 M39832 Figure 5. EEPROM SDP disable Flowchart Figure 6. EEPROM and Flash Data Polling Flowchart START WRITE AAh in Address 5555h READ DQ5 & DQ7 at VALID ADDRESS WRITE 55h in Address 2AAAh Page Write Instruction DQ7 = DATA WRITE 80h in Address 5555h YES NO WRITE AAh in Address 5555h NO WRITE 55h in Address 2AAAh DQ5 =1 YES READ DQ7 WRITE 20h in Address 5555h DQ7 = DATA Unprotected State after tWC (Write Cycle time) YES NO FAIL PASS AI01699B AI01369 READ Read operations and instructions can be used to: – read the contents of the Memory Array (Flash and EEPROM) – read the status bits and identifiers. Read data (Flash and EEPROM) Both Chip Enable EF (or EE) and Output Enable (G) must be low in order to read the data from the memory. Read the Manufacturer Identifier The manufacturer’s identifier can be read with two methods: a Read operation or a Read instruction. Read Operation. The manufacturer’s identifier can be read with a Read operation with specific logic 14/36 levels applied on A0, A1, A6 and the VID level on A9 (See Table 7). Read Instruction. The manufacturer’s identifier can also be read with a single read operation immediatly following the AS instruction (See Table 5A and Table 7). Read the Flash Identifier The Flash identifier can be read with two methods: a Read operation or a Read instruction. Read Operation. The Flash identifier can be read with a single Read operation with specific logic levels applied on A0, A1, A6 and the VID level on A9 (See Table 7). Read Instruction. The Flash identifier can also be read with a single read operation immediatly following the AS instruction (See Table 5A and Table 7). M39832 Read the EEPROM Identifier The EEPROM identifier (64 bytes, user defined) can be read with a single Read operation with A6 = ’0’ and A9 = VID (See Table 6). When accessing the 64 Bytes of EEPROM Identifier, the only LSB addresses are decoded. The LSB addresses are A0 to A5 when BYTE = ’1’ (x16) and A–1 to A4 when BYTE = ’0’ (x8). Each Byte of the EEPROM identifier can be individually accessed in read or write mode. Read the OTP Row The OTP row is mapped in the EEPROM array (EE = ’0’, EF = ’1’). Read of the OTP row (64 bytes) is by an instruction (ROTP) composed of three specific Write operations of data bytes at three specific memory locations (each location in a different page) before reading the OTP row content (See Table 5B). When accessing the OTP row, only the LSB addresses are decoded and A6 must be ’0’. The LSB addresses are A0 to A5 when BYTE = ’1’ (x16) and A–1 to A4 when BYTE = ’0’ (x8). Each Read of the OTP row has to be followed by the (RT) Return instruction (See Table 5B). Read the Flash Block Protection Status Reading the Flash block protection status is by a read operation immediatly following the AS instruction (See Table 5A and Table 8). A12-A18 define the Flash block whose protection has to be verified. This Read operation will output a 01h if the Flash block is protected and a 00h if the Flash block is not protected. The Flash block protection status can also be verified with a single Read operation (see chapter: Flash array specific features), with VID on A9 (See Table 6 and Table 8). Read the Status Bits The M39832 provides several Write operation status flags which may be used to minimize the application write (or erase or program) time. These signals are available on the I/O port bits when programming (or erasing) are in progress. It should be noted that the Ready/Busy pins also reflects the status of the EEPROM Write and the Flash Programming/Erasing. Data Polling flag, DQ7. When Erasing or Programming into the Flash block (or when Writing into the EEPROM block), bit DQ7 outputs the comple- ment of the bit being entered for Programming/Writing on DQ7. Once the Program instruction or the Write operation is performed, the true logic value is read on DQ7 (in a Read operation). Flash memory block specific features: – Data Polling is effective after the fourth W pulse (for programming) or after the sixth W pulse (for Erase). It must be performed at the address being programmed or at an address within the Flash sector being erased. – During an Erase instruction, DQ7 outputs a ’0’. After completion of the instruction, DQ7 will output the last bit programmed (that is a ’1’ after erasing). – if the byte to be programmed is in a protected Flash sector, the instruction is ignored. – If all the Flash sectors to be erased are protected, DQ7 will be set to ’0’ for about 100µs, and then return to the previous addressed byte. No erasure will be performed. – if all sectors are protected, a Bulk Erase instruction is ignored. Toggle flag, DQ6. The M39832 also offers another way for determining when the EEPROM write or the Flash memory Program instruction is completed. During the internal Write operation, the DQ6 will toggle from ’0’ to ’1’ and ’1’ to ’0’ on subsequent attempts to read any byte of the memory, when either G , EE or EF is low. When the internal cycle is completed the toggling will stop and the data read on DQ0-DQ7 is the addressed memory byte. The device is now accessible for a new Read or Write operation. The operation is completed when two successive reads yield the same output data. Flash memory block specific features: a. The Toggle bit is effective after the fourth W pulse (for programming) or after the sixth W pulse (for Erase). b. If the byte to be programmed belongs to a protected Flash sector, the instruction is ignored and: – if all the Flash sectors selected for erasure are protected, DQ6 will toggle to ’0’ for about 100µs, and then return to the previous addressed byte. – if all sectors are protected, the Bulk Erase instruction is ignored. 15/36 M39832 Figure 7A. Data Toggle Flowchart Figure 7B. Flash ata Toggle Flowchart START START READ DQ2, DQ5 & DQ6 READ DQ5 & DQ6 DQ6 = TOGGLE YES NO YES NO DQ5 =1 YES READ DQ2, DQ6 NO DQ2, DQ6 = TOGGLE YES FAIL DQ5 =1 YES READ DQ6 DQ6 = TOGGLE NO DQ2, DQ6 = TOGGLE NO NO YES PASS FAIL PASS AI01370 AI01873 Toggle Bit, DQ2 (Flash array only). This toggle bit, together with DQ6, can be used to determine the device status during the Erase operations. It can also be used to identify the block being erased. During Erase or Erase Suspend a read from a block being erased will cause DQ2 to toggle. A read from a block not being erased will set DQ2 to ’1’ during erase and to DQ2 during Erase Suspend. During Flash Array Erase, a read operation will cause DQ2 to toggle as all blocks are being erased. DQ2 will be set to ’1’ during program operation and when erase is complete. After erase completion and if the error bit DQ5 is set to ’1’, DQ2 will toggle if the faulty block is addressed. Error flag, DQ5 (Flash block only). This bit is set to ’1’ by the internal logic when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. In case of an error in block erase or program, the block in which the error occured or to which the programmed data belongs, must be discarded. The 16/36 DQ5 failure condition will also appear if a user tries to program a ’1’ to a location that is previously programmed to ’0’. Other Blocks may still be used. The error bit resets after a Read/Reset (RD) instruction. In case of success of Program or Erase, the error bit will be set to ’0’ . when A0 is High with A1 Low. Erase Timer Bit, DQ3 (Flash array only). This bit is set to ’0’ by internal logic when the last block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, after 50ms to 90ms, DQ3 returns to ’1’. WRITE a BYTE (or a PAGE) in EEPROM It should be noticed that writing in the EEPROM array is an operation, it is not an instruction (as for Programming a byte in the Flash array). Write a Byte in EEPROM Array A write operation is initiated when Chip Enable EE is Low and Write Enable W is Low with Output M39832 Enable G High. Addresses are latched on the falling edge of W, EE whichever occurs last. Once initiated, the write operation is internally timed until completion, that is during a time tW. The status of the write operation can be found by reading the Data Polling and Toggle bits (as detailed in the READ chapter) or the ERB output. This Ready/Busy output is driven low from the write of the byte being written until the completion of the internal Write sequence. Write a Page in EEPROM Array The Page write allows up to 64 bytes within the same EEPROM page to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A6-A14 when BYTE is high (x16) or A5-A13 when BYTE is low (x8) must be the same for all bytes. Once initiated, the Page write operation is internally timed until completion, that is during a time tWC. The status of the write operation can be seen by reading the Data Polling and Toggle bits (as detailed in the READ chapter) or the ERB output. This Ready/Busy output is driven low from the write of the first byte to be written until the completion of the internal Write sequence. A Page write is composed of successive Write operations which must be sequenced within a time period (between two consecutive Write operations) that is smaller than the tWLWL value. If this period of time exceeds the tWLWL value, the internal programming cycle will start. EEPROM Array Software Data Protection A protection instruction allows the user to inhibit all write modes to the EEPROM array: the Software Data Protection (referenced as SDP in the following). The SDP feature is useful for protecting the EEPROM memory from inadvertent write cycles that may occur during uncontrolled bus conditions. The M39832 is shipped as standard in the unprotected state meaning that the EEPROM memory contents can be changed by the user. After the SDP enable instruction, the device enters the Protect Mode where no further write operations have any effect on the EEPROM memory contents. The device remains in this mode until a valid SDP disable instruction is received whereby the device reverts to the unprotected state. To enable the Software Data Protection, the device has to be written (with a Page Write) with three specific data bytes at three specific memory locations (each location in a different page) as shown in Figure 4 and Table 5B. This sequence provides an unlock key to enable the write action, and, at the same time, SDP continues to be set. Any further Write in EEPROM when the SDP is set will use this same sequence of three specific data bytes at three specific memory locations followed by the bytes to write. The first SDP enable sequence can be directly followed by the bytes to written. Similarly, to disable the Software Data Protection the user has to write specific data bytes into six different locations with a Page Write addressing different bytes in different pages, as shown in Figure 5 and Table 5B. The Software Data Protection state is non-volatile and is not changed by power on/off sequences. The SDP enable/disable instructions set/reset an internal non-volatile bit and therefore will require a write time tWC, This Write operation can be monitored only on the Toggle bit (status bit DQ6) and the ERB pin. The Ready/Busy output is driven low from the first byte to be written (that is the first Write AAh, @5555h of the SDP set/reset sequence) until the completion of the internal Write sequence. Write OTP Row Writing (only one time) in the OTP row (64 bytes) is enabled by an instruction (WOTP). This instruction is composed of three specific Write operations of data bytes at three specific memory locations (each location in a different page) followed by the the data to store in the OTP row (refer to Table 5B). When accessing the OTP row, the only LSB addresses are decoded and A6 must be ’0’. The LSB addresses are A0 to A5 when BYTE = ’1’ (x16) and A–1 to A4 when BYTE = ’0’ (x8). Once at least one Byte of the OTP row has been written (even with FFh), the whole row becomes Read only. Write the EEPROM Block Identifier The EEPROM block identifier (64 Bytes) can be written with a single Write operation with A6 = ’0’ and the VID level on A9 (see Table 6). When accessing the 64 Bytes of EEPROM Identifier, the only LSB addresses are decoded. The LSB addresses are A0 to A5 when BYTE = ’1’ (x16) and A-1 to A4 when BYTE = ’0’ (x8). Each Byte of the EEPROM identifier can be individually accessed in read or write mode. PROGRAM in the Flash ARRAY It should be noted that writing data into the EEPROM array and the Flash array is not performed in a similar way: the Flash memory requires an instruction (see Instruction chapter) for Erasing and another instruction for Programming one (or more) byte(s) or word(s), the EEPROM memory is directly written with a simple operation (see Operation chapter). 17/36 M39832 Program (PG) Instruction. This instruction uses four write cycles. Both for Byte-wide configuration and for Word-wide configuration. The Program command A0h is written to address AAAAh in the Byte-wide configuration or to address 5555h in the Word-wide configuration on the third cycle after two Coded cycles. A fourth write operation latches the Address on the falling edge of W or EF and the Data to be written on the rising edge and starts the internal operation. Read operations output the Status Register bits after the programming has started. Memory programming is made only by writing ’0’ in place of ’1’. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend. In this case, DQ2 will toggle at the address being programmed. Auto Select (AS) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 90h to address AAAAh in the Byte-wide configuration or address 5555h in the Word-wide configuration for command set-up. A subsequent read will output the manufacturer code and the device code or the block protection status depending on the levels of A0 and A1. The manufacturer code is output when the addresses lines A0 and A1 are Low, the Flash code for Top Boot or Bottom Boot is output when A0 is High with A1 Low. The AS instruction allows access to the block protection status. After giving the AS instruction, A0 is set to VIL with A1 at VIH, while A12-A18 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. The ERASE in the Flash ARRAY Flash Array Erase (FAE) Instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address AAAAh in the Byte-wide configuration or the address 5555h in the Word-wide configuration on the third cycle after the two Coded cycles. The Flash Array Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as it will be done 18/36 automatically before erasing it to FFh. Read operations after the sixth rising edge of W or EF output the Status Register bits. During the execution of the erase, Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle bits DQ2 and DQ6 toggle during erase operation and stop when erase is completed. After completion, the Status Bit DQ5 returns ’1’ if there has been an Erase Failure. Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address AAAh in the Byte-wide configuration or address 5555h in the Word-wide configuration on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description). Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the Block(s) are being erased. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as it will be done automatically before erasing it to FFh. Read operations after the sixth rising edge of W or EF output the Status Register bits. During the execution of the erase , the memory accepts only the Erase Suspend ES and Read/Reset RD instructions. Data Polling bit DQ7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. The Toggle bit DQ2 and DQ6 toggle during the erase operation. They stop when erase is completed. After completion the Status bit DQ5 returns ’1’ if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the memory. M39832 Figure 8. Block Protection Flowchart START BLOCK ADDRESS on A12 to A18 EE = VIH n=0 G, A9 = VID, EF = VIL Wait 4µs W = VIL Wait 100µs W = VIH G = VIH Wait 4µs READ DQ0 at PROTECTION ADDRESS: A0, A6 = VIL, A1 = VIH and A12 to A18 DEFINING BLOCK DQ0 =1 NO YES A9 = VIH ++n = 25 NO PASS YES A9 = VIH FAIL AI00853 19/36 M39832 Figure 9. Block Unprotecting Flowchart START EE = EF = VIH n=0 A6, A12, A15 = VIH G, A9 = VIH Wait 4µs EF, G, A9 = VID Wait 4µs W = VIL Wait 10ms W = VIH EF, G = VIH Wait 4µs READ at UNPROTECTION ADDRESS: A1, A6 = VIH, A0 = VIL and A12 to A18 DEFINING BLOCK (see Note 1) NO NO ++n = 1000 YES FAIL DATA = 00h INCREMENT BLOCK YES LAST BLOCK NO YES PASS AI00850 Note: 1. A6 is kept at VIH during unprotection algorithm in order to secure best unprotection verification. During all other protection status reads, A6 must be kept at VIL. 20/36 M39832 Table 10. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Figure 11. Output AC Testing Load Circuit ≤ 10ns VCC 0.V to VCC Input and Output Timing Ref. Voltages IOH VCC / 2 1N914 DEVICE UNDER TEST Figure 10. AC Testing Input Output Waveform 1N914 CL = 30pF IOL VCC VCC / 2 0V CL includes JIG capacitance VOUT = 1.5V when the DEVICE UNDER TEST is in the Hi-Z output state. AI00939 AI00854 Table 11. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol CIN COUT Parameter Test Condition Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Input Capacitance Output Capacitance Min Note: 1. Sampled only, not 100% tested. Erase Suspend (ES) Instruction. The Block Erase operation may be suspended by this instruction which consists of writing the command B0h without any specific address. No Coded cycles are required. It permits reading of data from another block and programming in another block while an erase operation is in progress. Erase suspend is accepted only during the Block Erase instruction execution. Writing this command during Erase timeout will, in addition to suspending the erase, terminate the timeout. The Toggle bit DQ6 stops toggling when erase is suspended. The Toggle bits will stop toggling between 0.1ms and 15ms after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at ’1’. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instructions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in both DQ2 and DQ6 toggling when the data is being programmed. A Read/Reset command will definitively abort erasure and result in invalid data in the blocks being erased. Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any Coded cycles. FLASH ARRAY SPECIFIC FEATURES Block Protection (See Figure 8). Each block can be separately protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or erase operations. This mode is activated when both A9 and G are raised to VID and an address in the block is applied on A12-A18. Block protection is initiated on the edge of W falling to VIL. Then after a delay of 100ms, the edge of W rising to VIH ends the protection operations. Block protection verify is achieved by bringing G, EF, A0 and A6 to VIL and A1 to VIH, while W is at VIH and A9 at VID. 21/36 M39832 Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A12-A18 is protected. Any attempt to program or erase a protected block will be ignored by the device. Remarks: – The Verify operation is a read with a simulated worst case conditions. This allows a guarantee of the retention of the Protection status – During the application life, the block protection status can be accessed with a regular Read instruction without applying a "high voltage" VID on A9. This instruction is detailed in Table 5 and Table 8. Blocks Unprotection (See Figure 9). All protected blocks can be unprotected simultaneously on programming equipment to allow updating of bit contents. All blocks must first be protected before the unprotection operation. Block unprotection is activated when A9, G and E are at VID and A12, A15 at VIH. Unprotection is initiated by the edge of W falling to VIL. After a delay of 10ms, the unprotection operation will end. Unprotection verify is achieved by bringing G and E to VIL while A0 is at VIL, A6 and A1 are at VIH and A9 remains at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs A12-A18 has been succesfully unprotected. Each block must be separately verified by giving its address in order to ensure that it has been unprotected. Remarks: – The Verify operation is a read with a simulated worst case conditions. This allows a guarantee of the retention of the Protection status – During the application life, the Block protection status can be accessed with a regular Read instruction without "high voltage" VID on A9. This instruction is detailed in Table 5 and Table 8. Block Temporary Unprotection. Any previously protected block can be temporarily unprotected in order to change stored data. The temporary unprotection mode is activated by bringing RP to VID. During the temporary unprotection mode the previously protected blocks are unprotected. A block can be selected and data can be modified by executing the Erase or Program instruction with the RP signal held at VID. When RP is returned to VIH, all the previously protected blocks are again protected. 22/36 Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded cycles. Subsequent read operations will read the memory array addressed and output the data read. A wait state of 10ms is necessary after Read/Reset prior to any valid read if the memory was in an Erase mode when the RD instruction is given. GLOSSARY Array: EEPROM array (256 Kbit) or Flash array (8 Mbit) Block: part of the Flash array (See Figure 3A and 3B). Page: 64 bytes of EEPROM Write and Program: Writing (into the EEPROM array) and programming (the Flash array is not performed in a similar way: – the Flash memory requires an instruction (see Instruction chapter) for Erasing and another instruction for Programming one (or more) byte(s) or word(s) – the EEPROM memory is directly written with a simple operation (see Operation chapter). SDP: Software Data Protection. Used for protecting the EEPROM array against false Write operations (as in noisy environments). POWER SUPPLY and CURRENT CONSUMPTION Power Up. The M39832 internal logic is reset upon a power-up condition to Read memory status. Any Write operation in EEPROM is inhibited during the first 5 ms following the power-up. Either EF, EE or W must be tied to VIH during Power-up for the maximum security of the data contents and to remove the possibility of a byte being written on the first rising edge of EF, EE or W. Any write cycle initiation is locked when Vcc is below VLKO. Supply Rails. Normal precautions must be taken for supply voltage decoupling, each device in a system should have the VCC rail decoupled with a 0.1µF capacitor close to the VCC and VSS pins. The printed circuit board trace width should be sufficient to carry the VCC program and erase currents required. M39832 Table 12. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 2.7 to 3.6V) Symbol Parameter Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA Supply Current (Read Flash) EE = VIH, EF = VIL, G = VIH, f = 6MHz 10 mA ICC2 Supply Current (Read EEPROM) EE = VIL, EF = VIH, G = VIH, f = 6MHz 10 mA ICC3 Supply Current (Standby) EF = EE = VCC ± 0.2V 100 µA ICC4 Supply Current (Flash Block Program or Erase) Byte program, Sector or Chip Erase in progress 20 mA ICC5 Supply Current (EEPROM Write) During tWC 20 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 VCC VCC + 0.3 V VOL Output Low Voltage IOL = 1.8mA 0.45 V VOH Output High Voltage IOH = –100µA VID A9 High Voltage IID VID Current ILI Input Leakage Current ILO Output Leakage Current ICC1 (1) VLKO VCC Minimum for Write, Erase and Program Test Condition Min VCC –0.4 11.5 A9 = VID 1.9 V 12.5 V 100 µA 2.3 V Note: 1. When reading the Flash block when an EEPROM byte(s) is under a write cycle, the supply current is ICC1 + ICC5. 23/36 24/36 Note: Write Enable (W) = High DQ0-DQ7 G EF (EE) EE (EF) A0-A18 tEHFL ADDRESS VALID AND CHIP ENABLE tAVQV tGLQV OUTPUT ENABLE tGLQX tELQX tELQV VALID tAVAV DATA VALID tEHFL VALID tGHQX tGHQZ tEHQZ tEHQX tAXQX AI01952 M39832 Figure 12. Read Mode AC Waveforms M39832 Table 13. Read AC Characteristics (TA = 0 to 70°C or –20 to 85°C; VCC = 3.3V ± 0.3V) M39832 Symbol Alt Parameter Test Condition -120 Min tAVAV tRC Address Valid to Next Address Valid (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL), G = VIL tAVQV tACC Address Valid to Output Valid (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL), G = VIL tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL tELQV (2) tCE Chip Enable Low to Output Valid G = VIL tGLQX (1) tOLZ Output Enable Low to Output Transition (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL) tGLQV (2) tOE Output Enable Low to Output Valid (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL) tEHQX tOH Chip Enable High to Output Transition G = VIL tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL tGHQX tOH Output Enable High to Output Transition (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL) tGHQZ (1) tDF Output Enable High to Output Hi-Z (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL) tAXQX tOH Address Transition to Output Transition (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL), G = VIL tEHFL tCED EE (EF) Active to EF (EE) Unit -150 Max 120 Min Max 150 120 0 ns 150 0 120 0 ns 150 0 55 0 0 0 ns ns 40 0 40 ns ns 55 40 ns ns ns 40 ns 0 0 ns 100 100 ns Notes: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of EE (or EF) without increasing tELQV. 25/36 M39832 Figure 13. Write AC Waveforms, W Controlled WRITE CYCLE A0-A18 VALID tWLAX tAVWL tWHEH E (1) tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH tWHDX VALID DQ0-DQ7 tWHRH RB tWHRL VCC tVCHEL AI01953 Notes: Address are latched on the falling edge of W, Data is latched on the rising edge of W. E is either EF when EE = VIH or EE when EF = VIH. 26/36 M39832 Figure 14. Write AC Waveforms, E Controlled WRITE CYCLE A0-A18 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL E tELEH (1) tEHEL tDVEH DQ0-DQ7 tEHDX VALID tWHRL RB VCC tVCHWL Notes: AI01954 Address are latched on the falling edge of E, Data is latched on the rising edge of E. E is either EF when EE = VIH or EE when EF = VIH. 27/36 M39832 Table 14. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V) M39832 Symbol Alt Parameter -120 Min tAVAV tWC Address Valid to Next Address Valid tCS tWLWH Unit -150 Max Min Max 120 150 ns Chip Enable Low to Write Enable Low 0 0 ns tWP Write Enable Low to Write Enable High 50 65 ns tDVWH tDS Input Valid to Write Enable High 50 65 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tCH Write Enable High to Chip Enable High 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 30 35 ns tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 50 65 ns Output Enable High to Write Enable Low 0 0 ns VCC High to Chip Enable Low 50 50 µs Write Enable High to Output Valid (Program) 15 15 µs Write Enable High to Output Valid (Sector Erase) 2.0 tELWL tWHEH (2) (2) tGHWL tVCHEL tWHQV1 tVCS (1) tWHQV2 (1) Time Out between 2 consecutive Section Erase tWHWL0 tWHGL tWHRL (3) tOEH Write Enable High to Output Enable Low tDB Write Enable High to Ready/Busy Output Low Notes: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV 2. Chip Enable means (EE, EF) = (VIL, VIH) or (EE, EF) = (VIH, VIL). 3. With a 3.3KΩ pull-up resistor. 28/36 30 2.0 80 0 30 sec 80 µs 0 150 ns 150 ns M39832 Table 15. Write AC Characteristics, EE or EF Controlled (TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V) M39832 Symbol Alt Parameter tWLWL tBLC Byte Load Cycle (EEPROM) tWHRH tWC Write Cycle Time (EEPROM) tAVAV Address Valid to Next Address Valid -120 Unit -150 Min Max Min Max 0.2 150 0.2 150 µs 10 ms 10 120 150 ns tWLEL tWS Write Enable Low to Memory Block Enable Low 0 0 ns tELEH tCP Memory Block Enable Low to Memory Block Enable High 50 65 ns tDVEH tDS Input Valid to Memory Block Enable High 50 65 ns tEHDX tDH Memory Block Enable High to Input Transition 0 0 ns tEHWH tWH Memory Block Enable High to Write Enable High 0 0 ns tEHEL tCPH Memory Block Enable High to Memory Block Enable Low 30 35 ns tAVEL tAS Address Valid to Memory Block Enable Low 0 0 ns tELAX tAH Memory Block Enable Low to Address Transition 50 65 ns Output Enable High to Memory Block Enable Low 0 0 ns VCC High to Write Enable Low 50 50 µs tEHQV1 (1) Memory Block Enable High to Output Valid (Program) 15 15 µs tEHQV2 (1) Memory Block Enable High to Output Valid (Sector Erase) 2.0 tGHEL tVCHWL tVCS tEHGL tOEH Memory Block Enable High to Output Enable Low tEHRL (2) tDB EEPROM Block Enable High to Ready/Busy Output Low 30 0 2.0 30 0 150 sec ns 150 ns Notes: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV. 2. With a 3.3KΩ pull-up resistor. 29/36 30/36 Notes: 1. 2. 3. 4. 5. LAST CYCLE OF PROGRAM OR ERASE DATA POLLING READ CYCLES tWHQ7V tEHQ7V tELQV tAVQV tQ7VQV IGNORE DQ7 DATA POLLING (LAST) CYCLE tGLQV BYTE ADDRESS (WITHIN SECTORS) All other timings are as a normal Read cycle. DQ7 and DQ0-DQ6 can transmit to valid at any point during the data output valid period. tWHQ7V is the Program or Erase time. During erasing operation Byte address must be within Sector being erased. E is either EF when EE = VIH or EE when EF = VIH. DQ0-DQ6 DQ7 W G E (5) A0-A18 VALID VALID DATA OUTPUT VALID AI01955 DATA VERIFY READ CYCLE M39832 Figure 15. Data Polling DQ7 AC Waveforms M39832 Table 16. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V) M39832 Symbol Parameter -120 Min tWHQ7V1 (2) Write Enable High to DQ7 Valid (Program, W Controlled) 10 tWHQ7V2 (2) Write Enable High to DQ7 Valid (Sector Erase, W Controlled) 1.5 tEHQ7V1 (2) Flash Block Enable High to DQ7 Valid (Program, EF Controlled) 10 tEHQ7V2 (2) Flash Block Enable High to DQ7 Valid (Sector Erase, EF Controlled) 1.5 tQ7VQV Q7 Valid to Output Valid (Data Polling) Unit -150 Max Min Max µs 10 30 1.5 30 µs 10 30 sec 1.5 50 30 sec 55 ns Notes: 1. All other timings are defined in Read AC Characteristics table. 2. tWHQ7V is the Program or Erase time. Table 17. Program, Erase Times and Program, Erase Endurance Cycles (Flash Block) (TA = 0 to 70°C; VCC = 2.7V to 3.6V) M39832 Parameter Unit Typ Typical after 100k W/E Cycles Flash array Erase (Preprogrammed) 5 5 sec Flash array Erase 12 12 sec Flash array Block Erase 2.4 sec Parameter Block Erase 2.3 sec Main Block (32Kb) Erase 2.7 sec Main Block (64Kb) Erase 3.3 Min Max 15 sec Chip Program (Byte) 8 8 sec Byte Program 10 10 µs Word Program 20 20 µs Program/Erase Cycles (per Block) 100,000 cycles 31/36 32/36 LAST CYCLE OF PROGRAM OF ERASE DATA TOGGLE READ CYCLE Notes: 1. All other timings are as a normal Read cycle. 2. E is either EF when EE = VIH or EE when EF = VIH. DQ0-DQ5, DQ7 DQ6 W G E (2) A0-A18 DATA TOGGLE READ CYCLE IGNORE STOP TOGGLE tWHQV tEHQV tAVQV READ CYCLE VALID VALID tGLQV tELQV VALID AI01956 M39832 Figure 16. Data Toggle DQ6 AC Waveforms M39832 Figure 17. EEPROM Page Write Mode AC Waveforms, W Controlled A0-A14 or A–1-A13 Addr 0 Addr 1 Addr 2 Addr n EE G tWHWL tWHRH tWLWL W tWLWH DQ0-DQ7 Byte 0 Byte 1 Byte 2 Byte n tWHRL ERB AI00856 33/36 M39832 ORDERING INFORMATION SCHEME Example: M39832 - B 15 W NE 6 T Array Matrix T Top Boot B Bottom Boot Speed 12 120ns 15 150ns Option T Operating Voltage W 2.7V to 3.6V Temp. Range Package NE TSOP48 12 x 20mm Tape & Reel Packing 1 0 to 70 °C 6 –40 to 85 °C Devices are shipped from the factory with the memory content set at all "1’s" (FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 34/36 M39832 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm mm Symb Typ inches Min Max A Typ Min 1.20 Max 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 11.90 12.10 0.469 0.476 - - - - L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 48 e 0.50 0.020 48 CP 0.10 0.004 A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a A1 α L Drawing is not to scale. 35/36 M39832 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 36/36