M29W641DH, M29W641DL M29W641DU 64 Mbit (4Mb x16, Uniform Block) 3V Supply Flash Memory PRODUCT PREVIEW FEATURES SUMMARY ■ SUPPLY VOLTAGE Figure 1. Packages – VCC = 2.7V to 3.6V Core Power Supply – VCCQ = 1.8V to 3.6V for Input/Output ■ – VPP =12 V for Fast Program (optional) ACCESS TIME: 70, 90, 100 and 120ns ■ PROGRAMMING TIME – 10 µs typical – Double Word Program option ■ 128 UNIFORM, 32-KWord MEMORY BLOCKS ■ PROGRAM/ERASE CONTROLLER TSOP48 (N) 12 x 20mm – Embedded Program and Erase algorithms ■ ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend ■ UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming ■ FBGA WRITE PROTECT OPTIONS – M29W641DH: WP Pin for Write Protection of Highest Address Block – M29W641DL: WP Pin for Write Protection of Lowest Address Block – M29W641DU: No Write Protection ■ TEMPORARY BLOCK UNPROTECTION MODE ■ COMMON FLASH INTERFACE ■ EXTENDED MEMORY BLOCK TFBGA63 (ZA) 7 x 11mm – Extra block used as security block or to store additional information ■ LOW POWER CONSUMPTION – Standby and Automatic Standby ■ ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Device Code M29W641D: 22C7h April 2003 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/42 M29W641DH, M29W641DL, M29W641DU TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. TFGBA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VPP (VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCCQ Supply Voltage (1.8V to 3.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/42 M29W641DH, M29W641DL, M29W641DU Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 14 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 25 Table 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 25 Figure 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Bottom view package outline 26 Table 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . 26 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 17. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3/42 M29W641DH, M29W641DL, M29W641DU APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 18. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 19. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 21. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 22. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 APPENDIX C. EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 24. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 APPENDIX D. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 25. Programmer Technique Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 16. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 18. In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4/42 M29W641DH, M29W641DL, M29W641DU SUMMARY DESCRIPTION The M29W641D is a 64 Mbit (4Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single, low voltage, 2.7V to 3.6V VCC supply for the circuitry and a 1.8V to 3.6V VCCQ supply for the Input/Output pins. An optional 12 V VPP power supply is provided to speed up customer programming. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The highest address block of the M29W641DH or the lowest address block of the M29W641DL can be protected from accidental programming or erasure using the WP pin (if WP = VIL). The M29W641DU does not feature the WP pin. Each block can be erased independently so it is possible to preserve valid data while old data is erased. The blocks can be protected to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The M29W641D has an extra block, the Extended Block, (of 32 KWords) that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. However the protection is not reversible, once protected the protection cannot be undone. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in a 48-pin TSOP package (M29W641DL and M29W641DH) or in a 63-ball TFBGA package (M29W641DU). All devices are delivered with all the bits erased (set to 1). Figure 2. Logic Diagram VCC VCCQ VPP 22 16 A0-A21 DQ0-DQ15 W E M29W641D G RB RP WP VSS AI06697b Table 1. Signal Names A0-A21 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8DQ15 Data Inputs/Outputs E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect (M29W641DH and M29W641DL only) RB Ready/Busy Output (M29W641DU only) WP Write Protect VCC Supply Voltage VCCQ Supply Voltage for Input/Output VPP Supply Voltage for Fast Program (optional) VSS Ground 5/42 M29W641DH, M29W641DL, M29W641DU Figure 3. TSOP Connections A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 12 13 24 48 M29W641D 37 36 25 AI06698 6/42 A16 VCCQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 M29W641DH, M29W641DL, M29W641DU Figure 4. TFGBA Connections (Top view through package) 1 2 A NC(1) NC(1) B NC(1) 3 4 5 6 7 8 NC(1) NC(1) NC(1) NC(1) C A3 A7 RB W A9 A13 D A4 A17 VPP RP A8 A12 E A2 A6 A18 A21 A10 A14 F A1 A5 A20 A19 A11 A15 G A0 DQ0 DQ2 DQ5 DQ7 A16 H E DQ8 DQ10 DQ12 DQ14 VCCQ J G DQ9 DQ11 VCC DQ13 DQ15 K VSS DQ1 DQ3 DQ4 DQ6 VSS L NC(1) NC(1) NC(1) NC(1) M NC(1) NC(1) NC(1) NC(1) AI06879 Note: 1. Balls are shorted together via the substrate but not connected to the die. 7/42 M29W641DH, M29W641DL, M29W641DU SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. Write Protect (WP). The Write Protect pin is available in the M29W641DH and M29W641DL only. It provides a hardware method of protecting the highest address block for the M29W641DH and the lowest address block for the M29W641DL. The Write Protect pin must not be left floating or unconnected. When Write Protect is Low, VIL , the memory protects either the highest or lowest address block; Program and Erase operations in this block are ignored while Write Protect is Low. When Write Protect is High, VIH, the memory reverts to the previous protection status for this block. Program and Erase operations can now modify the data in this block unless the block is protected using Block Protection. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, V OL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- 8/42 comes high-impedance. See Table 13 and Figure 12, Reset/Block Temporary Unprotect AC Characteristics. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if Write Protect (WP) is at V IL, then one of the two outermost blocks will remain protected even if RP is at V ID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See Table 13 and Figure 12, Reset/Block Temporary Unprotect AC Characteristics, for more details. Holding RP at V ID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. VPP (VPP). When the VPP pin is raised to VPPH the memory automatically enters the Unlock Bypass mode. When the pin is returned to V IH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to V PP and from V PP to VIH must be slower than tVHVPP, see Figure 13. Never raise the pin to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. VCC Supply Voltage (2.7V to 3.6V). VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. VCCQ Supply Voltage (1.8V to 3.6V). VCCQ provides the power supply to the I/O pins and enables all Outputs to be powered independently of VCC. M29W641DH, M29W641DL, M29W641DU 0.1µF ceramic capacitor close to the pin for current surge protection (high frequency, inherently low inductance capacitors should be as close as possible to the device). See Figure 8, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required V PP program and erase currents. See Table 9, DC Characteristics. VCCQ can be tied to VCC or can use a separate supply. VSS Ground. VSS is the reference for all voltage measurements. The device features two V SS pins which must be both connected to the system ground. Note: Each device in a system should have VCC, VCCQ and VPP decoupled from VSS with a Table 2. Bus Operations Operation Address Inputs A0-A21 Data Inputs/Outputs DQ15-DQ0 E G W Bus Read VIL VIL VIH Cell Address Bus Write VIL VIH VIL Command Address X VIH VIH X Hi-Z Standby VIH X X X Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 0020h Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH 22C7h Output Disable Extended Memory Block Verify Code VIL VIL VIH A0 = VIH, A1 = VIH, A6 = VIL, A9 = VID, Others VIL or VIH Data Output Data Input 98h (factory locked, WP protects highest address block) 18h (not factory locked, WP protects highest address block) 88h (factory locked, WP protects lowest block) 08h (not factory locked, WP protects lowest block) Note: X = VIL or VIH. 9/42 M29W641DH, M29W641DL, M29W641DU BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 9, Read Mode AC Waveforms, and Table 10, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 10 and Figure 11, Write AC Waveforms, and Table 11 and Table 12, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V IH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should 10/42 be held within VCC ± 0.2V. For the Standby current level see Table 9, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 2, Bus Operations. Block Protect and Chip Unprotect. Groups of blocks can be protected against accidental Program or Erase. The whole chip can be unprotected to allow the data inside the blocks to be changed. Write Protect (WP) can be used to protect one of the outermost blocks. When Write Protect (WP) is at V IL one of the two outermost blocks is protected and remains protected regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin status. For the M29W641DH, it is the highest addressed block that can be protected. For the M29W641DL, it is the lowest. Block Protect and Chip Unprotect operations are described in Appendix D. M29W641DH, M29W641DL, M29W641DU COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. See Table 3 for a summary of the commands. Read/Reset Command The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a Block erase operation then the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. Auto Select Command The Auto Select command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Memory Block Verify Code. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands are ignored. In Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either V IL or VIH. The Device Code for the M29W641D is 22C7h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = V IL , A1 = V IH, and A12-A21 specifying the address of the block. The other address bits may be set to either V IL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output. Read CFI Query Command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the de- vice is in the Read Array mode, or when the device is in Autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/ Reset command would be needed if the device is to be put in the Read Array mode from Autoselected mode. See Appendix B, Table 18 to Table 23 for details on the information contained in the Common Flash Interface (CFI) memory area. Program Command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 4. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Fast Program Commands There is a Fast Program command available to improve the programming throughput, by writing several adjacent words or bytes in parallel: the Double Word Program command. Double Word Program Command. The Double Word Program command is used to write a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus write cycles are necessary to issue the Double Word Program command. 11/42 M29W641DH, M29W641DL, M29W641DU ■ ■ ■ The first bus cycle sets up the Double Word Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. Programming should not be attempted when VPP is not at V PPH. After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other Bank output the contents of the memory array. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Typical Program times are given in Table 4, Program, Erase Times and Program, Erase Endurance Cycles. Unlock Bypass Command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory enters Unlock Bypass mode. When in this mode the memory can be read as if in Read mode. When V PPH is applied to the VPP pin the memory automatically enters the Unlock Bypass mode and the Unlock Bypass Program command can be issued immediately. Unlock Bypass Program Command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the ad- 12/42 dress and data, and starts the Program/Erase Controller. A Program operation initiated by issuing the Unlock Bypass Program command is identical to a Program operation initiated by issuing the Program command. It cannot be aborted and a Bus Read operation will output the Status Register. See the Program Command paragraph for further details. Unlock Bypass Reset Command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/ Reset command does not exit from Unlock Bypass Mode. Chip Erase Command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 4. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. Block Erase Command The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of M29W641DH, M29W641DL, M29W641DU the lowest address block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register section for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 4. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Erase Suspend Command The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency time of the Erase Suspend Command being issued. Once the Program/ Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. Erase Resume Command The Erase Resume command must be used to restart the Program/Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once. Enter Extended Block Command The device has an extra 32 KWord block (Extended Block) that can only be accessed using the Enter Extended Block command. Three Bus write cycles are required to issue the Extended Block command. Once the command has been issued the device enters Extended Block mode where all Bus Read or Write operations to the Boot Block addresses access the Extended Block. The Extended Block (with the same address as the Boot Blocks) cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode the Boot Blocks are not accessible. To exit from the Extended Block mode the Exit Extended Block command must be issued. The Extended Block can be protected, however once protected the protection cannot be undone. Exit Extended Block Command The Exit Extended Block command is used to exit from the Extended Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command. Block Protect and Chip Unprotect Commands Groups of blocks can be protected against accidental Program or Erase. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block Protect and Chip Unprotect operations are described in Appendix D. 13/42 M29W641DH, M29W641DL, M29W641DU Command Length Table 3. Commands Bus Write Operations 1st 2nd Addr Data 1 X F0 3 555 Auto Select 3 Program 3rd 4th Addr Data Addr Data AA 2AA 55 X F0 555 AA 2AA 55 555 90 4 555 AA 2AA 55 555 A0 Double Word Program 3 555 50 PA0 PD0 PA1 PD1 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 Block Erase 6+ 555 AA 2AA 55 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read CFI Query 1 55 98 Enter Extended Block 3 555 AA 2AA Exit Extended Block 4 555 AA 2AA 5th Addr Data PA PD 80 555 555 80 55 555 88 55 555 90 6th Addr Data Addr Data AA 2AA 55 555 10 555 AA 2AA 55 BA 30 X 00 Read/Reset Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. Table 4. Program, Erase Times and Program, Erase Endurance Cycles Typ (1, 2) Max(2) Unit Chip Erase 80 400(3) s Block Erase (32 KWords) 0.8 6(4) s 50(4) µs Parameter Min Erase Suspend Latency Time Program (Word) 10 200(3) µs Double Word Program 10 200(3) µs Chip Program (Word by Word) 40 200(3) s Chip Program (Double Word) 20 100(3) s Program/Erase Cycles (per Block) Data Retention Note: 1. 2. 3. 4. 14/42 100,000 cycles 20 years Typical values measured at room temperature and nominal voltages. Sampled, but not 100% tested. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. Maximum value measured at worst case conditions for both temperature and VCC. M29W641DH, M29W641DL, M29W641DU STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 5, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 5, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 6, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly. 15/42 M29W641DH, M29W641DL, M29W641DU Table 5. Status Register Bits Address DQ7 DQ6 DQ5 DQ3 DQ2 RB(1) Program Any Address DQ7 Toggle 0 – – 0 Program During Erase Suspend Any Address DQ7 Toggle 0 – – 0 Program Error Any Address DQ7 Toggle 1 – – 0 Chip Erase Any Address 0 Toggle 0 1 Toggle 0 Erasing Block 0 Toggle 0 0 Toggle 0 Non-Erasing Block 0 Toggle 0 0 No Toggle 0 Erasing Block 0 Toggle 0 1 Toggle 0 Non-Erasing Block 0 Toggle 0 1 No Toggle 0 Erasing Block 1 No Toggle 0 – Toggle 1 Operation Block Erase before timeout Block Erase Erase Suspend Non-Erasing Block Data read as normal Good Block Address 0 Toggle 1 1 No Toggle 0 Faulty Block Address 0 Toggle 1 1 Toggle 0 Erase Error Note: 1. Only the M29W641DU device is concerned. 2. Unspecified data bits should be ignored. 16/42 1 M29W641DH, M29W641DL, M29W641DU Figure 5. Data Polling Flowchart Figure 6. Data Toggle Flowchart START START READ DQ6 READ DQ5 & DQ7 at VALID ADDRESS READ DQ5 & DQ6 DQ7 = DATA YES DQ6 = TOGGLE NO NO YES NO DQ5 =1 NO YES DQ5 =1 YES READ DQ7 at VALID ADDRESS READ DQ6 TWICE DQ7 = DATA YES DQ6 = TOGGLE NO FAIL PASS NO YES FAIL PASS AI90194 AI90195B 17/42 M29W641DH, M29W641DL, M29W641DU MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute Maximum Ratings Symbol Parameter Min Max Unit TBIAS Temperature Under Bias –50 125 °C TSTG Storage Temperature –65 150 °C VCCQ Input/Output Supply Voltage (1,2) –0.6 4 V VCC Supply Voltage –0.6 4 V VID Identification Voltage –0.6 13.5 V Program Voltage –0.6 13.5 V VPP(3) Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to V CC +2V during transition and for less than 20ns during transitions. 3. VPP must not remain at 12V for more than a total of 80hrs. 18/42 M29W641DH, M29W641DL, M29W641DU DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7. Operating and AC Measurement Conditions M29W641D Parameter 70 90 100 120 Unit Min Max Min Max Min Max Min Max VCC Supply Voltage 3.0 3.6 2.7 3.6 3.0 3.6 2.7 3.6 V VCCQ Supply Voltage 3.0 3.6 2.7 3.6 1.65 1.95 1.65 1.95 V Ambient Operating Temperature –40 85 –40 85 –40 85 –40 85 °C Load Capacitance (CL) 30 Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 30 30 30 pF 10 10 10 10 ns 0 to VCCQ 0 to VCCQ 0 to VCCQ 0 to VCCQ V VCCQ/2 VCCQ/2 VCCQ/2 VCCQ/2 V Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit VPP VCCQ VCC VCCQ VCCQ 25kΩ VCCQ/2 0V DEVICE UNDER TEST AI05557b 25kΩ 0.1µF 0.1µF CL 0.1µF CL includes JIG capacitance AI05558b Table 8. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: Sampled only, not 100% tested. 19/42 M29W641DH, M29W641DL, M29W641DU Table 9. DC Characteristics Symbol Parameter Test Condition Min Max Unit 0V ≤ VIN ≤ VCCQ ±1 µA 0V ≤ VOUT ≤ VCCQ ±1 µA ILI Input Leakage Current ILO Output Leakage Current ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6 MHz 10 mA ICC2 Supply Current (Standby) E = VCC ±0.2V, RP = VCC ±0.2V 100 µA VPP pin = VIL or VIH 20 mA VPP pin = VPPH 20 mA ICC3 Supply Current (Program/ Erase) Program/Erase Controller active VIL Input Low Voltage VCCQ ≤ VCC –0.5 0.8 V VIH Input High Voltage VCCQ ≤ VCC 0.7VCCQ VCCQ + 0.3 V 11.5 12.5 V VPPH Voltage for VPP Program Acceleration VCC = 3.0V ±10% IPP Current for VPP Program Acceleration VCC = 3.0V ±10% 15 mA VOL Output Low Voltage IOL = 4.0mA, VCC = VCCmin 0.45 V VOH (1) Output High Voltage VID Identification Voltage 11.5 12.5 V Program/Erase Lockout Supply Voltage 1.8 2.3 V VLKO (1) Note: 1. Sampled only, not 100% tested. 20/42 IOH = –2.0mA, VCC = VCCmin 0.85VCCQ V IOH = –100µA, VCC = VCCmin VCCQ – 0.4 V M29W641DH, M29W641DL, M29W641DU Figure 9. Read Mode AC Waveforms tAVAV A0-A21 VALID tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQX tGHQX tGLQV tGHQZ DQ0-DQ7/ DQ8-DQ15 VALID AI06699 Table 10. Read AC Characteristics M29W641D Symbol Alt Parameter Test Condition Unit 70 90 100 120 tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL Min 70 90 100 120 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL Max 70 90 100 120 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 0 0 ns tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 90 100 120 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 0 0 ns tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 35 35 50 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 25 30 30 30 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 30 30 30 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition Min 0 0 0 0 ns Note: 1. Sampled only, not 100% tested. 21/42 M29W641DH, M29W641DL, M29W641DU Figure 10. Write AC Waveforms, Write Enable Controlled tAVAV A0-A21 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 tWHDX VALID VCC tVCHEL RB tWHRL AI06800b Note: 1. RB concerns the M29W461DU only. Table 11. Write AC Characteristics, Write Enable Controlled M29W641D Symbol Alt Parameter Unit 70 90 100 120 tAVAV tWC Address Valid to Next Address Valid Min 70 90 100 120 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 0 ns tWLWH tWP Write Enable Low to Write Enable High Min 35 35 35 50 ns tDVWH tDS Input Valid to Write Enable High Min 45 45 45 50 ns tWHDX tDH Write Enable High to Input Transition Min 0 0 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 30 30 ns tAVWL tAS Address Valid to Write Enable Low Min 0 0 0 0 ns tWLAX tAH Write Enable Low to Address Transition Min 45 45 45 50 ns Output Enable High to Write Enable Low Min 0 0 0 0 ns tGHWL tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 0 0 ns tWHRL(1) tBUSY Program/Erase Valid to RB Low Max 90 90 90 90 ns tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 50 50 µs Note: 1. This timing concerns the M29W461DU only. 22/42 M29W641DH, M29W641DL, M29W641DU Figure 11. Write AC Waveforms, Chip Enable Controlled tAVAV A0-A21 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 tEHDX VALID VCC tVCHWL RB tEHRL AI06801b Note: 1. RB concerns the M29W461DU only. Table 12. Write AC Characteristics, Chip Enable Controlled M29W641D Symbol Alt Parameter Unit 70 90 100 120 tAVAV tWC Address Valid to Next Address Valid Min 70 90 100 120 ns tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 45 50 ns tDVEH tDS Input Valid to Chip Enable High Min 45 45 45 50 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 0 ns tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 30 30 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 0 0 0 ns tELAX tAH Chip Enable Low to Address Transition Min 45 45 45 50 ns Output Enable High Chip Enable Low Min 0 0 0 0 ns tGHEL tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 0 0 ns tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 90 90 90 90 ns tVCHWL tVCS VCC High to Write Enable Low Min 50 50 50 50 µs Note: 1. This timing concerns the M29W461DU only. 23/42 M29W641DH, M29W641DL, M29W641DU Figure 12. Reset/Block Temporary Unprotect AC Waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL tPLPX RP tPHPHH tPLYH AI06802b Note: 1. RB concerns the M29W461DU only. Table 13. Reset/Block Temporary Unprotect AC Characteristics M29W641D Symbol Alt tPHWL (1) tPHEL tPHGL 100 120 Min 50 50 50 50 ns tRB RB High to Write Enable Low, Chip Enable Low, Output Enable Low Min 0 0 0 0 ns Max 50 50 50 50 µs RP Pulse Width Min 500 500 500 500 ns RP Rise Time to VID Min 500 500 500 500 ns VPP Rise and Fall Time Min 250 250 250 250 ns tREADY RP Low to Read Mode tPLPX tRP tPHPHH (1) tVIDR tVHVPP (1) 90 RP High to Write Enable Low, Chip Enable Low, Output Enable Low tRHGL (1, 2) tPLYH Unit 70 tRH (1) tRHWL (1, 2) tRHEL (1, 2) Parameter Note: 1. Sampled only, not 100% tested. 2. These timings concern the M29W461DU only. Figure 13. Accelerated Program Timing Waveforms VPP VPP Pin VIL or VIH tVHVPP tVHVPP AI06806 24/42 M29W641DH, M29W641DL, M29W641DU PACKAGE MECHANICAL Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C A1 TSOP-a α L Note: Drawing is not to scale. Table 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 Max 0.0472 A1 0.100 0.050 0.150 0.0039 0.0020 0.0059 A2 1.000 0.950 1.050 0.0394 0.0374 0.0413 B 0.170 0.270 0.0067 0.0106 C 0.100 0.210 0.0039 0.0083 CP 0.100 0.0039 D 19.800 20.200 0.7795 0.7953 D1 18.300 18.500 0.7205 0.7283 – – – – E 11.900 12.100 0.4685 0.4764 L 0.500 0.700 0.0197 0.0276 alfa 0 5 0 5 e N 0.500 48 0.0197 48 25/42 M29W641DH, M29W641DL, M29W641DU Figure 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Bottom view package outline D D1 SD FD e E ddd SE E1 BALL "A1" FE A e b A2 A1 BGA-Z33 Note: Drawing is not to scale. Table 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 A1 0.0472 0.250 A2 0.0098 0.900 b Max 0.350 0.450 0.0354 0.0138 0.0177 D 7.000 6.900 7.100 0.2756 0.2717 0.2795 D1 5.600 – – 0.2205 – – ddd – – 0.100 – – 0.0039 E 11.000 10.900 11.100 0.4331 0.4291 0.4370 E1 8.800 – – 0.3465 – – e 0.800 – – 0.0315 – – FD 0.700 – – 0.0276 – – FE 1.100 – – 0.0433 – – SD 0.400 – – 0.0157 – – SE 0.400 – – 0.0157 – – 26/42 M29W641DH, M29W641DL, M29W641DU PART NUMBERING Table 16. Ordering Information Scheme Example: M29W641DL 70 N 1 T Device Type M29 Operating Voltage W = VCC = 2.7 to 3.6V Device Function 641DH = 64 Mbit (x16), Uniform Block, Write Protection on highest address Block 641DL = 64 Mbit (x16), Uniform Block, Write Protection on Lowest Address Block 641DU = 64 Mbit (x16), Uniform Block, No Write Protection Speed 70 = 70ns 90 = 90ns 10 = 100ns 12 = 120ns Package N = TSOP48: 12 x 20 mm (M29W641DH and M29W641DL only) ZA = TFBGA63: 7 x 11mm, 0.80mm pitch (M29W641DU only) Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Option T = Tape & Reel Packing E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office. Devices are shipped from the factory with the memory content bits erased to 1. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 27/42 M29W641DH, M29W641DL, M29W641DU APPENDIX A. BLOCK ADDRESSES Table 17. Block Addresses Block KWords Protection Block Group Address Range 0 32 1 32 2 32 010000h–017FFFh 3 32 018000h–01FFFFh 4 32 020000h–027FFFh 5 32 000000h–007FFFh (1) Protection Group 008000h–00FFFFh 028000h–02FFFFh Protection Group 6 32 030000h–037FFFh 7 32 038000h–03FFFFh 8 32 040000h–047FFFh 9 32 048000h–04FFFFh Protection Group 10 32 050000h–057FFFh 11 32 058000h–05FFFFh 12 32 060000h–067FFFh 13 32 068000h–06FFFFh Protection Group 14 32 070000h–077FFFh 15 32 078000h–07FFFFh 16 32 080000h–087FFFh 17 32 088000h–08FFFFh Protection Group 18 32 090000h–097FFFh 19 32 098000h–09FFFFh 20 32 0A0000h–0A7FFFh 21 32 0A8000h–0AFFFFh Protection Group 22 32 0B0000h–0B7FFFh 23 32 0B8000h–0BFFFFh 24 32 0C0000h–0C7FFFh 25 32 0C8000h–0CFFFFh Protection Group 26 32 0D0000h–0D7FFFh 27 32 0D8000h–0DFFFFh 28 32 0E0000h–0E7FFFh 29 32 0E8000h–0EFFFFh Protection Group 28/42 30 32 0F0000h–0F7FFFh 31 32 0F8000h–0FFFFFh M29W641DH, M29W641DL, M29W641DU Block KWords 32 32 33 32 Protection Block Group Address Range 100000h–107FFFh 108000h–10FFFFh Protection Group 34 32 110000h–117FFFh 35 32 118000h–11FFFFh 36 32 120000h–127FFFh 37 32 128000h–12FFFFh Protection Group 38 32 130000h–137FFFh 39 32 138000h–13FFFFh 40 32 140000h–147FFFh 41 32 148000h–14FFFFh Protection Group 42 32 150000h–157FFFh 43 32 158000h–15FFFFh 44 32 160000h–167FFFh 45 32 168000h–16FFFFh Protection Group 46 32 170000h–177FFFh 47 32 178000h–17FFFFh 48 32 180000h–187FFFh 49 32 188000h–18FFFFh Protection Group 50 32 190000h–197FFFh 51 32 198000h–19FFFFh 52 32 1A0000h–1A7FFFh 53 32 1A8000h–1AFFFFh Protection Group 54 32 1B0000h–1B7FFFh 55 32 1B8000h–1BFFFFh 56 32 1C0000h–1C7FFFh 57 32 1C8000h–1CFFFFh Protection Group 58 32 1D0000h–1D7FFFh 59 32 1D8000h–1DFFFFh 60 32 1E0000h–1E7FFFh 61 32 1E8000h–1EFFFFh Protection Group 62 32 1F0000h–1F7FFFh 63 32 1F8000h–1FFFFFh 64 32 200000h–207FFFh 65 32 208000h–20FFFFh Protection Group 66 32 210000h–217FFFh 67 32 218000h–21FFFFh 29/42 M29W641DH, M29W641DL, M29W641DU Block KWords 68 32 69 32 Protection Block Group Address Range 220000h–227FFFh 228000h–22FFFFh Protection Group 70 32 230000h–237FFFh 71 32 238000h–23FFFFh 72 32 240000h–247FFFh 73 32 248000h–24FFFFh Protection Group 74 32 250000h–257FFFh 75 32 258000h–25FFFFh 76 32 260000h–267FFFh 77 32 268000h–26FFFFh Protection Group 78 32 270000h–277FFFh 79 32 278000h–27FFFFh 80 32 280000h–287FFFh 81 32 288000h–28FFFFh Protection Group 82 32 290000h–297FFFh 83 32 298000h–29FFFFh 84 32 2A0000h–2A7FFFh 85 32 2A8000h–2AFFFFh Protection Group 86 32 2B0000h–2B7FFFh 87 32 2B8000h–2BFFFFh 88 32 2C0000h–2C7FFFh 89 32 2C8000h–2CFFFFh Protection Group 90 32 2D0000h–2D7FFFh 91 32 2D8000h–2DFFFFh 92 32 2E0000h–2E7FFFh 93 32 2E8000h–2EFFFFh Protection Group 94 32 2F0000h–2F7FFFh 95 32 2F8000h–2FFFFFh 96 32 300000h–307FFFh 97 32 308000h–30FFFFh Protection Group 98 32 310000h–317FFFh 99 32 318000h–31FFFFh 100 32 320000h–327FFFh 101 32 328000h–32FFFFh Protection Group 30/42 102 32 330000h–337FFFh 103 32 338000h–33FFFFh M29W641DH, M29W641DL, M29W641DU Block KWords 104 32 105 32 Protection Block Group Address Range 340000h–347FFFh 348000h–34FFFFh Protection Group 106 32 350000h–357FFFh 107 32 358000h–35FFFFh 108 32 360000h–367FFFh 109 32 368000h–36FFFFh Protection Group 110 32 370000h–377FFFh 111 32 378000h–37FFFFh 112 32 380000h–387FFFh 113 32 388000h–38FFFFh Protection Group 114 32 390000h–397FFFh 115 32 398000h–39FFFFh 116 32 3A0000h–3A7FFFh 117 32 3A8000h–3AFFFFh Protection Group 118 32 3B0000h–3B7FFFh 119 32 3B8000h–3BFFFFh 120 32 3C0000h–3C7FFFh 121 32 3C8000h–3CFFFFh Protection Group 122 32 3D0000h–3D7FFFh 123 32 3D8000h–3DFFFFh 124 32 3E0000h–3E7FFFh 125 32 126 32 127 32 3E8000h–3EFFFFh Protection Group 3F0000h–3F7FFFh 3F8000h–3FFFFFh Note: 1. Used as the Extended Block Addresses in Extended Block mode. 31/42 M29W641DH, M29W641DL, M29W641DU APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Table 18 to Table 23 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 23, Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Table 18. Query Structure Overview Address Sub-section Name Description 10h CFI Query Identification String Command set ID and algorithm data offset 1Bh System Interface Information Device timing & voltage information 27h Device Geometry Definition Flash device layout 40h Primary Algorithm-specific Extended Query table Additional information specific to the Primary Algorithm (optional) 61h Security Code Area 64 bit unique device number Note: Query data are always presented on the lowest order data outputs. Table 19. CFI Query Identification String Address Data Description 10h 0051h 11h 0052h 12h 0059h 13h 0002h 14h 0000h 15h 0040h 16h 0000h 17h 0000h 18h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported 19h 0000h Address for Alternate Algorithm extended Query table 1Ah 0000h “Q” Query Unique ASCII String "QRY" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 22) Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. 32/42 Value AMD Compatible P = 40h NA NA M29W641DH, M29W641DL, M29W641DU Table 20. CFI Query System Interface Information Address Data Description Value 1Bh 0027h VCC Logic Supply Minimum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV 2.7V 1Ch 0036h VCC Logic Supply Maximum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV 3.6V 1Dh 00B5h VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 11.5V 1Eh 00C5h VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 12.5V 1Fh 0004h Typical timeout per single word program = 2n µs 16µs 20h 0000h Typical timeout for minimum size write buffer program = 2n µs NA 21h 000Ah Typical timeout per individual block erase = 2n ms 1s 22h 0000h Typical timeout for full chip erase = 2n ms NA 23h 0004h Maximum timeout for word program = 2n times typical 24h 0000h Maximum timeout for write buffer program = 2n times typical NA 25h 0003h Maximum timeout per individual block erase = 2n times typical 8s 26h 0000h Maximum timeout for chip erase = 2n times typical NA 256 µs Table 21. Device Geometry Definition Address Data Description Value 27h 0017h Device Size = 2n in number of bytes 28h 29h 0001h 0000h Flash Device Interface Code description 2Ah 2Bh 0000h 0000h Maximum number of bytes in multi-byte program or page = 2n NA 2Ch 0001h Number of Erase Block Regions. It specifies the number of regions containing contiguous Erase Blocks of the same size. 1 2Dh 2Eh 007Fh 0000h Region 1 Information Number of identical size erase block = 007Fh+1 2Fh 30h 0000h 0001h Region 1 Information Block size in Region 1 = 0100h * 256 byte 8 MByte x16 Async. 128 64 KByte 33/42 M29W641DH, M29W641DL, M29W641DU Table 22. Primary Algorithm-Specific Extended Query Table Address Data Description 40h 0050h 41h 0052h 42h 0049h 43h 0031h Major version number, ASCII "1" 44h 0030h Minor version number, ASCII "0" 45h 0000h Address Sensitive Unlock (bits 1 to 0) 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) Yes 46h 0002h Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write 2 47h 0004h Block Protection 00 = not supported, x = number of blocks per protection group 4 48h 0001h Temporary Block Unprotect 00 = not supported, 01 = supported 49h 0004h Block Protect /Unprotect 04 = M29W400B 4Ah 0000h Simultaneous Operations, 00 = not supported No 4Bh 0000h Burst Mode, 00 = not supported, 01 = supported No 4Ch 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No 4Dh 00B5h VPP Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 11.5V 4Eh 00C5h VPP Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 12.5V "P" Primary Algorithm extended Query table unique ASCII string “PRI” 34/42 Data 61h XXXX 62h XXXX 63h XXXX 64h XXXX "R" "I" Description 64 bit: unique device number Yes 4 Table 23. Security Code Area Address Value M29W641DH, M29W641DL, M29W641DU APPENDIX C. EXTENDED MEMORY BLOCK The M29W641D has an extra block, the Extended Block, that can be accessed using a dedicated command. This Extended Block is 32 KWords. It is used as a security block (to provide a permanent security identification number) or to store additional information. The Extended Block is either Factory Locked or Customer Lockable, its status is indicated by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be changed. When set to ‘1’, it indicates that the device is factory locked and the Extended Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific procedure must be followed to read it. See “Extended Memory Block Verify Code” in Table 2, Bus Operations, for details of how to read bit DQ7. The Extended Block can only be accessed when the device is in Extended Block mode. For details of how the Extended Block mode is entered and exited, refer to the Enter Extended Block Command and Exit Extended Block Command paragraphs, and to Table 3, “Commands”. Factory Locked Extended Block In devices where the Extended Block is factory locked, the Security Identification Number is written to the Extended Block address space (see Table 24, Extended Block Address and Data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected. Customer Lockable Extended Block A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to ‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the Extended Block but care must be taken because the protection of the Extended Block is not reversible. There are two ways of protecting the Extended Block: ■ Issue the Enter Extended Block command to place the device in Extended Block mode, then use the In-System Technique (refer to Appendix D, In-System Technique and to the corresponding flowcharts, Figures 18 and 19, for a detailed explanation of the technique). ■ Issue the Enter Extended Block command to place the device in Extended Block mode, then use the Programmer Technique (refer to Appendix D, Programmer Technique and to the corresponding flowcharts, Figures 16 and 17, for a detailed explanation of the technique). Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode. Table 24. Extended Block Address and Data Device Address(1) Data x16 Factory Locked 000000h-000007h Security Identification Number 000008h-007FFFh Unavailable M29W641D Customer Lockable Determined by Customer Note: 1. See Table 17, Block Addresses. 35/42 M29W641DH, M29W641DL, M29W641DU APPENDIX D. BLOCK PROTECTION Block protection can be used to prevent any operation from modifying the data stored in the memory. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. Programmer Technique The Programmer technique uses high (V ID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 16, Programmer Equipment Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 17, Programmer Equipment Chip Unprotect Flowchart. Table 25, Programmer Technique Bus Operations, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. In-System Technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 18, In-System Equipment Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 19, In-System Equipment Chip Unprotect Flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. Table 25. Programmer Technique Bus Operations E G W Address Inputs A0-A21 Data Inputs/Outputs DQ15-DQ0 Block (Group) Protect(1) VIL VID VIL Pulse A9 = VID, A12-A21 Block Address Others = X X Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH Others = X X Block (Group) Protection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A21 Block Address Others = X Pass = XX01h Retry = XX00h Block (Group) Unprotection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A21 Block Address Others = X Retry = XX01h Pass = XX00h Operation Note: 1. Block Protection Groups are shown in Appendix A, Tables 17. 36/42 M29W641DH, M29W641DL, M29W641DU Figure 16. Programmer Equipment Group Protect Flowchart START Set-up ADDRESS = GROUP ADDRESS W = VIH n=0 G, A9 = VID, E = VIL Protect Wait 4µs W = VIL Wait 100µs W = VIH E, G = VIH, A0, A6 = VIL, A1 = VIH E = VIL Verify Wait 4µs G = VIL Wait 60ns Read DATA DATA NO = 01h YES A9 = VIH E, G = VIH ++n = 25 NO End YES PASS A9 = VIH E, G = VIH FAIL AI05574 37/42 M29W641DH, M29W641DL, M29W641DU Figure 17. Programmer Equipment Chip Unprotect Flowchart START Set-up PROTECT ALL GROUPS n=0 CURRENT GROUP = 0 A6, A12, A15 = VIH(1) E, G, A9 = VID Unprotect Wait 4µs W = VIL Wait 10ms W = VIH E, G = VIH ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1, A6 = VIH E = VIL Wait 4µs G = VIL INCREMENT CURRENT GROUP Verify Wait 60ns Read DATA NO End NO 38/42 ++n = 1000 DATA = 00h YES LAST GROUP YES YES A9 = VIH E, G = VIH A9 = VIH E, G = VIH FAIL PASS NO AI05575 M29W641DH, M29W641DL, M29W641DU Figure 18. In-System Equipment Group Protect Flowchart Set-up START n=0 RP = VID Protect WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Wait 100µs Verify WRITE 40h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Wait 4µs READ DATA ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL DATA NO = 01h YES End RP = VIH ISSUE READ/RESET COMMAND PASS ++n = 25 NO YES RP = VIH ISSUE READ/RESET COMMAND FAIL AI05576 39/42 M29W641DH, M29W641DL, M29W641DU Figure 19. In-System Equipment Chip Unprotect Flowchart START Set-up PROTECT ALL GROUPS n=0 CURRENT GROUP = 0 RP = VID WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Unprotect WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Wait 10ms Verify WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH Wait 4µs READ DATA ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH NO End NO ++n = 1000 YES DATA = 00h INCREMENT CURRENT GROUP YES LAST GROUP NO YES RP = VIH RP = VIH ISSUE READ/RESET COMMAND ISSUE READ/RESET COMMAND FAIL PASS AI05577 40/42 M29W641DH, M29W641DL, M29W641DU REVISION HISTORY Table 26. Document Revision History Date Version 30-Apr-2002 -01 Document released 1.1 When in Extended Block mode, the block at the boot block address can be used as OTP. Data Toggle Flow chart corrected. Double Word Program Time (typ) changed to 20s. Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 01 equals 1.0). 2.0 New Part Numbers added. 100ns and 120ns Speed Classes added. TFBGA63 package added. VIO removed from and VCCQ added to Table 6, Absolute Maximum Ratings. VCCQ added to Table 7, Operating and AC Measurement Conditions. Ready/Busy pin (TFBGA63 package) added to the signals (concerns M29W641DU only). Figure 7, AC Measurement I/O Waveform, and Figure 8, AC Measurement Load Circuit, modified. Unlock Bypass Commands clarified and VCCQ description specified in SIGNAL DESCRIPTIONS section. Test Conditions modified for ILI, ILO, VIL, VIH, VOL and VOH parameters in Table 9, DC Characteristics, and VIL, VIH, VOL and VOH parameters corrected. tWLWH, tDVWH, tWLAX, tWHRL parameters modified for 90ns speed class in Table 11, Write AC Characteristics, Write Enable Controlled. tELEH, tDVEH, tELAX and tEHRL parameters modified for 90ns speed class in Table 12, Write AC Characteristics, Chip Enable Controlled. tPLYH parameter added to Table 13, Reset/Block Temporary Unprotect AC Characteristics. Data and Value modified for address 2Dh, and Data modified for address 30h in Table 21, Device Geometry Definition. Description modified at address offset 4Eh in Table 22. Data Retention and Erase Suspend Latency Time parameters added to Table 6, Program, Erase Times and Program, Erase Endurance Cycles, and Typical after 100k W/E Cycles column removed. IID (Identification) current removed from Table 9, DC Characteristics. Lead-free package options E and F added to Table 16, Ordering Information Scheme. Appendix C, EXTENDED MEMORY BLOCK, added. VSS pin connection to ground clarified. Auto Select Command is used to read the Extended Memory Block. Note added to Table 16, Ordering Information Scheme. 05-Sep-2002 8-Apr-2003 Revision Details 41/42 M29W641DH, M29W641DL, M29W641DU Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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