M36L0R7040T0 M36L0R7040B0 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 16 Mbit PSRAM, 1.8V Supply, Multi-Chip Package FEATURES SUMMARY MULTI-CHIP PACKAGE – 1 die of 128 Mbit (8Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory – 1 die of 16 Mbit (1Mb x16) Pseudo SRAM ■ SUPPLY VOLTAGE – VDDF = VDDP = VDDQ = 1.7 to 1.95V – VPP = 9V for fast program (12V tolerant) ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code (Top Flash Configuration) M36L0R7040T0: 88C4h – Device Code (Bottom Flash Configuration) M36L0R7040B0: 88C5h ■ PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY ■ SYNCHRONOUS / ASYNCHRONOUS READ – Synchronous Burst Read mode: 54MHz – Asynchronous Page Read mode – Random Access: 85ns ■ SYNCHRONOUS BURST READ SUSPEND ■ PROGRAMMING TIME – 10µs typical Word program time using Buffer Program ■ MEMORY ORGANIZATION – Multiple Bank Memory Array: 8 Mbit Banks – Parameter Blocks (Top or Bottom location) ■ DUAL OPERATIONS – program/erase in one Bank while read in others – No delay between read and write operations ■ SECURITY – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ December 2004 Figure 1. Package FBGA TFBGA88 (ZAQ) 8 x 10mm BLOCK LOCKING – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – WPF for Block Lock-Down – Absolute Write Protection with VPP = VSS ■ COMMON FLASH INTERFACE (CFI) ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK PSRAM ■ ACCESS TIME: 70ns ■ LOW STANDBY CURRENT: 110µA ■ DEEP POWER DOWN CURRENT: 10µA ■ 1/18 M36L0R7040T0, M36L0R7040B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Clock (KF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Wait (WAITF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Chip Enable (E1P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Chip Enable (E2P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Write Enable (WP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Output Enable (GP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Upper Byte Enable (UBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/18 M36L0R7040T0, M36L0R7040B0 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Figure 5. Figure 6. Table 5. Table 6. Table 7. Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline15 Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3/18 M36L0R7040T0, M36L0R7040B0 SUMMARY DESCRIPTION The M36L0R7040T0 and M36L0R7040B0 combine two memory devices in a Multi-Chip Package: a 128-Mbit, Multiple Bank Flash memory, the M30L0R7000T0 or M30L0R7000B0, and a 16Mbit PseudoSRAM, the M69AR024B. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8x10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram VDDQ VPPF VDDF VDDP 23 16 A0-A22 DQ0-DQ15 EF GF WAITF A0-A22 (1) Address Inputs DQ0-DQ15 Common Data Input/Output VDDF Power Supply for Flash Memory VDDQ Flash Memory Power Supply for I/O Buffers VPPF Flash Optional Supply Voltage for Fast Program and Erase VSS Ground VDDP PSRAM Power Supply NC Not Connected Internally DU Do Not Use as Internally Connected Flash Memory Control Functions LF Latch Enable Input EF Chip Enable Input GF Output Enable Input WF Write Enable Input RPF Reset Input WPF Write Protect Input KF Burst Clock WAITF Wait Data in Burst Mode PSRAM Control Functions WF E1P Chip Enable Input RPF GP Output Enable Input WP Write Enable Input E2P Power-down Input KF UBP Upper Byte Enable Input E1P LBP Lower Byte Enable Input WPF LF M36L0R7040T0 M36L0R7040B0 Note: 1. A22-A20 are not connected to the PSRAM component. GP WP E2P UBP LBP VSS 4/18 Table 1. Signal Names AI08467 M36L0R7040T0, M36L0R7040B0 Figure 3. TFBGA Connections (Top view through package) 1 2 3 4 5 A DU DU B A4 A18 A19 VSS VDDF C A5 LBP NC VSS D A3 A17 NC E A2 A7 F A1 G 6 7 8 DU DU NC A21 A11 NC KF A22 A12 VPPF WP EP A9 A13 NC WPF LF A20 A10 A15 A6 UBP RPF WF A8 A14 A16 A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAITF NC H GP DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC J NC GF DQ9 DQ11 DQ4 DQ6 DQ15 VDDQ K EF DU DU NC VDDP NC VDDQ E2P L VSS VSS VDDQ VDDF VSS VSS VSS VSS M DU DU DU DU AI08732 5/18 M36L0R7040T0, M36L0R7040B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A22). Addresses A0-A19 are common inputs for the Flash memory and the PSRAM components. The other lines (A20-A22) are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory Program/Erase Controller or they select the cells to access in the PSRAM. The Flash memory component is accessed through the Chip Enable signal (EF) and through the Write Enable (WF) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP). Data Input/Output (DQ0-DQ15). In the Flash memory, the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. In the PSRAM the Upper Byte Data Inputs/Outputs, DQ8-DQ15, carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) is driven Low. The Lower Byte Data Inputs/Outputs, DQ0-DQ7, carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable input controls data output during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be 6/18 locked or unlocked. (See the Lock Status Table in the M30L0R7000T0 datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 6., Flash Memory DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 7., Flash Memory DC Characteristics - Voltages). Flash Latch Enable (LF). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Flash Clock (KF). The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during Asynchronous Read and in write operations. Flash Wait (WAITF). WAITF is a Flash output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable. asserted PSRAM Chip Enable (E1P). When (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. It is not allowed to set EF at VIL, E1P at VIL and E2P at VIH at the same time. PSRAM Chip Enable (E2P). The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode. M36L0R7040T0, M36L0R7040B0 It is not allowed to set EF at VIL, E1P at VIL and E2P at VIH at the same time. PSRAM Write Enable (WP). The Write Enable input controls writing to the PSRAM memory array. WP is active low. PSRAM Output Enable (GP). The Output Enable gates the outputs through the data buffers during a Read operation of the PSRAM memory. GP is active low. PSRAM Upper Byte Enable (UBP). The Upper Byte Enable input enables the upper byte for PSRAM (DQ8-DQ15). UBP is active low. PSRAM Lower Byte Enable (LBP). The Lower Byte Enable input enables the lower byte for PSRAM (DQ0-DQ7). LBP is active low. VDDF Supply Voltage. VDDF provides the power supply to the internal cores of the Flash memory component. It is the main power supply for all Flash operations (Read, Program and Erase). VDDP Supply Voltage. VDDP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM operations. VDDQ Supply Voltage. VDDQ provides the power supply for the Flash Memory I/O pins. This allows all Outputs to be powered independently of the Flash Memory core power supply, VDDF. VPPF Program Supply Voltage. VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against Program or Erase, while VPPF > VPP1F enables these functions (see Tables 6 and 7, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. Note: Each Flash memory device in a system should have their supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 6., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents. 7/18 M36L0R7040T0, M36L0R7040B0 FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: EF for the Flash memory and E1P and E2P for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations in the Flash memory and the PSRAM which would result in a data bus contention. Therefore it is recommended to put the other device in the high impedance state when reading the selected device. Figure 4. Functional Block Diagram VDDF VPPF VDDQ EF A20-A22 A0-A19 GF WF RPF WPF 128 Mbit Flash Memory DQ0-DQ15 WAITF LF KF VDDP E1P GP WP E2P 16 Mbit PSRAM UBP LBP VSS AI08468 8/18 M36L0R7040T0, M36L0R7040B0 Table 2. Main Operating modes EF GF WF LF Flash Read VIL VIL VIH VIL(2) VIH Flash Write VIL VIH VIL VIL(2) VIH Flash Address Latch VIL X VIH VIL VIH Flash Data Out or Hi-Z (3) Flash Output Disable VIL VIH VIH X VIH Hi-Z Flash Standby VIH X X X VIH Hi-Z X X X X VIL Hi-Z Operation Flash Reset RPF WAITF(4) E1P E2P GP WP LBP,UBP DQ15-DQ0 Flash Data Out Flash Data In PSRAM must be disabled Any PSRAM mode is allowed Hi-Z Hi-Z VIL VIH VIL VIH VIL PSRAM data out PSRAM Write VIL VIH VIH VIL VIL PSRAM data in Output Disable VIL VIH VIH VIH X Hi-Z VIH VIH X X X Hi-Z X VIL X X X Hi-Z PSRAM Read Flash Memory must be disabled PSRAM Standby PSRAM Deep Power-Down Note: 1. 2. 3. 4. Any Flash mode is allowed X = Don't care. LF can be tied to VIH if the valid address has been previously latched. Depends on GF. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R7000T0 datasheet for details. 9/18 M36L0R7040T0, M36L0R7040B0 FLASH MEMORY COMPONENT The M36L0R7040T0 and M36L0R7040B0 contain a 128 Mbit Flash memory. For detailed information on how to use the devices, see the M30L0R7000(T/B)0 datasheet which is available from the internet site http://www.st.com or from your local STMicroelectronics distributor. PSRAM COMPONENT The M36L0R7040T0 and M36L0R7040B0 contain a 16 Mbit PSRAM. For detailed information on how to use the device, see the M69AR024B datasheet 10/18 which is available from the internet site http:// www.st.com or from your local STMicroelectronics distributor. M36L0R7040T0, M36L0R7040B0 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute Maximum Ratings Value Symbol Parameter Unit Min Max Ambient Operating Temperature –25 85 °C TBIAS Temperature Under Bias –25 85 °C TSTG Storage Temperature –65 125 °C TLEAD Lead Temperature during Soldering (1) °C TA VIO VDDF, VDDQ, VDDP VPPF IO tVPPFH Input or Output Voltage –0.2 3.3 V Core and Input/Output Supply Voltages –0.2 2.5 V Flash Program Voltage –0.2 14 V Output Short Circuit Current 100 mA Time for VPPF at VPPFH 100 hours Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. ECOPACK® 7191395 specification, 11/18 M36L0R7040T0, M36L0R7040B0 DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC Measurement Conditions Flash Memory PSRAM Parameter Unit Min Max Min Max VDDF Supply Voltage 1.7 1.95 – – V VDDP Supply Voltage – – 1.7 1.95 V VDDQF Supply Voltage 1.7 1.95 – – V VPPF Supply Voltage (Factory environment) 8.5 12.6 – – V VPPF Supply Voltage (Application –0.4 VDDQ +0.4 – – V –25 85 –25 85 °C environment) Ambient Operating Temperature Load Capacitance (CL) Output Circuit Resistors (R1, R2) 30 50 pF 16.7 16.7 kΩ Input Rise and Fall Times 5 Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 5. AC Measurement I/O Waveform 5 ns 0 to VDDQ 0 to VDDQ V VDDQ/2 VDDQ/2 V Figure 6. AC Measurement Load Circuit VDDQ VDDQ VDDF VDDQ/2 VDDQ R1 0V DEVICE UNDER TEST AI06161 CL 0.1µF R2 0.1µF CL includes JIG capacitance AI08364B Table 5. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Note: Sampled only, not 100% tested. 12/18 Test Condition Min Max Unit VIN = 0V 12 pF VOUT = 0V 15 pF M36L0R7040T0, M36L0R7040B0 Table 6. Flash Memory DC Characteristics - Currents Symbol Parameter Test Condition ILI Input Leakage Current ILO Max Unit 0V ≤ VIN ≤ VDDQ ±1 µA Output Leakage Current 0V ≤ VOUT ≤ VDDQ ±1 µA Supply Current Asynchronous Read (f=6MHz) EF = VIL, GF = VIH 10 15 mA 4 Word 7 16 mA 8 Word 10 18 mA 16 Word 13 20 mA Continuous 18 25 mA 4 Word 16 18 mA 8 Word 18 20 mA 16 Word 21 25 mA Continuous 22 27 mA Supply Current Synchronous Read (f=40MHz) IDD1 Supply Current Synchronous Read (f=54MHz) Min Typ IDD2 Supply Current (Reset) RPF = VSS ± 0.2V 25 70 µA IDD3 Supply Current (Standby) EF = VDDF ± 0.2V 25 70 µA IDD4 Supply Current (Automatic Standby) EF = VIL, GF = VIH 25 70 µA VPPF = VPPH 8 15 mA VPPF = VDDF 10 20 mA VPPF = VPPH 8 15 mA VPPF = VDDF 10 20 mA Program/Erase in one Bank, Asynchronous Read in another Bank 20 35 mA Program/Erase in one Bank, Synchronous Read in another Bank 32 47 mA EF = VDDF ± 0.2V 25 70 µA VPPF = VPPH 2 5 mA VPPF = VDDF 0.2 5 µA VPPF = VPPH 2 5 mA VPPF = VDDF 0.2 5 µA VPPF Supply Current (Read) VPPF ≤ VDDF 0.2 5 µA VPPF Supply Current (Standby) VPPF ≤ VDDF 0.2 5 µA Supply Current (Program) IDD5 (1) Supply Current (Erase) Supply Current IDD6 (1,2) (Dual Operations) IDD7(1) Supply Current Program/ Erase Suspended (Standby) VPPF Supply Current (Program) IPP1(1) VPPF Supply Current (Erase) IPP2 IPP3(1) Note: 1. Sampled only, not 100% tested. 2. VDDF Dual Operation current is the sum of read and program or erase currents. 13/18 M36L0R7040T0, M36L0R7040B0 Table 7. Flash Memory DC Characteristics - Voltages Symbol Parameter Test Condition Min Typ Max Unit VIL Input Low Voltage –0.5 0.4 V VIH Input High Voltage VDDQ –0.4 VDDQ + 0.4 V VOL Output Low Voltage IOL = 100µA 0.1 V VOH Output High Voltage IOH = –100µA VDDQ –0.1 VPP1 VPPF Program Voltage-Logic Program, Erase 1.1 1.8 3.3 V Program, Erase 8.5 9.0 12.6 V 0.4 V VPPF Program Voltage Factory VPPH VPPLK Program or Erase Lockout VLKO VDDF Lock Voltage VRPH RPF pin Extended High Voltage V 1 V 3.3 V Table 8. PSRAM DC Characteristics Symbol Parameter ICC1 VCC Active Current ICC2 ILI Input Leakage Current ILO Output Leakage Current IPD Deep Power Down Current ISB Standby Supply Current CMOS Test Condition VDDP = 1.95V, VIN = VIH or VIL, E1P = VIL and E2P = VIH, IOUT = 0mA Min Max Unit tAVAV Read / tAVAV Write = minimum 20 mA tAVAV Read / tAVAV Write = maximum 3 mA 0V ≤ VIN ≤ VDDP –1 1 µA 0V ≤ VOUT ≤ VDDP –1 1 µA VDDP = 1.95V, E1P ≥ VDDP – 0.2V or E1P ≤ VIL, VIN ≥ VDDP – 0.2V or VIN ≤ 0.2V 10 µA VDDP = 1.95V, E1P = E2P ≥ VDDP – 0.2V, IOUT = 0mA 110 µA VIH (1) Input High Voltage 0.8VDDP VDDP + 0.2 V VIL (2) Input Low Voltage –0.3 0.4 V VOH Output High Voltage IOH = –0.5mA VOL Output Low Voltage IOL = 1mA Note: 1. 2. 3. 4. 14/18 VDDP – 0.2 Average AC current, cycling at tAVAV minimum. E1P = VIL, E2P = VIH, UBP OR/AND LBP = VIL, VIN = VIH OR VIL. E1P ≤ 0.2V or E2P ≥ VDDQ –0.2V, UBP OR/AND LBP ≤ 0.2V, VIN ≤ 0.2V or VIN ≥ VDDQ –0.2V. Output disabled. V 0.2 V M36L0R7040T0, M36L0R7040B0 PACKAGE MECHANICAL Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline D D1 e SE E E2 E1 b BALL "A1" ddd FE FE1 FD SD A2 A A1 BGA-Z42 Note: Drawing is not to scale. Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 A1 Max 0.0472 0.200 0.0079 A2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 5.600 0.2205 ddd 0.100 9.900 E 10.000 E1 7.200 0.2835 E2 8.800 0.3465 e 0.800 FD 1.200 0.0472 FE 1.400 0.0551 FE1 0.600 0.0236 SD 0.400 0.0157 SE 0.400 0.0157 – 10.100 0.0039 – 0.3937 0.0315 0.3898 0.3976 – – 15/18 M36L0R7040T0, M36L0R7040B0 PART NUMBERING Table 10. Ordering Information Scheme Example: M36 L 0 R 7 0 4 0 T 0 ZAQ T Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture 0 = No Die Operating Voltage R = VDDF = VDDP = VDDQ = 1.7 to 1.95V Flash 1 Density 7 = 128 Mbit Flash 2 Density 0 = No Die RAM 1 Density 4 = 16 Mbit RAM 0 Density 0 = No Die Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 0 = 0.13µm Flash technology, 85ns speeds; 0.18µm RAM, 70ns speed Package ZAQ = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-free and RoHS package, standard packing F= Lead-free and RoHS package, tape and reel packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 16/18 M36L0R7040T0, M36L0R7040B0 REVISION HISTORY Table 11. Document Revision History Date Version 19-Nov-2003 1.0 First Issue 2.0 TFBGA88 package specifications updated. TFBGA88 package fully compliant with the ST ECOPACK specification. Flash memory and PSRAM data updated to revision 1.0 of M30L0R7000x0 datasheet and revision 6.0 of M69AR024B datasheet. Document status promoted from Target Specification to full Datasheet. 06-Dec-2004 Revision Details 17/18 M36L0R7040T0, M36L0R7040B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 18/18