M36L0R8060T1 M36L0R8060B1 256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package FEATURES SUMMARY MULTI-CHIP PACKAGE – 1 die of 256 Mbit (16Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory – 1 die of 64 Mbit (4Mb x16) Pseudo SRAM ■ SUPPLY VOLTAGE – VDDF = VCCP = VDDQF = 1.7 to 1.95V – VPPF = 9V for fast program (12V tolerant) ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code M36L0R8060T1: 880Dh – Bottom Device Code M36L0R8060B1: 880Eh ■ PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY ■ SYNCHRONOUS / ASYNCHRONOUS READ – Synchronous Burst Read mode: 54MHz – Asynchronous Page Read mode – Random Access: 85ns ■ SYNCHRONOUS BURST READ SUSPEND ■ PROGRAMMING TIME – 10µs typical Word program time using Buffer Enhanced Factory Program command ■ MEMORY ORGANIZATION – Multiple Bank Memory Array: 16 Mbit Banks – Parameter Blocks (Top or Bottom location) ■ DUAL OPERATIONS – program/erase in one Bank while read in others – No delay between read and write operations ■ SECURITY – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ June 2005 Figure 1. Package FBGA TFBGA88 (ZAQ) 8 x 10mm BLOCK LOCKING – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – WPF for Block Lock-Down – Absolute Write Protection with VPPF = VSS ■ COMMON FLASH INTERFACE (CFI) ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK PSRAM ■ ACCESS TIME: 70ns ■ ASYNCHRONOUS PAGE READ – Page Size: 16 words – Subsequent read within page: 20ns ■ LOW POWER FEATURES – Temperature Compensated Refresh (TCR) – Partial Array Refresh (PAR) – Deep Power-Down (DPD) Mode ■ SYNCHRONOUS BURST READ/WRITE ■ 1/18 M36L0R8060T1, M36L0R8060B1 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Flash Memory Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PSRAM Component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....4 .....5 .....6 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Address Inputs (A0-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Chip Enable input (EP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCCP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VDDQF Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/18 M36L0R8060T1, M36L0R8060B1 Table 4. Figure 5. Figure 6. Table 5. Table 6. Table 7. Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. TFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline . . . . 15 Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3/18 M36L0R8060T1, M36L0R8060B1 SUMMARY DESCRIPTION The M36L0R8060T1 and M36L0R8060B1 combine two memory devices in a Multi-Chip Package: ■ a 256-Mbit, Multiple Bank Flash memory, the M30L0R8000T0 or M30L0R8000B0, ■ a 64-Mbit PseudoSRAM, the M69KB096AA. This document should be read in conjunction with the M30L0R8000x0 and M69KB096AA datasheets. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8x10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the package is also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. Flash Memory Component For detailed information on how to use the Flash memory component, refer to the M30L0R8000(T/ B)0 datasheet which is available from your local STMicroelectronics distributor. The memory is supplied with all the bits erased (set to ‘1’). PSRAM Component For detailed information on how to use the PSRAM component, see the M69KB096AA datasheet that is available from your local STMicroelectronics distributor. 4/18 Figure 2. Logic Diagram VDDQF VPPF VDDF VCCP 24 16 A0-A23 DQ0-DQ15 EF GF WAIT WF RPF WPF L M36L0R8060T1 M36L0R8060B1 K EP GP WP CRP UBP LBP VSS AI10533b M36L0R8060T1, M36L0R8060B1 Table 1. Signal Names A0-A23 Address Inputs DQ0-DQ15 Common Data Input/Output L Latch Enable input for Flash memory and PSRAM K Burst Clock for Flash memory and PSRAM WAIT Wait Data in Burst Mode for Flash memory and PSRAM VDDF Flash Memory Power Supply VDDQF Flash Power Supply for I/O Buffers VPPF Flash Optional Supply Voltage for Fast Program & Erase VSS Ground VCCP PSRAM Power Supply NC Not Connected Internally DU Do Not Use as Internally Connected Flash Memory Signals EF Chip Enable input GF Output Enable Input WF Write Enable input RPF Reset input WPF Write Protect input PSRAM Signals EP Chip Enable Input GP Output Enable Input WP Write Enable Input CRP Configuration Register Enable Input UBP Upper Byte Enable Input LBP Lower Byte Enable Input 5/18 M36L0R8060T1, M36L0R8060B1 Figure 3. TFBGA Connections (Top view through package) 1 2 3 4 5 A DU DU B A4 A18 A19 VSS VDDF C A5 LBP A23 VSS D A3 A17 NC E A2 A7 F A1 G 6 7 8 DU DU NC A21 A11 NC K A22 A12 VPPF WP EP A9 A13 NC WPF L A20 A10 A15 A6 UBP RPF WF A8 A14 A16 A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT NC H GP DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC J NC GF DQ9 DQ11 DQ4 DQ6 DQ15 VDDQF K EF DU DU NC VCCP NC VDDQF CRP L VSS VSS VDDQF VDDF VSS VSS VSS VSS M DU DU DU DU AI09313b 6/18 M36L0R8060T1, M36L0R8060B1 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A23). Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. The other lines (A23-A22) are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable signal (W F), while the PSRAM is accessed through the Chip Enable signal (EP) and the Write Enable signal (WP). Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UBP) is driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the selected address when Lower Byte Enable (LBP) is driven Low. When both UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance. Latch Enable (L). The Latch Enable pin is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KB096AA for the PSRAM and M30L0R8000T/B0 for the Flash memory. Clock (K). The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AA for the PSRAM and M30L0R8000T/B0 for the Flash memory. Wait (WAIT). WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how it behaves, please refer to the M69KB096AA datasheet for the PSRAM and to the M30L0R8000T/B0 datasheet for the Flash memory. Flash Chip Enable (EF). The Flash Chip Enable input activates the control logic, input buffers, de- coders and sense amplifiers of the Flash memory component. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable pin controls the data outputs during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R8000T0/B0 datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 6., Flash Memory DC Characteristics Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 7., Flash Memory DC Characteristics - Voltages). PSRAM Chip Enable input (EP). The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode. PSRAM Write Enable (WP). Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. Enable, PSRAM Output Enable (GP). Output GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. 7/18 M36L0R8060T1, M36L0R8060B1 PSRAM Upper Byte Enable (UB P). The Upper Byte En-able, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. PSRAM Lower Byte Enable (LBP). The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LBP and UBP are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low. PSRAM Configuration Register Enable (CR P). When this signal is driven High, VIH, Write operations load either the value of the Refresh Configuration Register (RCR) or the Bus configuration register (BCR). VDDF Supply Voltage. VDDF provides the power supply to the internal core of the Flash memory. It is the main power supply for all Flash memory operations (Read, Program and Erase). VCCP Supply Voltage. VCCP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM operations. VDDQF Supply Voltage. VDDQF provides the power supply for the Flash I/O pins. This allows all Outputs to be powered independently of the Flash core power supplies, VDDF and VCCP. 8/18 VPPF Program Supply Voltage. VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against Program or Erase, while VPPF > VPP1 enables these functions (see Tables 6 and 7, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in a system should have their supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 6., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents. M36L0R8060T1, M36L0R8060B1 FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: EF for the Flash memory and EP for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations on one of the Flash memory and the PSRAM components which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 4. Functional Block Diagram A22-A23 EF WF RPF WPF 256 Mbit Flash Memory GF WAIT VDDF VDDQF VPPF K L VCCP A0-A21 VSS DQ0-DQ15 EP GP WP 64 Mbit PSRAM CRP UBP LBP AI09314b 9/18 M36L0R8060T1, M36L0R8060B1 Table 2. Main Operating Modes WAITF(4) EF GF WF LF RPF Flash Read VIL VIL VIH VIL(2) VIH Flash Write VIL VIH VIL VIL(2) VIH Flash Address Latch VIL X VIH VIL VIH Flash Data Out or Hi-Z (3) Flash Output Disable VIL VIH VIH X VIH Hi-Z Flash Standby VIH X X X VIH Hi-Z X X X X VIL Hi-Z Operation Flash Reset PSRAM Standby GP WP LBP,UBP DQ15-DQ0 Flash Data In PSRAM must be disabled. The Flash memory must be disabled PSRAM Write Configuration Register CRP Flash Data Out PSRAM Read PSRAM Write EP Any PSRAM mode is allowed. Hi-Z Hi-Z VIL VIL VIL VIH VIL PSRAM data out VIL VIL X VIL VIL PSRAM data in VIL VIH VIH VIL X PSRAM data in VIH VIL X X X Hi-Z VIH X X X X Hi-Z Any Flash mode is allowed. PSRAM Deep Power-Down Note: 1. 2. 3. 4. 10/18 X = Don't care. LF can be tied to VIH if the valid address has been previously latched. Depends on GF. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R8000T0 datasheet for details. M36L0R8060T1, M36L0R8060B1 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute Maximum Ratings Value Symbol Parameter Unit Min Max Ambient Operating Temperature –25 85 °C TBIAS Temperature Under Bias –25 85 °C TSTG Storage Temperature –65 125 °C TLEAD Lead Temperature During Soldering (1) °C TA VIO VDDF, VDDQF, VCCP VPPF IO tVPPFH Input or Output Voltage –0.5 VDDQ + 0.3 V Core and Input/Output Supply Voltages –0.2 2.45 V Flash Program Voltage –0.2 12.6 V Output Short Circuit Current 100 mA Time for VPPF at VPPFH 100 hours Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 11/18 M36L0R8060T1, M36L0R8060B1 DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC Measurement Conditions Flash Memory PSRAM Parameter Unit Min Max Min Max VDDF Supply Voltage 1.7 1.95 – – V VCCP Supply Voltage – – 1.7 1.95 V VDDQF Supply Voltage 1.7 1.95 – – V VPPF Supply Voltage (Factory environment) 8.5 9.5 – – V VPPF Supply Voltage (Application –0.4 VDDQF +0.4 – – V –25 85 –25 85 °C environment) Ambient Operating Temperature Load Capacitance (CL) Output Circuit Resistors (R1, R2) 30 30 pF 16.7 16.7 kΩ Input Rise and Fall Times 5 Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 5. AC Measurement I/O Waveform ns 0 to VDDQF 0 to VDDQF V VDDQF/2 VDDQF/2 V Figure 6. AC Measurement Load Circuit VDDQF VDDQF VDDF VDDQF/2 VDDQF R1 0V DEVICE UNDER TEST AI06161b CL 0.1µF R2 0.1µF CL includes JIG capacitance AI08364c Table 5. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Note: Sampled only, not 100% tested. 12/18 Test Condition Min Max Unit VIN = 0V 14 pF VOUT = 0V 18 pF M36L0R8060T1, M36L0R8060B1 Table 6. Flash Memory DC Characteristics - Currents Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current Supply Current Asynchronous Read (f=5MHz) IDD1 Test Condition Typ Max Unit 0V ≤ VIN ≤ VDDQF ±1 µA 0V ≤ VOUT ≤ VDDQF ±1 µA E = VIL, G = VIH 13 15 mA 4 Word 16 18 mA 8 Word 18 20 mA 16 Word 23 25 mA Continuous 25 27 mA RP = VSS ± 0.2V 50 110 µA E = VDDQF ± 0.2V K=Vss 50 110 µA E = VIL, G = VIH 50 110 µA VPP = VPPH 8 20 mA VPP = VDD 10 25 mA VPP = VPPH 8 20 mA VPP = VDD 10 25 mA Program/Erase in one Bank, Asynchronous Read in another Bank 23 40 mA Program/Erase in one Bank, Synchronous Read (Continuous f=54MHz) in another Bank 35 52 mA E = VDDQF ± 0.2V K=Vss 50 110 µA VPP = VPPH 2 5 mA VPP = VDD 0.2 5 µA VPP = VPPH 2 5 mA VPP = VDD 0.2 5 µA VPP Supply Current (Read) VPP ≤ VDD 0.2 5 µA VPP Supply Current (Standby) VPP ≤ VDD 0.2 5 µA Supply Current Synchronous Read (f=54MHz) IDD2 Supply Current (Reset) IDD3 Supply Current (Standby) IDD4 Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) Supply Current IDD6 (1,2) (Dual Operations) IDD7(1) Supply Current Program/ Erase Suspended (Standby) VPP Supply Current (Program) IPP1(1) VPP Supply Current (Erase) IPP2 IPP3(1) Note: 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents. 13/18 M36L0R8060T1, M36L0R8060B1 Table 7. Flash Memory DC Characteristics - Voltages Symbol Parameter Test Condition Min Typ Max Unit VIL Input Low Voltage 0 0.4 V VIH Input High Voltage VDDQF – VDDQF + 0.4 0.4 V VOL Output Low Voltage IOL = 100µA VOH Output High Voltage IOH = –100µA VPP1 VPP Program Voltage-Logic Program, Erase 1.3 1.8 3.3 V VPPH VPP Program Voltage Factory Program, Erase 8.5 9.0 9.5 V VPPLK Program or Erase Lockout 0.4 V VLKO VDD Lock Voltage 1 V VRPH RP pin Extended High Voltage 3.3 V 0.1 V VDDQF – V 0.1 Table 8. PSRAM DC Characteristics Symbol Parameter ICC1 (1) Operating Current: Asynchronous Random Read/Write ICC1P (1) Operating Current: Asynchronous Page Read ICC2 (1) Operating Current: Initial Access, Burst Read/Write Test Condition VCC =VIH or VIL, E = VIL, IOUT = 0mA Min. Typ Max. Unit 70ns 25 mA 70ns 15 mA 80MHz 35 mA 66MHz 30 mA ICC3R(1) Operating Current: Continuous Burst Read 80MHz 18 mA 66MHz 15 mA ICC3W(1) Operating Current: Continuous Burst Write 80MHz 35 mA 66MHz 30 mA VCC = VCCQ or 0V, E = VIH 120 µA 0V ≤ VIN ≤ VCC 1 µA G = VIH or E = VIH 1 µA ISB(2) VCC Standby Current ILI Input Leakage Current ILO Output Leakage Current IZZ Deep-Power Down Current VIH Input High Voltage 1.4 VCCQ + 0.2 V VIL Input Low Voltage −0.2 0.4 V VOH Output High Voltage IOH = −0.2mA VOL Output Low Voltage IOL = 0.2mA 10 VIN = VIH or VIL µA 0.8VCCQ V 0.2VCCQ V Note: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive the output capacitance expected in the actual system. 2. ISB(Max) values are measured with RCR2 to RCR0 bits set to ‘000’ (full array refresh) and RCR6 to RCR5 bits set to ‘11’ (temperature compensated refresh threshold at +85°C). In order to achieve low standby current, all inputs must be driven either to VCCQ or VSS. 3. The Operating Temperature is +25°C. 14/18 M36L0R8060T1, M36L0R8060B1 PACKAGE MECHANICAL Figure 7. TFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline D D1 e SE E E2 E1 b BALL "A1" ddd FE FE1 SD FD A2 A A1 BGA-Z42 Note: Drawing is not to scale. Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 A1 Max 0.0472 0.200 0.0079 A2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 5.600 0.2205 ddd 0.100 9.900 E 10.000 E1 7.200 0.2835 E2 8.800 0.3465 e 0.800 FD 1.200 0.0472 FE 1.400 0.0551 FE1 0.600 0.0236 SD 0.400 0.0157 SE 0.400 0.0157 – 10.100 0.0039 – 0.3937 0.0315 0.3898 0.3976 – – 15/18 M36L0R8060T1, M36L0R8060B1 PART NUMBERING Table 10. Ordering Information Scheme Example: M36 L 0 R 8 0 6 0 T 1 ZAQ T Device Type M36 = Multi-Chip Package (Multiple Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture 0 = No Die Operating Voltage R = VDDF = VCCP = VDDQF = 1.7 to 1.95V Flash 1 Density 8 = 256 Mbits Flash 2 Density 0 = No Die RAM 1 Density 6 = 64 Mbits RAM 0 Density 0 = No Die Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 1 = 0.13µm Flash Technology Multi-Level Design, 85ns speed; 0.11µm PSRAM, 70ns speed, burst mode Package ZAQ = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-free and RoHS Standard packing F = Lead-free and RoHS Tape & Reel packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 16/18 M36L0R8060T1, M36L0R8060B1 REVISION HISTORY Table 11. Document Revision History Date Version Revision Details 15-Oct-2004 0.1 First Issue 29-Apr-2004 0.2 Part Number M69KB096A changed to M69KB096AA throughout document. 24-June-2005 0.3 Status changed from Preliminary to Full Datasheet. Table 6., Table 7. and Table 8. modified. Signal changed from VDDQ to VDDQF throughout the document. 17/18 M36L0R8060T1, M36L0R8060B1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 18/18