88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Features Parallel NOR and PSRAM 88-Ball MCP Combination Memory MT38L3021A902ZQXZI.X79 Features Figure 1: MCP Block Diagram • Micron® Parallel NOR Flash and PSRAM components • RoHS-compliant, “green” package • Space-saving multichip package (MCP) • Low-voltage operation (1.70–1.95V) • Industrial temperature range: –40°C to +85°C NOR Flash Power NOR Flash Device NOR Flash-Specific Features • Multiple-bank, Parallel NOR Flash memory • Synchronous/asynchronous read – Synchronous burst read mode: 66 MHz – Random access times: 70ns – Asynchronous page read mode: 20ns • Programming times – 2.5μs typical word program time using buffer enhanced factory program command – Fast program with 9V V PP • Memory blocks – Multiple bank memory array: 8Mb banks – Top or bottom location parameter blocks1 • Dual operations – Program erase in 1 bank, read in others – No delay between READ and WRITE operations • Block locking – All blocks locked at power-up – Any combination of blocks can be locked – WP# for block lock-down • Security – 2112-bit user programmable OTP cells – 64-bit unique device number • Common Flash interface • 100,000 PROGRAM/ERASE cycles per block • Electronic signature – Manufacturer code: 20h – 128Mb Flash code: 88C4h (top boot) PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN PSRAM Power PSRAM Device PSRAM-Specific Features • Synchronous/asynchronous read – Synchronous burst read mode: 80 MHz – Random access times: 70ns – Asynchronous page read mode: 20ns • Partial-array self refresh (PAR) • Deep power-down (DPD) mode • Automatic temperature-compensated self-refresh (TCR) Notes: 1 1. Contact factory for availability of version. 2. For physical part markings, see Part Numbering Information (page 2). Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Features Part Numbering Information Micron NOR MCP devices are available in different configurations and densities. The NOR MCP part numbering system is available at www.micron.com/numbering. Figure 2: Part Number Chart MT 38X XXX X X X X X XXX X X . XXX -XX Micron Technology Production Status Product Family Die Revision Code Density Operating Temperature Range Voltage Range (Core I/O) Special Option Die Count Package Code NOR Configuration xPSRAM Description xNAND Description Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/ Label,” at www.micron.com/csn. PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM MCP General Description MCP General Description Micron MCP products combine NOR Flash and PSRAM devices in a single MCP. Operational characteristics for the NOR Flash and PSRAM devices are found in the standard data sheets for each of the discrete devices. Recommended operating conditions do not allow more than one device to be active at a time. A common example of this scenario is running simultaneous READ operations on the NOR device and on the PSRAM device. Doing this results in data bus contention. To prevent this, one device must be High-Z when reading the selected device. NOR Flash device is the with M58LR128KT. For device specifications and complete Micron NOR Flash features documentation, contact your local Micron sales office. PSRAM device is the W965D6G. For device specifications and complete PSRAM features documentation, contact your local Micron sales office. PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 3: 88-Ball TFBGA (NOR x16; PSRAM x16) Ball Assignments 1 2 DNU DNU A4 A18 A19 VSS VDDF A5 LB# A23 VSS A3 A17 NC A2 A7 A1 3 4 5 6 7 8 A DNU DNU NC A21 A11 NC CLK A22 A12 VPP WE# CE# A9 A13 NC WP# ADV# A20 A10 A15 A6 UB# RP# WE# A8 A14 A16 A0 DQ8 DQ2 DQ10 DQ5 OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC OE# DQ9 DQ11 DQ4 DQ6 DQ15 VDDQF CE# DNU DNU NC VDDP NC VDDQF CRE VSS VSS VSS VSS VSS VSS DNU DNU DNU DNU B C D E F G DQ13 WAIT NC H NC J K L VDDQF VDDF M Flash Notes: PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN PSRAM 1. A23 is valid for 256Mb and above; otherwise, it is RFU. 2. A22 is valid for 128Mb and above; otherwise, it is RFU. 3. A21 is valid for 64Mb and above; otherwise, it is RFU. 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Ball Assignments and Descriptions Table 1: x16 NOR Ball Descriptions Symbol Alternate Symbol Type CE# E# Input Chip enable: Activates the memory control logics, input buffers, decoders, and sense amplifiers. When CE# is LOW and RESET is HIGH, the device is in active mode. When HIGH, the NOR device is deselected, the outputs are High-Z, and the power consumption is reduced to the standby level. OE# G# Input Output enable: Controls data outputs during NOR bus READ operations. WE# W# Input Write enable: Controls the bus WRITE operation of the NOR command interface. The data and address inputs are latched on the rising edge of CE# or WE#, whichever occurs first. WP# WP# Input Write protect: Provides additional hardware protection for each block. When WP# is LOW, lock-down is enabled and the protection status of the locked-down blocks cannot be changed. When WP# is HIGH, lock-down is disabled and the locked-down blocks can be locked or unlocked. RP# RP# Input Reset: Provides a hardware reset of the memory. When RP# is LOW, the device is in reset mode; the outputs are High-Z and the current consumption is reduced to IDD2. After RP#, all blocks are in the locked state and the configuration register is reset. When RP# is HIGH, the device is in normal operation. Upon exiting reset mode, the device enters asynchronous read mode, but a negative transition of CE# or L# is required to ensure valid data outputs. VPP Supply Both a NOR control input and power supply pin. The two functions are selected by the voltage range applied to the pin. When VPP = 0V - VDDQF, it functions as a control input. In this case, a voltage lower than VPPLKF provides absolute protection against program or erase, while VPP > VPP1F enables these functions. VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect, and PROGRAM or ERASE operations continue. When VPP is in the range of VPPH, it acts as a power supply pin. In this condition, VPP must be stable until the program/erase algorithm is completed. VDDF Supply Flash core power supply VDDQF Supply Flash I/O power supply PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN Description 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Ball Assignments and Descriptions Table 2: x16 PSRAM Ball Descriptions Symbol Alternate Symbol Type CE# E# Input Chip enable: When LOW, CE# activates the memory state machine, Iaddress buffers and decoders, enabling READ and WRITE operations. When HIGH, all other pins are ignored and the device is automatically put in low-power standby mode. OE# G# Input Output enable: Provides high-speed, tri-state control, enabling fast READ and WRITE cycles to be achieved with the common I/O data bus. WE# W# Input Write enable: Controls the bus WRITE operation. CRE CR Input Configuration register enable: When HIGH, bus READ or WRITE operations access either the value of the refresh configuration register or the bus configuration register, according to the value of A19. UB# Input Upper byte enable: Gates the data on the upper byte data I/Os (DQ[15:8]) to or from the upper part of the selected address during a WRITE or READ operation. LB# Input Lower byte enable: Gates the data on the lower byte data I/Os (DQ[7:0]) to or from the lower part of the selected address during a WRITE or READ operation. VDDP Supply Description PSRAM power supply. Table 3: NOR/PSRAM Shared Ball Descriptions Symbol Type Description A[MAX:0] Input Address: Select the cells in the memory array to access during bus READ operations. During bus WRITE operations they control the commands sent to the command interface of NOR memory program/erase controller, and they select the cells to access in the PSRAM. DQ[15:0] Input/ Output Data inputs/outputs: The bidirectional I/Os output the data stored at the selected address during a NOR bus READ operation or inputs a command or the data to be programmed during a bus WRITE operation. The upper byte data inputs/outputs carry the data to or from the upper part of the selected address during a PSRAM WRITE or READ operation, when UB# is driven LOW. Likewise, the lower byte data I/Os carry the data to or from the lower part of the selected address during a WRITE or READ operation, when LB# is driven LOW. CLK Input Clock ADV# Input Latch enable input WAIT Output Symbol Type VSS Supply Symbol Type NC – Not connected. DNU – Do not use. PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN WAIT data in burst mode Description Shared ground. Description 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 4: Absolute Maximum Ratings Parameters/Conditions Symbol Min Max Unit TA –40 85 °C TBIAS –40 85 °C TSTG –55 125 °C Ambient operating temperature Storage temperature range Input voltage VIN –0.2 2.45 V PSRAM core & I/O supply voltage VDDP –0.2 2.45 V Flash core supply voltage VDDF –0.2 2.45 V Flash I/O supply voltage VDDQF –0.2 2.45 V VPP –0.2 10 V IO – 100 mA tVPPH – 100 hours Flash VPP program voltage Output short circuit current Time for VPP at VPPH Table 5: Recommended Operating Conditions Parameters Symbol Min Max Unit PSRAM core & I/O supply voltage VDDP 1.70 1.95 V Flash core supply voltage VDDF 1.70 1.95 V Flash I/O supply voltage VDDQF 1.70 1.95 V Flash VPP supply voltage (application environment) VPP –0.4 VDDQF + 0.4 V Flash VPP supply voltage (factory environment) VPP 8.5 9.5 V – –40 +85 °C Operating temperature range PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Electrical Specifications Table 6: Operating Modes – Standard Asynchronous Operation X = "Don't Care" Flash Operation RP# CE# OE# PSRAM WE# CE# OE# WE# Shared CRE UB# LB# ADV# CLK1 ADQ[15:0] WAIT2 Flash READ VIH VIL VIL VIH VIH X X X X X VIH VIL Address in/ data out Low-Z WRITE VIH VIL VIH VIL VIH X X X X X VIH VIL Address in/ data in Low-Z ADDRESS LATCH VIH VIL VIH X VIH X X X X X VIL VIL Data out or High-Z3 Low-Z OUTPUT DISABLE VIH VIL VIH VIH VIH X X X X X VIH VIL High-Z Low-Z STANDBY VIH VIH X X X VIL High-Z High-Z RESET VIL X X X X VIL High-Z High-Z READ X VIH X X VIL VIL VIH VIL VIL VIL \_/ VIL Address in/ data out Low-Z WRITE X VIH X X VIL VIH VIL VIL VIL VIL \_/ VIL Address in/ data in High-Z READ CONFIGURATION REGISTER (CRE controlled) X VIH X X VIL VIL VIH VIH VIL VIL \_/ VIL Address in/ Low-Z BCR, RCR, or DIDR content SET CONFIGURATION REGISTER (CRE controlled)4 X VIH X X VIL VIH VIL VIH X X \_/ VIL BCR/RCR data Low-Z OUTPUT DISABLE (No operation) X VIH X X VIL VIH X VIL X X X X High-Z Low-Z VIH X X X X X X VIL High-Z High-Z VIH X X X X X X VIL High-Z High-Z Any PSRAM mode allowed PSRAM DEEP POWER DOWN5 Any Flash mode allowed STANDBY Notes: PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN 1. CLK must remain LOW when the PSRAM device is operating in asynchronous mode. 2. For the Flash device, WAIT polarity is configured using the SET CONFIGURATION REGISTER command. 3. See the NOR data sheet for more information. 4. BCR and RCR only. 5. The device enters deep power-down mode by driving the CE# from LOW to HIGH, with bit 4 of the RCR set to 0. The device remains in deep power-down mode until CE# goes LOW again and is held LOW for tDPDX. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Device Diagrams Device Diagrams Figure 4: 88-Ball Functional Block Diagram (NOR with PSRAM) VPP VDDQF VDDF OE# CE# WE# WP# A[MAX:0] NOR Flash DQ[15:0] RP# ADV# CLK VDDP CE# OE# WE# CRE UB# LB# WAIT PSRAM VSS PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Package Dimensions Package Dimensions Figure 5: 88-Ball TFBGA (Package Code: ZQ) Seating plane A 0.1 A 88X Ø0.375 ±0.05 Ball A1 ID 8 7 6 5 4 3 2 Ball A1 ID 1 A B C D E F 10 ±0.1 G 8.8 CTR H 0.8 TYP J K L M 0.8 TYP 5.6 CTR 1.2 MAX 0.2 MIN 8 ±0.1 Note: PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN 1. All dimensions are in millimeters. 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 88-Ball MCP: 128Mb Parallel NOR and 32Mb PSRAM Revision History Revision History Rev. B – 11/14 • Production Rev. A – 08/14 • Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef85e32e5d 88b_nor_psram_jx79.pdf - Rev. B 11/14 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.