MICROCHIP 24AA256

24AA256/24LC256/24FC256
256K I2C™ CMOS Serial EEPROM
Device Selection Table
Description:
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA256
1.8-5.5V
400 kHz(1)
I
24LC256
2.5-5.5V
400 kHz
I, E
24FC256
1.8-5.5V
1 MHz(2)
I
Note 1:
2:
The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device also has a page write capability of up to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 2 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIC, TSSOP, MSOP and DFN packages.
100 kHz for VCC < 2.5V.
400 kHz for VCC < 2.5V.
Features:
• Low-power CMOS technology:
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 μA at 5.5V
- Standby current 100 nA, typical at 5.5V
• 2-wire serial interface bus, I2C™ compatible
• Cascadable for up to eight devices
• Self-timed erase/write cycle
• 64-byte Page Write mode available
• 5 ms max. write cycle time
• Hardware write-protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt Trigger inputs for noise suppression
• 1,000,000 erase/write cycles
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP, SOIC, TSSOP, MSOP and DFN
packages, 14-lead TSSOP package
• Pb-free finishes available
• Temperature ranges:
- Industrial (I):
-40°C to +85°C
- Automotive (E):
-40°C to +125°C
Block Diagram
A0 A1A2 WP
I/O
Control
Logic
HV Generator
Memory
Control
Logic
EEPROM
Array
XDEC
Page Latches
I/O
SCL
YDEC
SDA
VCC
Sense Amp.
R/W Control
VSS
Package Types
A1
2
A2
VSS
3
4
8
VCC
7
WP
6
5
SCL
SDA
A0
1
A1
2
A2
VSS
3
4
8
7
6
5
DFN
VCC
A0
1
WP
A1
2
A2
3
VSS
4
SCL
8 VCC
24XX256
1
TSSOP/MSOP*
24XX256
A0
24XX256
PDIP/SOIC
7 WP
6 SCL
5 SDA
SDA
Note: * Pins A0 and A1 are no connects for the MSOP package only.
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
© 2005 Microchip Technology Inc.
DS21203N-page 1
24AA256/24LC256/24FC256
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Electrical Characteristics:
Industrial (I):
VCC = +1.8V to 5.5V
Automotive (E): VCC = +2.5V to 5.5V
Min.
Max.
Units
—
—
—
TA = -40°C to +85°C
TA = -40°C to +125°C
Conditions
D1
—
A0, A1, A2, SCL, SDA
and WP pins:
—
D2
VIH
High-level input voltage
0.7 VCC
—
V
—
D3
VIL
Low-level input voltage
—
0.3 VCC
0.2 VCC
V
V
VCC ≥ 2.5V
VCC < 2.5V
D4
VHYS
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC
—
V
VCC ≥ 2.5V (Note)
D5
VOL
Low-level output voltage
—
0.40
V
IOL = 3.0 ma @ VCC = 4.5V
IOL = 2.1 ma @ VCC = 2.5V
D6
ILI
Input leakage current
—
±1
μA
VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D7
ILO
Output leakage current
—
±1
μA
VOUT = VSS or VCC
D8
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D9
ICC Read Operating current
—
400
μA
VCC = 5.5V, SCL = 400 kHz
ICC Write
—
3
mA
VCC = 5.5V
—
1
μA
TA = -40°C to +85°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
—
5
μA
TA = -40°C to +125°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
D10
Note:
ICCS
Standby current
This parameter is periodically sampled and not 100% tested.
DS21203N-page 2
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.8V to 5.5V
Automotive (E): VCC = +2.5V to 5.5V
AC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
TA = -40°C to +85°C
TA = -40°C to +125°C
Conditions
1
FCLK
Clock frequency
—
—
—
—
100
400
400
1000
kHz
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V 24FC256
2.5V ≤ VCC ≤ 5.5V 24FC256
2
THIGH
Clock high time
4000
600
600
500
—
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V 24FC256
2.5V ≤ VCC ≤ 5.5V 24FC256
3
TLOW
Clock low time
4700
1300
1300
500
—
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V 24FC256
2.5V ≤ VCC ≤ 5.5V 24FC256
4
TR
SDA and SCL rise time
(Note 1)
—
—
—
1000
300
300
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V 24FC256
5
TF
SDA and SCL fall time
(Note 1)
—
—
300
100
ns
All except, 24FC256
1.8V ≤ VCC ≤ 5.5V 24FC256
6
THD:STA Start condition hold time
4000
600
600
250
—
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V 24FC256
2.5V ≤ VCC ≤ 5.5V 24FC256
7
TSU:STA Start condition setup time
4700
600
600
250
—
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V 24FC256
2.5V ≤ VCC ≤ 5.5V 24FC256
8
THD:DAT Data input hold time
0
—
ns
(Note 2)
9
TSU:DAT Data input setup time
250
100
100
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V 24FC256
10
TSU:STO Stop condition setup time
4000
600
600
250
—
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V 24FC256
2.5V ≤ VCC ≤ 5.5V 24FC256
11
TSU:WP
WP setup time
4000
600
600
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V 24FC256
12
THD:WP
WP hold time
4700
1300
1300
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V 24FC256
Note 1:
2:
3:
4:
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
© 2005 Microchip Technology Inc.
DS21203N-page 3
24AA256/24LC256/24FC256
Electrical Characteristics:
Industrial (I):
VCC = +1.8V to 5.5V
Automotive (E): VCC = +2.5V to 5.5V
AC CHARACTERISTICS (Continued)
Param.
No.
Sym.
Characteristic
TA = -40°C to +85°C
TA = -40°C to +125°C
Min.
Max.
Units
Conditions
—
—
—
—
3500
900
900
400
ns
1.8 V ≤ VCC < 2.5V
2.5 V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V 24FC256
2.5 V ≤ VCC ≤ 5.5V 24FC256
4700
1300
1300
500
—
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V 24FC256
2.5V ≤ VCC ≤ 5.5V 24FC256
10 + 0.1CB
250
250
ns
All except, 24FC256 (Note 1)
13
TAA
Output valid from clock
(Note 2)
14
TBUF
Bus free time: Time the bus
must be free before a new
transmission can start
15
TOF
Output fall time from VIH
minimum to VIL maximum
CB ≤ 100 pF
16
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
All except, 24FC256 (Notes 1
and 3)
17
TWC
Write cycle time (byte or
page)
—
5
ms
—
18
—
Endurance
1,000,000
—
Note 1:
2:
3:
4:
cycles 25°C (Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
5
SCL
7
SDA
IN
3
4
D4
2
8
10
9
6
16
14
13
SDA
OUT
WP
DS21203N-page 4
(protected)
(unprotected)
11
12
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
8-pin
PDIP
8-pin
SOIC
8-pin
TSSOP
8-pin
MSOP
8-pin
DFN
A0
1
1
1
—
1
User Configurable Chip Select
A1
2
2
2
—
2
User Configurable Chip Select
(NC)
—
—
—
1, 2
—
Not Connected
A2
3
3
3
3
3
User Configurable Chip Select
VSS
4
4
4
4
4
Ground
SDA
5
5
5
5
5
Serial Data
Name
Function
SCL
6
6
6
6
6
Serial Clock
(NC)
—
—
—
—
—
Not Connected
WP
7
7
7
7
7
Write-Protect Input
VCC
8
8
8
8
8
+1.8V to 5.5V (24AA256)
+2.5V to 5.5V (24LC256)
+1.8V to 5.5V (24FC256)
2.1
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
For the MSOP package only, pins A0 and A1 are not
connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz and 1 MHz).
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4
Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
3.0
FUNCTIONAL DESCRIPTION
The 24XX256 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX256 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
© 2005 Microchip Technology Inc.
DS21203N-page 5
24AA256/24LC256/24FC256
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high, determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
DS21203N-page 6
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
Note:
The 24XX256 does not generate any
Acknowledge
bits
if
an
internal
programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX256) will leave the data line high to enable
the master to generate the Stop condition.
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
FIGURE 4-1:
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
FIGURE 4-2:
Data
Allowed
to Change
Stop
Condition
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
SDA
1
2
3
4
5
6
7
Data from transmitter
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
© 2005 Microchip Technology Inc.
8
9
1
2
3
Data from transmitter
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
DS21203N-page 7
24AA256/24LC256/24FC256
5.0
DEVICE ADDRESSING
FIGURE 5-1:
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code. For the
24XX256, this is set as ‘1010’ binary for read and write
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1, A0). The Chip Select bits
allow the use of up to eight 24XX256 devices on the
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address.
For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
Chip Select bits (Figures 5-1 and 5-2) should be set to
‘0’. Only two 24XX256 MSOP packages can be
connected to the same bus.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bits are a
“don’t care.” The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX256 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and appropriate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX256 will select a read or
write operation.
FIGURE 5-2:
0
1
Control
Code
DS21203N-page 8
Read/Write Bit
Chip Select
Bits
Control Code
S
1
0
1
A2
0
A1
A0 R/W ACK
Slave Address
Start Bit
5.1
Acknowledge Bit
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 2 Mbit
by adding up to eight 24XX256 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A15; A1 as address bit A16; and A2
as address bit A17. It is not possible to sequentially
read across device boundaries.
For the MSOP package, up to two 24XX256 devices
can be added for up to 512 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A17. Bits A0 (A15) and A1 (A16) of the
control byte must always be set to a logic ‘0’ for the
MSOP.
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
1
CONTROL BYTE
FORMAT
0
A
2
A
1
Chip
Select
Bits
Address High Byte
A
0 R/W
x
A A A A A
14 13 12 11 10
Address Low Byte
A
9
A
8
A
7
•
•
•
•
•
•
A
0
x = “don’t care” bit
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
6.0
WRITE OPERATIONS
6.1
Byte Write
Upon receipt of each word, the six lower Address
Pointer bits are internally incremented by one. If the
master should transmit more than 64 bytes prior to
generating the Stop condition, the address counter will
roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop
condition is received, an internal write cycle will begin
(Figure 6-2). If an attempt is made to write to the array
with the WP pin held high, the device will acknowledge
the command, but no write cycle will occur, no data will
be written and the device will immediately accept a new
command.
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX256. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX256, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX256 acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX256 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2
6.3
Write-Protection
The WP pin allows the user to write-protect the entire
array (0000-7FFF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is, therefore, necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX256 in much the same
way as in a byte write. The exception is that instead of
generating a Stop condition, the master transmits up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer, and will be written into memory
once the master has transmitted a Stop condition.
FIGURE 6-1:
BYTE WRITE
SDA Line
S
T
A
R
T
Bus Activity
AA
S1 0 10A
2 10 0
Bus Activity
Master
Control
Byte
Bus Activity
Master
SDA Line
Address
Low Byte
S
T
O
P
Data
x
P
A
C
K
x = “don’t care” bit
FIGURE 6-2:
Address
High Byte
A
C
K
A
C
K
A
C
K
PAGE WRITE
S
T
A
R
T
Control
Byte
Address
High Byte
AAA
S10 1 02 1 00
Bus Activity
x = “don’t care” bit
© 2005 Microchip Technology Inc.
Address
Low Byte
Data Byte 0
S
T
O
P
Data Byte 63
P
x
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DS21203N-page 9
24AA256/24LC256/24FC256
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for
flow diagram.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
DS21203N-page 10
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
8.0
READ OPERATION
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX256 as part of a write operation (R/W bit set to
‘0’). Once the word address is sent, the master generates a Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a one.
The 24XX256 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, though it does generate a
Stop condition, which causes the 24XX256 to discontinue transmission (Figure 8-2). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.
Read operations are initiated in much the same way as
write operations, with the exception that the R/W bit of
the control byte is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XX256 contains an address counter that maintains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX256 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX256 discontinues transmission (Figure 8-1).
FIGURE 8-1:
8.3
S
T
A
R
T
SDA Line
S 1 0 1 0 A AA 1
2 1 0
Control
Byte
FIGURE 8-2:
Bus Activity
Master
SDA Line
P
A
C
K
Bus Activity
S
T
O
P
Data
Byte
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX256 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX256 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide sequential reads, the 24XX256 contains an internal Address
Pointer which is incremented by one at the completion
of each operation. This Address Pointer allows the
entire memory contents to be serially read during one
operation. The internal Address Pointer will
automatically roll over from address 7FFF to address
0000 if the master acknowledges the byte received
from the array address 7FFF.
CURRENT ADDRESS
READ
Bus Activity
Master
Random Read
N
O
A
C
K
RANDOM READ
S
T
A
R
T
Control
Byte
Address
High Byte
S1 01 0 AAA0
2 1 0
Control
Byte
S
T
O
P
Data
Byte
S 1 0 1 0 A A A1
2 1 0
x
A
C
K
A
C
K
Bus Activity
S
T
A
R
T
Address
Low Byte
A
C
K
P
N
O
A
C
K
A
C
K
x = “don’t care” bit
FIGURE 8-3:
Bus Activity
Master
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
S
T
O
P
Data (n + x)
Data (n + 2)
P
SDA Line
Bus Activity
© 2005 Microchip Technology Inc.
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
DS21203N-page 11
24AA256/24LC256/24FC256
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
Example:
24AA256
I/P e3 017
0510
XXXXXXXX
T/XXXNNN
YYWW
8-Lead SOIC (150 mil)
XXXXXXXX
T/XXYYWW
NNN
24LC256I
SN e3 0510
017
8-Lead SOIC (208 mil)
XXXXXXXX
T/XXXXXX
YYWWNNN
Legend: XX...X
T
Y
YY
WW
NNN
e3
Example:
Example:
24LC256
I/SM e3
0510017
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For
device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
DS21203N-page 12
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
Package Marking Information (Continued)
Example:
8-Lead TSSOP
XXXX
TYWW
NNN
4LD
I510
017
8-Lead MSOP
Example:
XXXXXT
YWWNNN
4L256I
510017
8-Lead DFN-S
Example:
24LC256
I/MF e3
0510
017
XXXXXXX
T/XXXXX
YYWW
NNN
First Line Marking Codes
TSSOP Package Codes
MSOP Package Codes
4AD
4A256T
Part No.
24AA256
24LC256
4LD
4L256T
24FC256
4FD
4F256T
© 2005 Microchip Technology Inc.
DS21203N-page 13
24AA256/24LC256/24FC256
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21203N-page 14
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
© 2005 Microchip Technology Inc.
DS21203N-page 15
24AA256/24LC256/24FC256
8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)
E
E1
p
D
2
1
n
B
α
c
A2
A
φ
L
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
.070
.069
.002
.300
.201
.202
.020
0
.008
.014
0
0
INCHES*
NOM
8
.050
.075
.074
.005
.313
.208
.205
.025
4
.009
.017
12
12
A1
MAX
.080
.078
.010
.325
.212
.210
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.78
1.97
1.75
1.88
0.05
0.13
7.62
7.95
5.11
5.28
5.13
5.21
0.51
0.64
0
4
0.20
0.23
0.36
0.43
0
12
0
12
MIN
MAX
2.03
1.98
0.25
8.26
5.38
5.33
0.76
8
0.25
0.51
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
Drawing No. C04-056
DS21203N-page 16
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
A2
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
INCHES
NOM
MAX
8
.026
.033
.002
.246
.169
.114
.020
0
.004
.007
0
0
.035
.004
.251
.173
.118
.024
4
.006
.010
5
5
.043
.037
.006
.256
.177
.122
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
8
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
2.90
3.00
3.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
© 2005 Microchip Technology Inc.
DS21203N-page 17
24AA256/24LC256/24FC256
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
n
p
MIN
INCHES
NOM
MAX
MILLIMETERS*
NOM
8
0.65 BSC
0.75
0.85
0.00
4.90 BSC
3.00 BSC
3.00 BSC
0.40
0.60
0.95 REF
0°
0.08
0.22
5°
5°
-
MIN
8
Number of Pins
Pitch
.026 BSC
A
.043
Overall Height
A2
Molded Package Thickness
.030
.033
.037
A1
.000
.006
Standoff
E
Overall Width
.193 TYP.
E1
.118 BSC
Molded Package Width
D
.118 BSC
Overall Length
L
.016
.024
.031
Foot Length
Footprint (Reference)
F
.037 REF
φ
0°
8°
Foot Angle
c
.003
.006
.009
Lead Thickness
B
.009
.012
.016
Lead Width
α
5°
15°
Mold Draft Angle Top
β
5°
15°
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
15°
15°
JEDEC Equivalent: MO-187
Drawing No. C04-111
DS21203N-page 18
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S)
E
p
B
E1
n
L
R
D1
1
D
D2
PIN 1
ID
EXPOSED
METAL
PADS
2
E2
TOP VIEW
BOTTOM VIEW
α
A2
A3
A
A1
INCHES
Units
Dimension Limits
Number of Pins
MIN
MILLIMETERS*
NOM
n
MAX
MIN
NOM
MAX
8
8
Pitch
p
Overall Height
A
.033
.039
0.85
1.00
Molded Package Thickness
A2
.026
.031
0.65
0.80
Standoff
A1
.0004
.002
0.01
0.05
Base Thickness
A3
.008 REF.
0.20 REF.
4.92 BSC
.050 BSC
.000
E
.194 BSC
Molded Package Length
E1
.184 BSC
Exposed Pad Length
E2
Overall Length
Overall Width
.152
D
.158
1.27 BSC
0.00
4.67 BSC
.163
3.85
4.00
4.15
5.99 BSC
.236 BSC
.226 BSC
5.74 BSC
Molded Package Width
D1
Exposed Pad Width
D2
.085
.091
.097
2.16
2.31
2.46
Lead Width
B
.014
.016
.019
0.35
0.40
0.47
Lead Length
L
.020
.024
.030
0.50
0.60
0.75
Tie Bar Width
R
α
Mold Draft Angle Top
.356
.014
12
12
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: pending
Drawing No. C04-113
© 2005 Microchip Technology Inc.
DS21203N-page 19
24AA256/24LC256/24FC256
APPENDIX A:
REVISION HISTORY
Revision L
Corrections to Section 1.0, Electrical Characteristics.
Revision M
Added 1.8V 400 kHz option for 24FC256.
Revision N
Revised Sections 2.1 and 2.4. Removed 14-Lead
TSSOP Package.
DS21203N-page 20
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2005 Microchip Technology Inc.
DS21203N-page 21
24AA256/24LC256/24FC256
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: 24AA256/24LC256/24FC256
Literature Number: DS21203N
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21203N-page 22
© 2005 Microchip Technology Inc.
24AA256/24LC256/24FC256
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
Device
Device:
Temperature
Range
24AA256:
24AA256T:
24LC256:
24LC256T:
24FC256:
24FC256T:
Temperature
Range:
I
E
Package:
P
SN
SM
ST
MF
MS
Lead Finish:
=
=
/XX
X
Package
Lead
Finish
256 Kbit 1.8V I2C Serial
EEPROM
256 Kbit 1.8V I2C Serial
EEPROM Tape and Reel)
256 Kbit 2.5V I2C Serial
EEPROM
256 Kbit 2.5V I2C Serial
EEPROM Tape and Reel)
256 Kbit High Speed I2C Serial
EEPROM
256 Kbit High Speed I2C Serial
EEPROM Tape and Reel)
-40°C to +85°C
-40°C to +125°C
=
=
=
=
=
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
Plastic SOIC (208 mil body), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
Dual, Flat, No Lead (DFN)(6x5 mm
body), 8-lead
= Plastic Micro Small Outline (MSOP),
8-lead
Examples:
a)
24AA256-I/P:
Industrial Temp.,
1.8V, PDIP package.
b)
24AA256T-I/SN: Tape and Reel,
Industrial Temp., 1.8V, SOIC
package.
c)
24AA256-I/ST:
Industrial Temp.,
1.8V, TSSOP package.
d)
24AA256-I/MS: Industrial Temp.,
1.8V, MSOP package.
e)
24LC256-E/P:
Extended Temp.,
2.5V, PDIP package.
f)
24LC256-I/SN: Industrial Temp.,
2.5V, SOIC package.
g)
24LC256T-I/SN: Tape and Reel,
Industrial Temp., 2.5V, SOIC
package.
h)
24LC256-I/MS: Industrial Temp,
2.5V, MSOP package.
i)
24FC256-I/P:
Industrial Temp,
1.8V, High Speed, PDIP package.
j)
24FC256-I/SN: Industrial Temp,
1.8V, High Speed, SOIC package.
k)
24FC256T-I/SN: Tape and Reel,
Industrial Temp, 1.8V, High Speed,
SOIC package
l)
24LC256T-I/STG: Industrial Temp,
2.5V, TSSOP package, Tape & Reel,
Pb-free
Blank= Pb-free – Matte Tin (see Note 1)
G
= Pb-free – Matte Tin only
m) 24LC256-I/PG: Industrial Temp,
2.5V, PDIP package, Pb-free
Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products
manufactured before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb). Please
visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences
and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of
the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
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© 2005 Microchip Technology Inc.
DS21203N-page 23
24AA256/24LC256/24FC256
NOTES:
DS21203N-page 24
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,
Smart Serial, SmartTel, Total Endurance and WiperLock are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21203N-page 25
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DS21203N-page 26
© 2005 Microchip Technology Inc.