MITSUBISHI LSIs revision-01, ' 98.12.08 M5M5V216AWG 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM FEATURES DESCRIPTION The M5M5V216A is a family of low voltage 2-Mbit static RAMs organized as 131,072-words by 16-bit, fabricated by Mitsubishi's high-performance 0.25µm CMOS technology. The M5M5V216A is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5V216AWG is packaged in a CSP (chip scale package), with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48pin) and ball pitch of 0.75mm. It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. From the point of operating temperature, the family is divided into three versions; "Standard", "W-version", and "I-version". Those are summarized in the part name table below. Single +2.7~+3.6V power supply Small stand-by current: 0.3µA(3V,typ.) No clocks, No refresh Data retention supply voltage=2.0V to 3.6V All inputs and outputs are TTL compatible. Easy memory expansion by S , BC1 and BC2 Common Data I/O Three-state outputs: OR-tie capability OE prevents data contention in the I/O bus Process technology: 0.25µm CMOS Package: 48 pin 7.0mm x8.5mm CSP PART NAME TABLE Version, Part name Operating temperature M5M5V216AWG -55L Standard 0 ~ +70 C M5M5V216AWG -70L M5M5V216AWG -55H 2.7 ~ 3.6V 2.7 ~ 3.6V M5M5V216AWG -70H M5M5V216AWG -70LW M5M5V216AWG -70L I 70ns(@ 2.7V) / 65ns(@3.3V) 55ns(@ 2.7V) / 50ns(@3.3V) 70ns(@ 2.7V) / 65ns(@3.3V) 70ns(@ 2.7V) / 65ns(@3.3V) 70ns(@ 2.7V) / 65ns(@3.3V) 55ns(@ 2.7V) / 50ns(@3.3V) 2.7 ~ 3.6V 70ns(@ 2.7V) / 65ns(@3.3V) 40 C --- --- 0.3µA 1µA 25 C 40 C 70 C 85 C --- --- 20µA --- 1µA 3µA 8µA --- --- --- --- --- 1µA 3µA --- --- 1µA 3µA 20µA 50µA 45mA (10MHz) 0.3µA 1µA 8µA 24µA 5mA (1MHz) --- --- 0.3µA 1µA 20µA 50µA 8µA 24µA * "typical" parameter is sampled, not 100% tested. PIN CONFIGURATION (TOP VIEW) (BOTTOM VIEW) 1 2 3 4 5 6 A BC1 OE A6 A3 A0 NC B DQ 16 BC2 A7 A2 S DQ 1 C DQ 14 DQ 15 A5 A1 DQ 2 D GND DQ 13 NC A4 DQ 4 E Vcc DQ 12 F DQ 11 DQ 10 A9 G DQ 9 NC H NC A8 Pin Function 6 5 4 3 2 1 A NC A0 A3 A6 OE BC1 B DQ 1 S A2 A7 BC2 DQ 16 S Chip select input DQ 3 C DQ 3 DQ 2 A1 A5 DQ 15 DQ 14 W Write control input Vcc D Vcc DQ 4 A4 NC DQ 13 GND OE Output inable input A0 ~ A16 Address input DQ1 ~ DQ16 Data input / output A16 GND DQ 12 Vcc BC1 Lower Byte (DQ1 ~ 8) A9 DQ 10 DQ 11 Upper Byte (DQ9 ~ 16) A13 A10 NC DQ 9 BC2 Vcc GND Ground supply A12 A11 A8 NC DQ 5 GND E GND DQ 5 A14 DQ 7 DQ 6 F DQ 6 DQ 7 A14 A10 A13 W DQ 8 G DQ 8 W A11 A12 A15 NC H NC A15 GND A16 25 C 55ns(@ 2.7V) / 50ns(@3.3V) 2.7 ~ 3.6V M5M5V216AWG -55H I M5M5V216AWG -70H I max. 55ns(@ 2.7V) / 50ns(@3.3V) 55ns(@ 2.7V) / 50ns(@3.3V) 2.7 ~ 3.6V M5M5V216AWG -55L I I-version -40 ~ +85 C time Active current Icc1 (3.0V, typ.) 55ns(@ 2.7V) / 50ns(@3.3V) 2.7 ~ 3.6V M5M5V216AWG -55HW M5M5V216AWG -70HW Stand-by current Icc(PD), Vcc=3.0V typical * Ratings (max.) 70ns(@ 2.7V) / 65ns(@3.3V) M5M5V216AWG -55LW W-version -20 ~ +85 C Access Power Supply MITSUBISHI ELECTRIC Power supply Outline: 48FJA NC: No Connection 1 MITSUBISHI LSIs revision-01, ' 98.12.08 M5M5V216AWG 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION The M5M5V216AWG is organized as 131,072-words by 16-bit. These devices operate on a single +2.7~3.6V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. The operation mode are determined by a combination of the device control inputs BC1 , BC2 , S , W and OE. Each mode is summarized in the function table. A write operation is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the low level S. The address(A0~A16) must be set up before the write cycle and must be stable during the entire cycle. A read operation is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and S are in an active state(S=L). When setting BC1 at the high level and other pins are in an active stage , upper-byte are in a selesctable mode in which both reading and writing are enabled, and lower-byte are in a non-selectable mode. And when setting BC2 at a high level and other pins are in an active stage, lowerbyte are in a selectable mode and upper-byte are in a non-selectable mode. When setting BC1 and BC2 at a high level or S at a high level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S. The power supply current is reduced as low as 0.3µA(25 C, typical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. FUNCTION TABLE BLOCK DIAGRAM S BC1 BC2 W OE Mode DQ1~8 DQ9~16 Icc H X X X X Non selection High-Z High-Z Standby L H H X X Non selection High-Z High-Z Standby Write L L H L L L H H X L L L H H H L H L L X Write High-Z Din Active L H L H L Read High-Z Dout Active L H L H H L L L L X Write Read L L L H L L L L H H A0 Read Din High-Z Active Dout High-Z Active High-Z High-Z Active High-Z High-Z Active Din Din Active Dout Dout Active High-Z High-Z Active DQ 1 A1 MEMORY ARRAY DQ 8 131072 WORDS x 16 BITS A15 - DQ 9 A16 CLOCK GENERATOR DQ 16 S BC1 Vcc BC2 W GND OE MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs revision-01, ' 98.12.08 M5M5V216AWG 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Ta Tstg Conditions Parameter Ratings Supply voltage With respect to GND Input voltage With respect to GND Output voltage With respect to GND Power dissipation Operating temperature Ta=25 C Standard (-L, -H) W-version (-LW, -HW) I-version (-LI, -HI) Units -0.5* ~ +4.6 -0.5* ~ Vcc + 0.5 0 ~ Vcc 700 0 ~ +70 - 20 ~ +85 - 40 ~ +85 - 65 ~ +150 Storage temperature V mW C C * -3.0V in case of AC (Pulse width < = 30ns) DC ELECTRICAL CHARACTERISTICS ( Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Symbol Parameter VIH VIL VOH1 VOH2 VOL II High-level input voltage IO Output leakage current BC1 and BC2=VIH or S=VIH or OE=VIH, VI/O=0 ~ Vcc Icc1 Active supply current ( AC,MOS level ) BC1 and BC2 < =0.2V , S < =0.2V > other inputs < = 0.2V or = Vcc-0.2V Output - open (duty 100%) f= 10MHz f= 1MHz Icc2 Active supply current ( AC,TTL level ) BC1 and BC2=VIL , S=VIL other pins =VIH or VIL Output - open (duty 100%) f= 10MHz f= 1MHz Conditions IOH= -0.5mA High-level output voltage 2 IOH= -0.05mA IOL=2mA Low-level output voltage V I =0 ~ Vcc Input leakage current High-level output voltage 1 -LW, -LI Icc4 Stand by supply current ( AC,TTL level ) +70 C <2> -HW, -HI -H, -HW, -HI BC1 and BC2 => Vcc - 0.2V S< = 0.2V Other inputs=0~Vcc BC1 and BC2=VIH , S=VIL +70 ~ +85 C +40 ~ +70 C +25 ~ +40 C -H 0 ~ +25 C -HW - 20 ~ +25 C -HI - 40 ~ +25 C or S=VIH Other inputs= 0 ~ Vcc Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=3.0V and Ta=25 C Parameter CI Input capacitance CO Output capacitance 0.6 V - 45 5 60 15 - 45 5 - - - - 1 0.3 0.3 0.3 60 15 60 20 30 10 5 2 2 2 - - 0.5 µA mA µA mA * -3.0V in case of AC (Pulse width < = 30ns) (Vcc=2.7 ~ 3.6V, unless otherwise noted) CAPACITANCE Symbol Units Vcc+0.3V 0.4 ±1 ±1 +70 ~ +85 C -L, -LW, -LI other inputs = 0 ~ Vcc ( AC,MOS level ) Max Vcc-0.5V S => Vcc - 0.2V, Stand by supply current Typ 2.0 -0.3 * 2.4 Low-level input voltage <1> Icc3 Min Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz MITSUBISHI ELECTRIC Min Limits Typ Max Units 8 10 pF 3 MITSUBISHI LSIs revision-01, ' 98.12.08 M5M5V216AWG 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~ 3.6V, unless otherwise noted) (1) TEST CONDITIONS Supply voltage Input pulse Input rise time and fall time Reference level Output loads 2.7V~3.6V VIH=2.2V,VIL=0.4V 5ns 1TTL DQ CL VOH=VOL=1.5V Transition is measured ±500mV from steady state voltage.(for ten,tdis) Including scope and jig capacitance Fig.1,CL=30pF CL=5pF (for ten,tdis) Fig.1 Output load (2) READ CYCLE Limits Parameter Symbol tCR ta(A) ta(S) ta(BC1) ta(BC2) ta(OE) tdis(S) tdis(BC1) tdis(BC2) tdis(OE) ten(S) ten(BC1) ten(BC2) ten(OE) tV(A) M5M5V216AWG - 70 M5M5V216AWG - 55 Read cycle time Address access time Chip select access time Byte control 1 access time Byte control 2 access time Output enable access time Output disable time after S high Output disable time after BC1 high Output disable time after BC2 high Output disable time after OE high Output enable time after S low Output enable time after BC1 low Output enable time after BC2 low Output enable time after OE low Data valid time after address Min 55 Min 70 Max 70 70 70 70 35 25 25 25 25 55 55 55 55 30 20 20 20 20 10 10 10 5 10 10 10 10 5 10 Units Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) M5M5V216AWG - 55 Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Byte control 1 setup time Byte control 2 setup time Chip select setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low Min 55 45 0 50 50 50 50 25 0 0 Max M5M5V216AWG - 70 Min 70 55 0 65 65 65 65 30 0 0 20 20 5 5 25 25 5 5 MITSUBISHI ELECTRIC Units Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs revision-01, ' 98.12.08 M5M5V216AWG 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle tCR A0~16 ta(A) ta(BC1) BC1 tv (A) ta(BC2) or and / or BC2 (Note3) tdis (BC1) or tdis (BC1) (Note3) ta(S) S (Note3) tdis (S) (Note3) tdis (OE) (Note3) ta (OE) OE (Note3) ten (OE) W = "H" level ten (BC1) ten (BC2) ten (S) DQ1~16 VALID DATA Write cycle ( W control mode ) tCW A0~16 tsu (BC1) or tsu(BC2) BC1 and / or BC2 (Note3) (Note3) tsu (S) S tsu (A-WH) (Note3) (Note3) OE tsu (A) tw (W) trec (W) tdis (W) W ten(OE) tdis(OE) DQ1~16 ten (W) DATA IN STABLE tsu (D) th (D) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs revision-01, ' 98.12.08 M5M5V216AWG 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (BC control mode) tCW A0~16 tsu (A) BC1 tsu (BC1) or tsu (BC2) trec (W) and / or BC2 S (Note3) (Note3) (Note5) W (Note4) (Note3) (Note3) tsu (D) th (D) DATA IN STABLE DQ1~16 Write cycle (S control mode) tCW A0~16 BC1 (Note4) and / or BC2 (Note3) tsu (A) tsu (S) trec (W) (Note3) S (Note5) W (Note4) (Note3) DQ1~16 tsu (D) th (D) (Note3) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S low , overlaps BC1 and/or BC2 low and W low. Note 5: When the falling edge of W is simultaneously or priorto the falling edge of BC1 and/or BC2 or the falling edge of S, the outputs are maintained in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs revision-01, ' 98.12.08 M5M5V216AWG 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Limits Parameter Test conditions Min Vcc (PD) Power down supply voltage VI (BC) VI (S) Byte control input BC1 & BC2 Chip select input S Icc (PD) Power down supply current Vcc=3.0V -LW, -LI 1) -L, -LW, -LI BC1 and BC2 > =Vcc - 0.2V S< = 0.2V other inputs=0~3V -HW, -HI +70 ~ +85 C +70 C - - - - 1 0.3 0.3 0.3 +40 ~ +70 C +25 ~ +40 C 2) -H S> = Vcc - 0.2V other inputs=0~3V -HW -20 ~ +25 C -HI -40 ~ +25 C 0 ~ +25 C Max Units V 2.0 2.0 2.0 - +70 ~ +85 C -H, -HW, -HI Typ V V 50 20 24 8 3 1 1 1 µA µA µA µA µA µA µA µA Typical value is for Ta=25 C (2) TIMING REQUIREMINTS Limits Symbol Parameter tsu (PD) trec (PD) Power down set up time Power down recovery time Test conditions Min Typ 0 5 Max Units ns ms (3) TIMING DIAGRAM BC control mode Vcc tsu (PD) BC1 2.7V 2.7V trec (PD) 2.2V 2.2V BC1 , BC2 > = Vcc - 0.2V BC2 S control mode Vcc tsu (PD) 2.7V 2.7V trec (PD) 2.2V S 2.2V S> = Vcc - 0.2V MITSUBISHI ELECTRIC 7