MITSUBISHI LSIs 1997.01.22 M5M5V32R16J,TP-10,-12,-15 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) FEATURES Fast access time M5M5V32R16J,TP-10 10ns(max) M5M5V32R16J,TP-12 12ns(max) M5M5V32R16J,TP-15 15ns(max) Low power dissipation Active 297mW(typ) Stand by 0.33mW(typ) Single +3.3V power supply Fully static operation : No clocks, No refresh Common data I/O Easy memory expansion by /S Three-state outputs : OR-tie capability OE prevents data contention in the I/O bus Directly TTL compatible : All inputs and outputs Separate control of lower and upper bytes by /LB and /UB N.C A3 A2 ADDRESS INPUTS A1 A0 CHIP SELECT /S INPUTS DQ1 DATA DQ2 INPUTS/ OUTPUTS DQ3 DQ4 (3.3V) Vcc (0V) GND DQ5 DATA DQ6 INPUTS/ OUTPUTS DQ7 DQ8 WRITE CONTROL /W INPUT A14 A13 ADDRESS INPUTS A12 A11 NC 1 44 2 43 3 42 4 41 5 40 6 39 7 8 9 10 11 12 13 14 15 M5M5V32R16J,TP The M5M5V32R16 is a family of 32768-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. In write and read cycles, the lower and upper bytes are able to be controled either togethe or separately by /LB and /UB. 38 35 36 35 34 33 32 31 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 Outline A4 ADDRESS A5 INPUTS A6 OUTPUT /OE ENABLE BYTE /UB CONTROL /LB INPUTS DQ16 DQ15 DATA INPUTS/ DQ14 OUTPUTS DQ13 GND (0V) Vcc (3.3V) DQ12 DQ11 DATA INPUTS/ DQ10 OUTPUTS DQ9 NC A7 A8 ADDRESS INPUTS A9 A10 NC 44P0K(J) 44P3W-H(TP) PACKAGE APPLICATION M5M5V32R16J : 44pin 400mil SOJ M5M5V32R16VP: 44pin 400mil TSOP(II) High-speed memory system FUNCTION The operation mode of the M5M5V32R16 is determined by a combination of the device control inputs /S, /W, /OE, /LB, and /UB. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with low level /LB and/or low level /UB and low level /S. The address must be set-up before write cycle and must be stable during the entire cycle. The data is latched into a cell on the traling edge of /W, /LB, /UB or /S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input /OE directly controls the output stage. Setting the /OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and /OE at a low level while /LB and/or /UB and /S are in an active state. (/LB and/or /UB=L, /S=L) When setting /LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when setting /UB at a high level and other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enable, and upper-Byte are in a non-selectable mode. When setting /LB and /UB at a high level or /S at high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by /LB, /UB and /S. Signal-/S controls the power-down feature. When /S goes high, power dissapation is reduced extremely. The access time from /S is equivalent to the address access time. MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M5V32R16J,TP-10,-12,-15 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION TABLE /S /W /OE /LB /UB Mode DQ1 - 8 DQ9 - 16 Icc L H L L L Read cycle All Bytes D OUT Active H L Read cycle Upper Bytes D OUT High-impedance L H L L H L D OUT Active L H Read cycle Lower Bytes D OUT High-impedance Active L L L L X L L Write cycle All Bytes D IN D IN Active X H L Write cycle Upper Bytes High-impedance D IN Active L L L H X L H Write cycle Lower Bytes D IN High-impedance Active H X X L Output disable High-impedance High-impedance Active X X H H H X X X X Non selection High-impedance High-impedance Stand by 6 OUTPUT BUFFERS /S MEMORY ARRAY 512 ROWS 1024 COLUMNS 7 8 9 10 13 14 15 16 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 29 30 31 32 35 36 37 38 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 11 33 Vcc 12 34 GND DATA INPUT BUFFERS CHIP SELECT INPUTS 27 42 3 4 5 18 19 20 21 ROW ADDRESS DECODERS ADDRESS INPUTS A7 A6 A2 A1 A0 A14 A13 A12 A11 ROW INPUT BUFFERS BLOCK DIAGRAM COLUMN I/O CIRCUITS UPPER BYTE CONTROL INPUTS LOWER BYTE CONTROL INPUTS OUTPUT BUFFERS OUTPUT ENABLE INPUT /W 17 /OE 41 COLUMN ADDRESS DECODERS /UB 40 COLUMN INPUT BUFFERS /LB 39 24 25 26 43 44 DATA INPUT BUFFERS WRITE CONTROL INPUT 2 A10 A9 A8 A5 A4 A3 ADDRESS INPUTS MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M5V32R16J,TP-10,-12,-15 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Conditions Ratings Unit -2.0* ~ 4.6 V With respect to GND -2.0* ~ Vcc+0.5 V Parameter Vcc Supply voltage VI Input voltage VO Output voltage Pd Power dissipation Topr Operating temperature -2.0* ~ Vcc V 1000 mW 0 ~ 70 C Tstg(bias) Storage temperature(bias) -10 ~ 85 C Tstg -65 ~ 150 C Ta=25 C Storage temperature * Pulse width < = 20ns, In case of DC: - 0.5V DC ELECTRICAL CHARACTERISTICS Symbol (Ta=0 ~ 70 C , Vcc=3.3V Parameter +10% - 5%, unless otherwise noted) Condition VIH VIL VOH VOL II High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current IOZ Output current in off-state I CC1 Active supply current (TTL level) Min 2.0 -0.3* 2.4 IOH = - 4mA IOL= 8mA V I = 0 ~ Vcc VI (/S)= VIH VO= 0 ~ Vcc AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC VI (/S)= VIL other inputs VIH or VIL Output-open(duty 100%) I CC2 Stand-by supply current (TTL level) VI (/S)= VIH I CC3 Stand-by current (MOS level) VI (/S)= Vcc=> 0.2V other inputs VI < = 0.2V or VI => Vcc - 0.2V Limits Typ Max Vcc+0.3 0.8 90 0.4 2 V V V V µA 10 µA 150 130 110 100 60 55 50 40 0.1 Unit mA mA 1 mA Max 6 8 Unit * Pulse width < = 20ns, in case of AC : - 3.0V CAPACITANCE (Ta=0 ~ 70 Symbol C, Vcc=3.3V +10% - 5% , unless otherwise noted) Parameter Test Condition Min Limit Typ CI Input capacitance VI =GND,Vi =25mVrms,f=1MHz CO Output capacitance Vo =GND,Vo =25mVrms,f=1MHz Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc=3.3V,Ta=25 C 3: CI,CO are periodically sampled and are not 100% tested. pF pF AC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C , Vcc=3.3V +10% - 5%, unless otherwise noted) (1) MEASUREMENT CONDITION Input pulse levels Input rise and fall time Input timing reference levels Output timing reference levels Output loads VIH =3.0V, V IL =0.0V 3ns V IH =1.5V, VIL =1.5V V OH =1.5V, V OL =1.5V Fig1,Fig2 Vcc (Including scope and JIG ) 480Ω DQ DQ 50Ω VL=1.5V Fig.1 Output load MITSUBISHI ELECTRIC 255Ω ( 5pF Including scope and JIG ) Fig.2 Output load for ten , tdis 3 MITSUBISHI LSIs M5M5V32R16J,TP-10,-12,-15 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM READ CYCLE Symbol tCR ta (A) ta (S) ta (OE) ta (B) tdis (S) tdis (OE) tdis (B) ten (S) ten (OE) ten (B) tv (A) tPU tPD Parameter Read cycle time Limits M5M5V32R16 -10 M5M5V32R16 -12 M5M5V32R16 -15 Unit Min 10 Address access time Chip select access time Output enable access time /LB,/UB access time Output disable time after /S high Output disable time after /OE high Output disable time after /LB,/UB high Output enable time after /S low Output enable time after /OE low Output enable time after /LB,/UB low Data valid time after address change Power-up time after chip selection Power down time after chip selection 0 0 0 4 3 3 Max 10 10 5 5 5 5 5 Max Min 12 12 12 6 6 6 6 6 0 0 0 4 3 3 4 0 Min 15 0 0 0 4 3 3 4 0 Max 15 15 7 7 7 7 7 4 0 10 12 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write cycle Limits Symbol tCW tw(W) tsu (B) tsu (A)1 tsu (A)2 tsu (S) tsu (D) th(D) trec(W) tdis (W) tdis (OE) ten (W) ten (OE) ten (B) tsu(A-WH) tsu(A-SH) tsu (A-BH) Parameter Write cycle time Write pulse width /LB,/UB setup time Address setup time(/W) Address setup time(/S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after /W low Output disable time after /OE high Output enable time after /W high Output enable time after /OE low Output enable time after /LB,/UB low Address to /W High Address to /S High Address to /LB,/UB High M5M5V32R16 -10 M5M5V32R16 -12 M5M5V32R16 -15 Unit Min Max Min Max Min Max 10 12 15 ns 9 10 12 ns 10 12 ns 9 0 0 0 ns 0 0 0 ns 9 10 12 ns 5 6 7 ns 0 0 ns 0 0 0 ns 0 0 6 0 7 ns 0 5 0 6 0 7 ns 0 5 0 0 ns 0 0 0 ns 0 0 0 ns 0 10 12 ns 9 10 12 ns 9 10 12 ns 9 MITSUBISHI ELECTRIC 4 MITSUBISHI LSIs M5M5V32R16J,TP-10,-12,-15 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle 1 A 0~14 t CR VIH VIL ta (A) tv (A) tv (A) DQ1~16 VOH PREVIOUS DATA VALID VOL /W=H /LB=L /S=L /UB=L UNKNOWN DATA VALID /OE=L Read cycle 2 (Note 4) t CR VIH /S VIL tdis (S) ta (S) (Note 5) ten (S) DQ1~16 (Note 5) VOH UNKNOWN DATA VALID VOL tPU ICC1 Icc tPD 50% ICC2 /W=H 50% /UB=L /OE=L /LB=L Note 4. Addresses valid prior to or coincident with /S transition low. 5. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2. Read cycle 3 (Note 6) t CR VIH /OE VIL ta(OE) (Note 5) DQ1~16 VOH tdis (OE) (Note 5) ten (OE) UNKNOWN DATA VALID VOL /W=H /UB=L /S=L /LB=L Note 6. Addresses and /S valid prior to /OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE)) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs M5M5V32R16J,TP-10,-12,-15 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM Read cycle 4 (Note 7) /UB,/LB t CR VIH VIL tdis (B) ta (B) (Note 5) DQ1~16 (Note 5) ten (B) VOH UNKNOWN DATA VALID VOL /W=H /OE=L /S=L Note 7. Addresses , /S and /OE valid prior to /LB,/UB transition low by (ta(A)-ta(B)), (ta(S)-ta(B)), (ta(OE)-ta(B)). Write cycle (/W control mode) t CW A 0~14 VIH VIL /S VIH VIL tsu (S) (Note8) /OE VIH VIL tsu (A) /W (Note8) tsu (A-WH) tw (W) trec (W) VIH VIL tsu (B) /LB,/UB VIH VIL (Note8) tdis (OE) DQ1~16 (Input Data) (Note8) tsu (D) th (D) VIH VIL DATA STABLE tdis (W) (Note 5) ten (OE) ten (W) tdis (OE) DQ1~16 (Output Data) VOH VOL (Note 5) Hi-Z Note 8: Hatching indicates the state is don't care. 9: When the falling edge of /W is simultaneous or prior to the falling edge of /S, the output is maintained in the high impedance. 10: ten,tdis are periodically sampled and are not 100% tested. MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs M5M5V32R16J,TP-10,-12,-15 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM Write cycle(/S control) t CW A 0~14 VIH VIL /S VIH VIL /W VIH VIL tsu (A) tsu (S) trec (W) tw (W) (Note7) (Note7) tsu (B) /LB,/UB VIH VIL (Note7) (Note7) tsu (D) DQ1~16 (Input Data) VIH VIL DATA STABLE (Note5) DQ1~16 (Output Data) VOH VOL th (D) tdis (W) (Note5) ten (S) Hi-Z (Note9) Write cycle(/LB,/UB control) t CW A 0~14 VIH VIL tsu (S) /S VIH VIL (Note7) /W (Note7) tw (W) VIH VIL (Note7) tsu (A) /LB,/UB (Note7) tsu (B) trec (W) VIH VIL tsu (D) DQ1~16 (iInput Data) VIH VIL DATA STABLE (Note5) DQ1~16 (Output Data) VOH VOL th (D) tdis (W) (Note5) ten (B) Hi-Z (Note9) MITSUBISHI ELECTRIC 7 MITSUBISHI LSIs M5M5V32R16J,TP-10,-12,-15 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM '96.11.20 P3 Vref --> 5.0V k.kubo '97.01.22 P3 Output loads=50Ω k.kubo '97.02.04 P3 Vref --> Vcc k.kubo MITSUBISHI ELECTRIC