MITSUBISHI LSIs 1998.11.30 Ver.B M5M54R01AJ-12,-15 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM DESCRIPTION The M5M54R01AJ is a family of 4194304-word by 1-bit PIN CONFIGURATION (TOP VIEW) static RAMs, fabricated with the high performance CMOS silicon gate process and designed for high speed application. These devices operate on a single 3.3V supply, and are address inputs directly TTL compatible. They include a power down chip select input feature as well. A0 A1 A2 A3 A4 A5 S (3.3V) VCC (0V) GND FEATURES •Fast access time M5M54R01AJ-12 ... 12ns(max) M5M54R01AJ-15 ... 15ns(max) •Single +3.3V power supply •Fully static operation : No clocks, No refresh •Easy memory expansion by S •Three-state outputs : OR-tie capability •OE prevents data contention in the I/O bus •Directly TTL compatible : All inputs and outputs APPLICATION High-speed memory units data inputs write control input address inputs D W A6 A7 A8 A9 A10 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Outline A21 A20 address A19 inputs A18 A17 A16 output enable OE input GND (0V) VCC (3.3V) data outputs Q A15 A14 address A13 inputs A12 A11 control B1/B4 byte input 32P0K PACKAGE M5M54R01AJ : 32pin 400mil SOJ BLOCK DIAGRAM address inputs A0 1 A1 A2 2 A3 4 A4 A5 5 6 3 MEMORY ARRAY 1024 ROWS 4096 COLUMNS data 23 Q outputs A6 12 A7 13 A8 14 A9 15 S W 7 11 COLUMN I/O CIRCUITS COLUMN ADDRESS COLUMN ADDRESS DECODERS DECODERS COLUMN INPUT BUFFERS OE 26 data 10 D inputs/ 8 24 VCC (3.3V) 9 GND (0V) 25 B1/B4 17 16 18 19 20 21 22 27 28 29 30 31 32 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 address inputs MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M54R01AJ-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M54R01AJ is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a non-selectable mode in which both reading and writing are disable. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. The RAM works with an organization of 4194304-word by 1bit, when B1/B4 is low of floating. And an organization of 1048576-word by 4bit is also obtained for reducing the test time,when B1/B4 is high. The pin configuration and function is as same as M5M54R04AJ. FUNCTION TABLE B1/B4 L S H W X OE X L L L X L L H L L L H H Mode Non selection Q D High-impedance Icc Stand by High-impedance Write Din Read High-impedance Dout Active High-impedance High-impedance High-impedance Active Active ABSOLUTE MAXIMUM RATINGS Symbol Parameter V cc Supply voltage VI Input voltage VO Output voltage Pd Power dissipation T opr Operating temperature Conditions With respect to GND Ratings Unit - 2.0 *~ 4.6 - 2.0*~ VCC+0.5 V - 2.0*~ VCC V Ta=25°C V 1000 mW 0 ~ 70 °C Tstg(bias) Storage temperature(bias) - 10 ~ 85 °C T stg - 65 ~ 150 °C * Pulse Storage temperature width≤3ns, In case of DC: - 0.5V DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70°C, Vcc=3.3V Symbol VIH VIL VOH VOL II Parameter +10% - 5% Limits Condition Min High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current 2.0 I OZ I OH = - 4mA IOL = 8mA VI= 0 ~ Vcc VI(S)=VIH Output current in off-state VI/O= 0 ~ Vcc I CC1 Active supply current (TTL level) VI(S)=VIL other inpus=VIH or VIL Output-open(duty 100%) AC Stand by current (TTL level) VI(S)=VIH Stand by current VI(S)=Vcc≥0.2V other inputs VI≤0.2V or VI ≥Vcc - 0.2V AC DC I CC3 Typ Max Unit 0.4 2 V V V V uA 2 uA Vcc+0.3 0.8 2.4 12ns cycle 180 15ns cycle 160 DC I CC2 ,unless otherwise noted) mA 90 12ns cycle 70 15ns cycle 60 mA 40 10 mA Note 1: Direction for current flowing into an IC is positive (no mark). MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M54R01AJ-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM CAPACITANCE (Ta=0~70°C, Vcc=3.3V Symbol Parameter +10% -5% ,unless otherwise noted) Test Condition Min Limit Typ Max Unit CI Input capacitance V I =GND, V I =25mVrms,f=1MHz 8 pF CO Output capacitance V O=GND, V O=25mVrms,f=1MHz 8 pF Note 2: CI,CO are periodically sampled and are not 100% tested. AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V +10% -5% ,unless otherwise noted) (1)MEASUREMENT CONDITION Input pulse levels .................................... VIH=3.0V, VIL=0.0V Input rise and fall time .................................................... 3ns Input timing reference levels ........................ VIH=1.5V, VIL=1.5V Output timing reference levels ................. VOH =1.5V, VOL=1.5V Output loads ........................................................ Fig.1,Fig.2 5.0V OUTPUT Z0=50Ω 480Ω DQ DQ 255Ω RL=50Ω 5pF (including scope and JIG) VL=1.5V Fig.1 Output load Fig.2 Output load for ten , t dis MITSUBISHI ELECTRIC 3 MITSUBISHI LSIs M5M54R01AJ-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM (2)READ CYCLE Limits Symbol tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tv(A) tPU tPD M5M54R01AJ-12 Parameter Min 12 Read cycle time Address access time Chip select access time Output enable access time 0 0 3 1 3 0 Output disable time after S high Output disable time after OE high Output enable time after S low Output enable time after OE low Data valid time after address change Power-up time after chip selection M5M54R01AJ-15 Max Min 15 12 12 6 6 6 0 0 3 1 3 0 12 Power-down time after chip selection Unit Max 15 15 7 7 7 15 ns ns ns ns ns ns ns ns ns ns ns (3)WRITE CYCLE Limits Symbol M5M54R01AJ-12 Parameter tCW tw(W) Write cycle time tw(W) tsu(A)1 tsu(A)2 tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) tsu(A-WH) Write pulse width(OE high) Address setup time(W) Min 12 Write pulse width (OE low) Max 12 10 0 0 Address setup time(S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low Address to W High Min 15 10 6 15 10 0 0 10 7 0 1 0 0 0 0 0 1 0 0 0 0 10 MITSUBISHI ELECTRIC M5M54R01AJ-15 6 6 10 Unit Max 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs M5M54R01AJ-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle 1 A 0~21 t CR VIH VIL ta(A) tv(A) Q VOH tv(A) PREVIOUS DATA VALID VOL UNKNOWN DATA VALID W=H S=L OE=L Read cycle 2 (Note 3) t CR S VIH VIL ta(S) VOH UNKNOWN DATA VALID VOL tPU Icc (Note 4) (Note 4) ten(S) Q tdis(S) ICC1 tPD 50% ICC2 50% W=H OE=L Note 3. Addresses valid prior to or coincident with S transition low. 4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2. Read cycle 3 (Note 5) OE t CR VIH VIL ta(OE) (Note 4) Q VOH tdis(OE) (Note 4) ten(OE) UNKNOWN DATA VALID VOL W=H S=L Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE)) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs M5M54R01AJ-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM Write cycle (W control mode) t CW A 0~21 VIH VIL S VIH VIL tsu(S) (Note 6) (Note 6) tsu(A-WH) OE VIH VIL tsu(A) W tw(W) trec(W) VIH VIL tsu(D) D VIH VIL th(D) DATA STABLE tdis(W) (Note 4) ten(OE) ten(W) tdis(OE) Q VOH VOL (Note 4) Hi-Z Write cycle(S control) t CW A 0~21 VIH VIL S VIH VIL tsu(A) tsu(S) trec(W) tw(W) W VIH VIL (Note 6) (Note 6) tsu(D) D VIH VIL DATA STABLE ten(S) Q VOH VOL th(D) (Note 4) tdis(W) (Note 4) Hi-Z (Note 7) Note 6: Hatching indicates the state is don't care. 7: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 8: ten,tdis are periodically sampled and are not 100% tested. MITSUBISHI ELECTRIC 6