MITSUBISHI M65580MAP

Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
Description
The M65580MAP-XXXFP are semiconductor integrated circuits designed with CMOS silicon gate technology for NTSC television
system, include 8bit MCU( M37272MA core) with a closed caption decoder and circuits needed for TV baseband signals(Video and
Chroma) processor and Deflection in a chip. PCB area and EMI noise can be reduced by one chip and 80QFP, and internal
connection of OSD signals. And it can realize a adjustment free system by built-in MCU and get a high performance adaptive YC
separation by 1 line memory. The above technology makes its performance more stable and better.
Feature
• Y/C processor
: 8bit Input, 10bit Output digital processing
• Deflection processor : optimized system by conventional analog and digital mixed solution
• ADC&DAC
: 8bit high speed video ADC & 10bit high speed video DAC
[MCU Block]
MCU(single microcomputer) in this IC has almost same function and performance as M37272MA-XXXSP/FP in mass-production.
And it is operated by simple instruction in the same memory space as that of built-in ROM, RAM, I/O.
2
It has a OSD, data slicer , and I C-BUS interface. So it is very useful for a channel selection system for NTSC TV with a closed caption
decoder.
[ASIC Block]
ASIC block consists of the following blocks.
(1) Analog frontend block ; Analog SW(2 CVBS(TV&EXT) inputs, Y/C signals to one signal, 2 channels 8 bit high speed video ADCs,
and ACC amplifiers
(2) Video and Chroma block ; A high performance 2 line adaptive YC separation by 1 line memory, Video blocks including sharpness,
YNR, a high performance blackstretch circuits, Chroma decoder, and RGB matrix including OSD mixing circuit.
(3) Deflection block ; A high performance sync separation by analog and digital mixed solution
(4) Analog backend block ; 3 channels 10 bit high speed video DACs for Cutoff & Drive, and Mute circuit.
Application
P00/PWM0
P14/SDA2
P13/SDA1
P12/SCL2
P11/SCL1
P10/OUT2
P31/B
P30/G
P53/OUT1
P52/R
P51/VSYNC
P50/HSYNC IN/OUT
V-PULSE OUT
OSD(R) IN
FAST BLK
OSD(G) IN
OSD(B) IN
HALF TONE
SCL
SDA
H OUT
FBP IN
VDD(DEF)
VSS(DEF)
NTSC TV with a closed caption decoder
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PIN CONFIGURATION (TOP VIEW)
M65580MAP-XXXFP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NECK PROTECTOR
HVCO F/B
V-RAMP OUT
AFC1 FILTER
X-RAY PROTECT
X-TAL
CHROMA APC FILTER
VDD(VCXO)
B OUT
VSS(OUTPUT)
G OUT
VDD(OUTPUT)
R OUT
VZ OUT
TV IN
VRB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VSS
FILT
VCC
P27/XCOUT
P26/FSCIN/XCIN
RESETB
P22/SIN/AD8
P21/SOUT/AD7
P20/SCLK/AD6
P15/AD1/INT3/FSCIN
P16/AD2/TIM2
VSS(DIGITAL)
OSD CLK
VDD(DIGITAL)
CLK OUT
RESETB(ASIC)
SYNC SEP IN
Y SW OUT
VDD(INPUT)
EXT IN
VSS(INPUT)
Y IN
VRT
C IN
P01/PWM1
P02/PWM2
P03/PWM3
P04/PWM4
P05/AD3
P06/INT2/AD4
P07/INT1
P23/TIM3
P24/TIM2
P25/AD5
HLF
VHOLD
CV IN
CN VSS
X IN
X OUT
MITSUBISHI
1
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
33 19 21 25 23 42 41 37
44 43 40 35 34
HVCO F/B
V-RAMP OUT
XTAL
Neck Protector
FBP IN
H OUT
AFC1 Filter
Vss(DEF)
Vdd(DEF)
Vrt
Vrb
Vss(Input)
Vdd(Input)
Vdd(VCXO)
Block Diagram(Whole)
Chroma APC Filter
M65580MAP-XXXFP
38 39
VZ OUT
27
36
X-ray Protect
Vss(OUTPUT)
31
12
Vss(Digital)
Vdd(OUTPUT)
29
14
Vdd(Digital)
16
RESET
SYNC SEP IN
18
Y SW OUT
58
57
55
Vss
1
Vcc
3
To TV IN of ASIC
77
75
SCL
OSD V-SYNC
HALF TONE
FAST BLK
32
B OUT
30
G OUT
28
R OUT
15
CLK(fsc) OUT
11
INTELLIGENT
MONITOR
59
52
54
47
OSD(B) OUT
CV IN
HLF
78
MCU CORE
M37272MA
MITSUBISHI
4
7
P27/XCOUT
P22/S IN/AD8
P25/AD5
P24/TIM2
P23/TIM3
P07/INT1
P06/INT2/AD4
P05/AD3
P04/PWM4
P03/PWM3
63 64 65 66 67 68 69 70 71 72 73 74
P02/PWM2
X IN
80
X OUT
FSC IN
I/O PORT
P01/PWM1
79
6
VHOLD
P14/SDA2
CNVss
5
61
EEPROM
EXT IN
OSD(G) OUT
62
P12/SCL2
Y IN
20
OSD(R) OUT
60
SDA
22
RGB OUT
Intelligent Monitor
HALF TONE
VD
OSD H-SYNC
P00/PWM0
2in1 Tuner
76
OSD V-SYNC
VD
56
HALF TONE
FAST BLK
HALF TONE
53
OSD(R) IN
HD
50
OSD(G) IN
FAST BLK
51
C IN
OSD(B) IN
OSD
49
HD
SDA
FAST BLK
SCL
45
3bit Digital OSD
46
48
TV IN
24
CLK-2 OUT
CCD
13
SIGNAL PROCESSOR
26
CVBS/YC input
17
RESET
RESET
2
FILT
10
P15/AD1/INT3
9
P20/SCLK/AD6
8
P21/S OUT/AD7
2
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
Absolute maximum ratings
Symbol
Parameter
VDD (MCU)
Supply voltage (MCU)
VDD (ASIC5V)
Supply voltage (ASIC5V)
Conditions
VDD (ASIC3.3V) Supply voltage (ASIC3.3V)
All voltage are based on
Vss.Output transistors are
cut off.
Ratings
Unit
-0.3 to 6.0
V
-0.3 to 6.0
V
-0.3 to 4.0
V
-0.3 to Vcc+0.3
V
VI (MCU)
Input Voltage (MCU)
VO (MCU)
Output Voltage (MCU)
-0.3 to Vcc+0.3
V
IOH (MCU)
Circuit current (MCU)
0 to 1 (See note 1)
mA
IOL1 (MCU)
Circuit current (P00-P07, P10, P15,
0 to 2 (See note 2)
mA
0 to 6 (See note 2)
mA
-0.3 to Vcc+0.3
V
-30
mA
P16, P20-P27, P30, P31, P52, P53)
IOL2 (MCU)
Circuit current (P11-P14)
VID (ASIC)
Digital input voltage
IOUT (ASIC)
Analog output current
Pd
Power dissipation
1460
mW
Kt
Thermal derating
14.6
mW/ ˚C
Topr
Operating temperature
-20 to 65
˚C
Tstg
Storage temperature
-40 to 125
˚C
Recommended operating condition
(Ta=-20 to 65 ˚C, unless otherwise noted)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD (MCU)
Supply voltage (MCU) (See note 3)
4.75
5.0
5.25
V
VDD (Digital)
Supply voltage (Digital)
4.75
5.0
5.25
V
VDD (Input)
Supply voltage (Input)
3.13
3.3
3.47
V
VDD (Output)
Supply voltage (Output)
3.13
3.3
3.47
V
VDD (VCXO)
Supply voltage (VCXO)
4.75
5.0
5.25
V
VDD (DEF)
Supply voltage (DEF)
4.75
5.0
5.25
V
VIH1 (MCU)
High Input voltage P00-P07, P10-P16, P20-P27, P50,
P51, RESETB, XIN
0.8Vcc
Vcc
V
VIH2 (MCU)
High Input voltage SCL1, SCL2, SDA1, SDA2
(When using I2C-Bus)
0.7Vcc
Vcc
V
VIH3 (ASIC)
High Input voltage RESETB, FBP IN, HALF TONE,
OSD(R/G/B) IN, FAST BLK
0.8Vcc
Vcc
V
VIL1 (MCU)
Low Input voltage P00-P07, P10-P16, P20-P27
0
0.4Vcc
V
VIL2 (MCU)
Low Input voltage SCL1, SCL2, SDA1, SDA2
(When using I2C-Bus)
0
0.3Vcc
V
VIL3 (MCU)
Low Input voltage (See note 4) P50, P51, RESETB,
XIN, TIM2, TIM3, INT1, INT2, INT3, SIN, SCLK
0
0.2Vcc
V
VIL4 (ASIC)
Low Input voltage RESETB, FBP IN, HALF TONE,
OSD(R/G/B) IN, FAST BLK
0
0.2Vcc
V
IOH (MCU)
High average output current (See note 1)
P10-P16, P20-P27, P30, P31, P52, P53
1
mA
MITSUBISHI
3
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
Limits
Symbol
IOL1 (MCU)
Parameter
Min.
Typ.
Low average output current (See note 2)
Max.
Unit
2
mA
6
mA
P00-P07, P10, P15, P16, P20-P27, P30, P31, P52, P53
IOL2 (MCU)
Low average output current (See note 2) P11-P14
f(XIN) (MCU)
Oscillation frequency (for CPU operation) XIN
(See note 5)
7.9
8.0
8.1
MHz
f(XCIN) (MCU)
Oscillation frequency (for sub-clock operation) XCIN
29
32
35
kHz
FSCIN (MCU)
Oscillation frequency (for OSD standard clock) FSCIN
fhs1 (MCU)
Input frequency TIM2, TIM3, INT1, INT2, INT3
fhs2 (MCU)
Input frequency SCLK
fhs3 (MCU)
Input frequency SCL1, SCL2
VI (MCU)
Input amplitude video signal CVIN
3.58
1.5
2.0
MHz
100
kHz
1
MHz
400
kHz
2.5
V
Note 1: The total current that flows out the MCU must be 20mA or less.
2: The total input current to MCU (IOL1+IOL2) must be 30mA or less.
3: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data
slicer, use 8MHz.
4: Pin name in each parameter is described pin names.
(1) Dedicated pins: dedicated pin name.
(2) Double-/Triple-function ports.
When the same limits: I/O port name.
When the limits of function except ports are different from I/O port limits; function pin name.
5: P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer pins.
P11-P14 have the hysteresis when these pins are used as multi-master I2C-Bus interface ports.
P20-P22 have the hysteresis when these pins are used as serial I/O pins.
Thermal derating
POWER DISSIPATION Pd (W)
THERMAL DERATING (MAXIMUM RATING)
2.0
1.5
1.46
1.0
0.88
0.5
0
25
50 65 75 100 125 150
AMBIENT TEMPERATURE Ta (˚C)
MITSUBISHI
4
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
[MCU Block(M37272MA)]
Description
MCU(single microcomputers) in this IC has almost same function and performance as M37272MA-XXXSP/FP in massproduction. And it is operated by simple instruction in the same memory space as that of built-in ROM, RAM, I/O.
2
It has a OSD, data slicer , and I C-BUS interface, so it is very useful for a channel selection system for NTSC TV with a
closed caption decoder.
Features
• Number of basic instructions
• Memory size
ROM
RAM
-------- 71
-------- 40Kbytes
-------- 1152bytes
(ROM correction memory:64bytes included)
--------- 0.5µs
• minimum instruction execution time
(at 8 MHz oscillation frequency)
• Power source voltage
-------- 5V±10%
• Subroutine nesting
-------- 128 levels(max.)
• Interrupts
-------- 17bytes 16vector
• 8-bit timers
-------- 6
• Programmable I/O ports(Ports P0,P1,P2)
-------- 23
• Input ports(Ports P50,P51)
-------- 2
• Output ports(Ports P30,P31,P52,P53)
-------- 4
• Serial I/O
-------- 8-bit x 1channel
2
-------- 1(2 systems)
• Multi-master I C-BUS interface
• A-D comparator (7-bit resolution)
-------- 8 channels
• PWM output circuit
-------- 8-bit x 5
• ROM correction function
-------- 32 bytes x 2
Power dissipation
-------- 165mW
(at Vcc=5.5V, 8MHz oscillation frequency, OSD on, and Data slicer on)
• Closed caption data slicer
• OSD function
Display characters -------- 32 characters x 2 lines(possible to display 3 lines or more by software)
Kinds of characters
254 kinds
Character display area
CC mode : 16x26 dots
OSD mode : 16x20 dots
Kinds of character sizes
CC mode : 1 kind
OSD mode : 8 kinds
Kinds of character colors
8 colors(R,G,B) (coloring unit: a character)
Kinds of background colors CC mode : 1 kind(black)
OSD mode : 8 kinds(possible to select color in character unit)
Display position
horizontal : 128 levels
Vertical : 512 levels
Attribute
CC mode : smooth italic, underline, flash, automatic solid space
OSD mode : border(black)
Kinds of raster colors
8 kinds
Smooth roll-up
Window function
MITSUBISHI
5
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
[ASIC Block]
Description
CVBS(TV/EXT) signals or Y/C signals input to this IC are converted to 8 bit digital signal by 2 channels high speed video
ADCs. These signals are input to digital section to obtain high performance R/G/B signals. First, CVBS signals are separated
to high quality Y/C signals by 2 dimensional adaptive YC separation circuit, and then Y/C signals are converted to R-Y&B-Y
signals by digital chroma decoder, after that, to R/G/B signals by RGB matrix circuit. These signals are mixed with OSD
signals come from MCU block, are converted to analog R/G/B signals by 3 channel 10 bit high speed video DACs. In
deflection block, to get a better Horizontal & Vertical signals, a conventional analog solution by analog CMOS technology is
used.
ASIC block consists of the followings blocks.
(1) Analog frontend block ; Analog SW(2 CVBS(TV&EXT) inputs, Y/C signals to one signal), 2 channels 8 bit high speed video
ADCs , and ACC amplifiers
(2) Video and Chroma block ; A high performance 2 line adaptive YC separation by 1 line memory, Video blocks including
sharpness, YNR, a high performance blackstretch circuits, Chroma decoder, and RGB matrix including OSD mixing circuit.
(3) Deflection block ; A high performance sync separation by analog and digital mixed solution
(4) Analog backend block ; 3 channels 10 bit high speed video DACs for Cutoff & Drive, and Mute circuit.
Features
[Video/Chroma Block]
• Built-in 1 Video SW for TV/EXT signal input
• 2 additional pins for S(Y/C) input
• YUV input signal available ( T.B.D )
• 2 channel 8 bit Video ADCs for CVBS(TV&EXT) or Y/C signal inputs
• Built-in adaptive 2 line comb filter(2DYCS) => Few dot crawl&crosscolor, and clear color transition
• Built-in a high performance Blackstretch
=> Dynamic & detailed picture
• Digital Luminance delay circuit
=> stable Y/C timing adjustment
• Built-in VCXO circuit(4fsc)
• High resolution R/G/B output
=> Built-in 10bit high speed Video DACs
• Internal connection of 8 color digital OSD ( R/G/B, F.B, H.T )
• Reference CLK output for tuner (fsc or 4MHz)
• Built-in YNR ( about fsc±1MHz)
• Gamma correction(for R/G/B signals)
[Deflection Block]
• Analog(conventional) sync separation
• Double AFC Circuit
• Built-in Horizontal reference Oscillator
• HD and VD pulse by Countdown
• Built-in digital Vramp generator
=>
=>
=>
=>
Better performance by abundant experience
Stable Horizontal scanning
No ceramic resonator and Adjustment free
Stable HD&VD
2
[List of main I C bus controllable Items]
• Chip
: Power-down mode
• Analog Input Stage
: CVBS/Y&C Input SW
• Luminance Processing : Sharpness, Blackstretch
• Chroma Processing
: Color, Tint, Killer level
• RGB Matrix
: ACL, OSD Input Level, Contrast, Brightness
• Analog Output Stage
: Drive adj.(R/G/B), Cutoff adj.(R/G/B)
• Deflection Block
: H-Phase, V-size, V-shift, V-Linearity
MITSUBISHI
6
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
ASIC Block Detailed Diagram
MITSUBISHI
7
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
Function and Outline of ASIC Block
Chip
Power down mode : 3 modes [ PD0 & PD1 & PD2 ]
Service SW
: stop of Vertical(Vramp) output ( For cutoff adjustment )
Analog Block
• Input stage => CVBS&Y/C input signals
Input level (CVBS) : 1.23Vp-p (173IRE) @max. / 1.0Vp-p @typ.
Input level (Y/C)
: Y:1.00Vp-p (140IRE) @typ./ C:0.7Vp-p @typ.
• Output stage => RGB output signals
Output level
: 0.7
Vp-p (typ.)
Drive(R&G&B)
: -3 to +4 dB
by 7bit
(White Balance)
Cutoff(R&G&B)
: 0.5
V
by 9bit
(Start lighting point)
Digital Block
• 2DYCS
Adaptive YC separation by using of 1H line memory and original algorithm
• Luminance processing
Contrast
: 0 to 200 LSB
by 7bit
Brightness
: -20 to 20
LSB
by 8bit (Pedestal DC level)
Sharpness
: 0 to 3
dB
by 5bit (by 0, 70, 140, 210ns)
Delay adjustment : 0 to 210
ns
by 2bit(70ns step) to Chroma signal
Blackstretch
: 3 selectable stretch point
[ Stretch areas ( 0 to 25/30/40IRE ), Through areas ( 25/30/40IRE ~ ) ]
4 selectable blackstretch curves ( 1/4, 2/4, 3/4, 4/4)
• Chroma processing
Tint
: -45 to 45
degree by 7bit => about 0.7 degree
: Variable demodulator (R-Y) axis
(-22.5 to +22.5 degree by 6bit => about 0.7 degree)
Color
: 0 to 200
%
by 7bit
• RGB matrix
ACL
EXT/RGB
BlueBack
Mute
Neck Protector
Deflection Block
• Horizontal Output
AFC2 phase
Hold => Shut down
AFC1 gain
• Vertical Output
V position
V size
Linearity
: Matrix(R-Y signal) ratio selectable (12/8, 13/8, 14/8)
2
: Automatic Contrast Limiter by MCU port(ADC) and I C bus
: clip to 7LSB @ data < 0Fh
: ON/OFF selectable
: ON/OFF of R/G/B output
: R/G/B output to zero( no signal)
: +5 to -5µs by 5bit
: fh@Hold-down : in about 16.5KHz => fh@Shutdown : H-STOP
: Normal/High selectable for VTR skew
: 0 to 16 H by 3 bit => 2H unit(connected with BLK)
: 1.4 to 2.6 V by 7bit
: 0 to 30 % by 7bit
MITSUBISHI
8
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
Application Examples
5V
SW REG
+200V
REG
ACL In
0.1u
FBT
470p
2K
15p
15p
0.1u
80
1
79
78
77
76
75
74
74
73
71
72
70
69
67
68
66
65
P00/PWM0
Vss
64
470p
0.1u
2
FILT
P14/SDA2
63
3
VCC
P13/SDA1
62
4
P27/Xcout
P12/SCL2
61
5
P26/FSCin
P11/SCL1
60
6
Reset In
P10/OUT2
59
7
P22/Sin/AD8
8
P21/Sout/AD7
9
Reset
MCU
P31/Bout
58
P30/Gout
57
P20/SCLK/AD6
P53/OUT1
56
10
P15/AD1/INT3
P52/Rout
11
P16/AD2/TIM2 (Int. Mon. In/Out)
12
Vss(Dig)
13
CLK-2 Out
14
Vdd(Dig)
15
CLK(fsc) Out
10K
10K
SDA
SCL
POWER ON H
55
0.01u
1M
P51/Vsync
P50/Hsync In/out
54
53
0.1u
470p
5V
VD out
51
F.B in
50
G(OSD) in
49
B(OSD) in
48
17
Sync Sep. In
18
CVBS(x2) Out
H.T in
47
19
Vdd(Input)
SCL
46
20
TV in
SDA
45
H OUT
44
ASIC
0.1u
560
3.3V
R(OSD) in
Digital Block
Reset In
16
52
0.1u
Video det out
(1.23Vp-p)
EXT In
(1.23Vp-p)
21
Vss(Input)
22
EXT in
23
Vrt
24
Yin
Analog Block
0.1u
FBP IN
43
Vdd(Def)
42
Vss(Def.)
41
H-Pulse Out
FBP in
0.1u
0.1u
Y In
(1.00Vp-p)
5V
NECK PRO
25
0.01u
26
27
28
29
30
31
32
33
34
35
36
37
38
39
39
40
C In
(0.70Vp-p)
0.1u
0.1u
5V
3.3V
-
150V
DY
1.5K
5V
REG
3.3V
REG
9V
REG
to H DRIVE
1.5K
FBT
1.5K
MITSUBISHI
9
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
Electrical characteristics
(Ta=25ºC, Vdd=5.0V, 3.3V)
Symbol
Parameter
Test
point
Input signal
Pins
SG
Limits
Unit
Min.
Typ.
Max.
Remarks
ICC
Standard conditions
ICC50
5.0V supply current
-
-
3,14,
33,42
102
116
130
mA
Supply of MCU, Digital, VCXO and
Deflection
ICC33
3.3V supply current
-
-
18, 29
47
56
65
mA
Supply of A/D and D/A
-
-
-
-
-
-
-
2AGTV Video SW output level (TV
input)
26
SG.A
18
1.5
1.7
1.9
Vpp
2AGEV Video SW output level
(External input)
20
SG.A
18
1.5
1.7
1.9
Vpp
Vtyp
Video standard output
26
SG.A 28,30,
32
590
740
890
mVpp
FBY
Video frequency
characteristics
26
SG.B 28,30,
32
-3
0
3
dB
f=5MHz
Y/C1
Y/C separation function 1
26
SG.E 28,30,
32
-
-30
-20
dB
feb=fec=fsc
Y/C2
Y/C separation function 2
26
SG.E 28,30,
32
-3
0
3
dB
feb=fsc, fec=fsc±1/2fH
Y/C3
Y/C separation function 3
26
SG.E 28,30,
32
-
-30
-20
dB
feb=fsc, fec=fsc±fH
YDL0
Y total delay time
26
SG.A 28,30,
32
2.4
3.0
3.6
µsec
YDL1
Y delay time 1
26
SG.A 28,30,
32
50
70
90
nsec YDL1=measure – YDL0
YDL2
Y delay time 2
26
SG.A 28,30,
32
50
70
90
nsec YDL2=measure – YDL1
YDL3
Y delay time 3
26
SG.A 28,30,
32
50
70
90
nsec YDL3=measure – YDL2
GTnor
Video tone control
characteristic 1
26
SG.B 28,30,
32
640
800
960
mV
f=2.5MHz
tone control
GTmax Video
characteristic 2
26
SG.B 28,30,
32
1
2.5
4
dB
f=2.5MHz
GTmin
Video tone control
characteristic 3
26
SG.B 28,30,
32
-7
-4
-1
dB
f=2.5MHz
BLS
Black stretch
characteristic
26
SG.D 28,30,
32
20
50
80
mV
Vy=0.18V,
45H=80h(BLS ON) / 00h(BLS OFF)
HT
Half Tone function
26
SG.A 28,30,
32
-9
-6
-3
dB
conditions of
VIDEO Standard
video character
MITSUBISHI
10
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Symbol
Parameter
Standard condition of
CHROMA chroma parameter
Input signal
Pins
SG
-
-
M65580MAP-XXXFP
Test
point
Limits
Unit
Min.
Typ.
Max.
-
-
-
-
-
Remarks
5DH=03h
CnorR
Chroma standard output
(R-Y)
26
SG.E
28
155
180
205
mV
feb=fec+50kHz
CnorB
Chroma standard output
(B-Y)
26
SG.E
32
275
310
345
mV
feb=fec+50kHz
ACC1
ACC characteristic 1
26
SG.E
28
-3
0
3
dB
Veb, Vec : +6dB of typical input level
ACC2
ACC characteristic 2
26
SG.E
28
-3
0
3
dB
Veb, Vec : -20dB of typical input level
VikN
Killer operation input level
26
SG.E
28
-40
-35
-30
dB
Veb, Vec : variable
KillP
Color residual at Killer on
26
SG.E
28
-
-40
-28
dB
Veb = 0mV
APCU
APC pull-in range (upper)
26
SG.E
28
400
-
-
Hz
feb=fec : variable
APCL
APC pull-in range (lower)
26
SG.E
28
-
-
-400
Hz
feb=fec : variable
DEMR
Demodulated output ratio
26
SG.E 28,32
0.47
0.57
0.67
-
DEMP
Demodulation phase
angle
26
SG.F 28,32
85
90
95
deg
Color control characteristic
Ccon 1 1
26
SG.E
28
160
200
240
%
feb=fec+50kHz
Color control characteristic
Ccon 2 2
26
SG.E
28
-
0
10
%
feb=fec+50kHz
TC1
TINT control characteristic
1
26
SG.F 28,32
30
45
60
deg
TC2
TINT control characteristic
2
26
SG.F 28,32
-60
-45
-30
deg
Fclk
CLK output frequency
26
SG.C
15
3.578
3.579
3.580
MHz
Vclk
CLK output amplitude
26
SG.C
15
350
500
650
mVpp
MITSUBISHI
feb=fec+50kHz
11
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Symbol
Parameter
RGB
Standard condition of
RGB parameter
VPED
Output Pedestal voltage
Input signal
Pins
SG
-
-
M65580MAP-XXXFP
Test
point
-
Limits
Unit
Min.
Typ.
Max.
-
-
-
-
Remarks
26
SG.D 28,30,
32
2.7
3.0
3.3
V
MTXRB Matrix ratio R/B
26
SG.H 28,32
0.74
0.92
1.10
-
MTXGB Matrix ratio G/B
26
SG.H 30,32
0.24
0.33
0.42
-
control
GYmax Contrast
characteristic 1
26
SG.D 28,30,
32
160
200
240
%
Vy =0.286V
Contrast control
characteristic 2
26
SG.D 28,30,
32
-
0
10
%
Vy =0.286V
48,49, SG.G 28,30,
51
32
250
300
350
mV
GYmin
control
GYEclip Contrast
characteristic 5
Lum
max
Vy = 0.0V
Brightness control
characteristic 2
26
SG.D 28,30,
32
100
150
200
mV
control
Lum min Brightness
characteristic 3
26
SG.D 28,30,
32
-200
-150
-100
mV
Vy =0.286V
D(R)1
R Drive control
characteristic 1
26
SG.D
28
1.5
3.5
5.5
dB
Vy =0.286V
D(G)1
G Drive control
characteristic 1
26
SG.D
30
1.5
3.5
5.5
dB
Vy =0.286V
D(B)1
B Drive control
characteristic 1
26
SG.D
32
1.5
3.5
5.5
dB
Vy =0.286V
D(R)2
R Drive control
characteristic 2
26
SG.D
28
-4.6
-2.6
-0.6
dB
Vy =0.286V
D(G)2
G Drive control
characteristic 2
26
SG.D
30
-4.6
-2.6
-0.6
dB
Vy =0.286V
D(B)2
B Drive control
characteristic 2
26
SG.D
32
-4.6
-2.6
-0.6
dB
Vy =0.286V
C(R)1
R Cut off control
characteristic 1
26
SG.D
28
210
260
310
mV
Vy =0.286V
C(G)1
G Cut off control
characteristic 1
26
SG.D
30
210
260
310
mV
Vy =0.286V
C(B)1
B Cut off control
characteristic 1
26
SG.D
32
210
260
310
mV
Vy =0.286V
C(R)2
R Cut off control
characteristic 2
26
SG.D
28
-310
-260
-210
mV
Vy =0.286V
C(G)2
G Cut off control
characteristic 2
26
SG.D
30
-310
-260
-210
mV
Vy =0.286V
C(B)2
B Cut off control
characteristic 2
26
SG.D
32
-310
-260
-210
mV
Vy =0.286V
OSD(R) OSD (R) output level
51
SG.G
28
500
600
700
mVpp
OSD(G) OSD (G) output level
49
SG.G
30
500
600
700
mVpp
OSD(B) OSD (B) output level
48
SG.G
32
500
600
700
mVpp
speed characteristic 48,49, SG.G 28,30,
SOSD1 OSD
1
51
32
-
100
200
nsec
speed characteristic 48,49, SG.G 28,30,
SOSD2 OSD
2
51
32
-
100
200
nsec
voltage between R
OFF(R) Offset
and OSD(R)
-
-
-
-50
0
50
mV
Difference at pedestal level
voltage between G
OFF(G) Offset
and OSD(G)
-
-
-
-50
0
50
mV
Difference at pedestal level
voltage between B
OFF(B) Offset
and OSD(B)
-
-
-
-50
0
50
mV
Difference at pedestal level
26
SG.A
40
1.0
1.3
1.6
V
NECK
Neck protector function
threshold voltage
MITSUBISHI
while monitoring at pins 28, 30, 32
12
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Symbol
Parameter
Input signal
Pins
SG
M65580MAP-XXXFP
Test
point
Limits
Unit
Min.
Typ.
Max.
Remarks
DEF
Standard condition of
defrection parameter
-
-
-
-
-
-
-
fH1
Horizontal free-running
frequency 1
-
-
44
15.53
15.73
15.93
kHz
fH2
Horizontal free-running
frequency 2
-
-
44
13.72
14.32
14.92
kHz
fH3
Horizontal free-running
frequency 3
-
-
44
17.25
17.85
18.45
kHz
FPHU
Horizontal pull-in range
(upper)
17
SG.I
44
250
500
-
Hz
Vary frequency of input signal.
FPHL
Horizontal pull-in range
(lower)
17
SG.I
44
-
-500
-250
Hz
Vary frequency of input signal.
HPV
Horizontal pulse amplitude
26
SG.A
44
4.0
4.5
5.0
V
HPTW
Horizontal pulse width
26
SG.A
44
19.3
22.3
25.3
µsec
HPD
Horizontal pulse duty
cycle
26
SG.A
44
30
35
40
%
HPT1
Horizontal pulse timing 1
26
SG.A
44
8.7
10.7
12.7
µsec
HPT2
Horizontal pulse timing 2
26
SG.A
44
2.2
4.2
6.2
µsec
HPT3
Horizontal pulse timing
variable range
26
SG.A
44
4.5
6.5
8.5
µsec HPT2 – HPT1
down function
HDOWN Hold
threshold voltage
26
SG.A
36
3.0
3.1
3.2
V
while monitoring at pin 44
down function
SDOWN Shut
threshold voltage
26
SG.A
36
3.3
3.5
3.7
V
while monitoring at pin 44
fV
Vertical free-running
frequency
-
-
38
55
60
65
Hz
SVC
Service mode function
-
-
38
2.5
2.8
3.1
V
FPVU
Vertical pull-in frequency
(upper)
17
SG.J
38
-
-
63
Hz
Vary frequency of input signal.
FPVL
Vertical pull-in frequency
(lower)
17
SG.J
38
57
-
-
Hz
Vary frequency of input signal.
VRsi 1
Vertical ramp size
26
SG.A
38
2.1
2.5
2.9
Vpp
ramp size control
VRsc 1 Vertical
range 1
26
SG.A
38
20
27
35
%
ramp size control
VRsc 2 Vertical
range 2
26
SG.A
38
-35
-27
-20
%
VLin 1
Vertical ramp Linearity
control range 1
26
SG.A
38
-5
0
5
%
VLin 2
Vertical ramp Linearity
control range 2
26
SG.A
38
19
24
29
%
ramp position
VRpo 1 Vertical
control range 1
26
SG.A
38
0
50
200
µsec
ramp position
VRpo 2 Vertical
control range 2
26
SG.A
38
790
940
1090
µsec (Measured value) – (Vrpo 1)
VW
26
SG.A
52
0.35
0.53
0.65
msec
VBLKW Vertical blanking width
26
SG.A 28,30,
32
1.52
1.64
1.76
msec
Minimum vertical sync
detection width
26
SG.A
13
18
23
µsec
WVSS
Vertical pulse width
11
MITSUBISHI
13
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
Electrical characteristics (MCU part)
(Vcc=5V±10%, Vss = 0V, f(XIN)=8MHz, Ta=–20˚C to 65˚C, unless otherwise noted)
Symbol
Parameter
Test conditions
VCC = 5.5 V,
f(XIN) = 8 MHz
ICC
Power source current
VOH
HIGH output voltage
VOL
LOW output voltage
P10–P16, P20–P27,
P30, P31, P52, P53
P00–P07, P10,
P15, P16, P20–P27,
P30, P31, P52, P53
LOW output voltage
P11–P14
IIZH
IIZL
RBS
OSD OFF
Data slicer OFF
OSD ON
VCC = 4.5 V
Hysteresis (See note 1)
RESET, P50–P51, INT1, INT2,
INT3, TIM2, TIM3, SIN, SCLK, SCL1,
SCL2, SDA1, SDA2
VCC = 5.0 V
HIGH input leak current
P00–P07, P10–P16, P20–P27,
P50, P51, RESET
LOW input leak current
P00–P07, P10–P16, P20–P27,
P50, P51, RESET
I 2C-BUS • BUS switch connection resistor
(between SCL1 and SCL2, SDA1 and SDA2)
15
30
30
45
60
200
Unit
Test
circuit
µA
1
VCC = 5.5 V, f(XIN) = 8 MHz
VCC = 5.5 V, f(XIN) = 0,
f(XCIN) = 32 kHz,
Low-power dissipation mode set
(CM5 = "0", CM6 = "1")
VCC = 5.5 V, f(XIN) = 0,
f(XCIN) = 0
VCC = 4.5 V
IOH = –0.5 mA
VCC = 4.5 V
IOL = 0.5 mA
Limits
Typ. Max.
mA
System operation VCC = 5.5 V, f(XIN) = 0,
f(XCIN) = 32 kHz,
OSD OFF, Data slicer OFF,
Low-power dissipation mode set
(CM5 = "0", CM6 = "1")
Wait mode
VT+ – VT–
Min.
2
4
mA
25
100
µA
1
10
2.4
V
0.4
2
V
0.4
0.6
IOL = 3 mA
IOL = 6 mA
0.5
1.3
V
3
VCC = 5.5 V
VI = 5.5 V
5
µA
4
VCC = 5.5 V
VI = 0 V
5
µA
4
VCC = 4.5 V
130
5
Notes 1: P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these
pins are used as multi-master I2C-BUS interface ports. P20–P22 have the hysteresis when these pins are used as serial I/O pins.
2: Connect 0.1µF or more capacitor externally between the power source pins VCC–VSS so as to reduce power source noise.
Also connect 0.1µF or more capacitor externally between the pins VCC–CNVSS.
3: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz.
4: Pin names in each parameter is described as bellow.
(1) Dedicated pin: dedicated pin names.
(2) Double-/triple-function ports
• When the same limits: I/O port name.
• When the limits of functions except ports are different from I/O port limits: function pin name.
MITSUBISHI
14
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
2
I C Bus Table
SLAVE ADDRESS= BAH(WRITE), BBH(READ)
A6
1
A5
0
A4
1
A3
1
A2
1
A1
0
A0
1
R/W
1/0
D5
D4
D3
D2
D1
D0
WRITE TABLE(input bytes)
SUB ADDRESS
HEX
BIN
00H 00000000
01H 00000001
02H 00000010
04H 00000100
05H 00000101
06H 00000110
07H 00000111
08H 00001000
09H 00001001
0AH 00001010
0BH 00001011
0CH 00001100
0DH 00001101
0EH 00001110
DATA
D7
D6
(not asigned)
0
0
0
X-ray Enable
YUV input
Y/C input
0
0
0
Ped Clamp
(not asigned)
0
0
0
Sharpness Delay (Front)
V1
V0
V1
Sharpness Delay (Rear)
V1
V0
V1
(not asigned)
Y DL Time Adj.
V0
V0
V0
(not asigned)
V0
V0
V0
(not asigned)
V0
V0
V1
(not asigned)
V0
V0
V1
(not asigned)
V0
V0
V1
Half Tone
V0
V0
V0
RGB Matrix Ratio
V1
V0
V0
OSD Comp
V0
V0
V0
15H 00010101
V1
V0
V0
(not asigned)
H Free
AFC1 Gain
0
0
0
(not asigned)
(for evaluation)
0
0
0
(not asigned) Black Stre. SW
V0
V1
V0
RGB Mute
(inhibited)
1
0
0
Service SW
V-Shift
0
0
0
V-Blanking Stop
0
1
0
V-Ramp Invert
1
1
1
16H 00010110
V0
CutOff(R) MSB
17H 00010111
V0
V0
V0
V0
V0
18H 00011000
V0
CutOff(G) MSB
19H 00011001
V0
V0
V0
V0
V0
1AH 00011010
V0
V0
0FH 00001111
10H 00010000
11H 00010001
12H 00010010
13H 00010011
14H 00010100
V0
CutOff(B) MSB
1BH 00011011
V0
V0
V0
(not asigned)
1CH 00011100
0
0
1DH 00011101
0
0
0
I/M(D) Enable
0
51H 01010001
0
0
0
(not asigned)
H Stop
Power Down Mode
0
0
0
1
0
EXT input
TV input
Y/C through
(for evaluation)
0
1
0
0
0
VRT Voltage
Sync-tip Clamp
0
1
0
0
0
Shrapness Gain (Front)
V0
V0
V0
V0
V0
Shrapness Gain (Rear)
V0
V0
V0
V0
V0
YNR SW
YNR Limitter Level
V0
V0
V0
V0
V0
Sharpness Limitter Level
V1
V0
V1
V0
V1
Tint Control
V0
V1
V0
V0
V1
Color Control
V0
V1
V0
V0
V0
Contrast Control
V1
V1
V0
V1
V1
OSD Level (R)
V1
V1
V1
V1
V0
OSD Level (G)
V1
V1
V1
V1
V0
OSD Level (B)
V1
V1
V1
V1
V0
Brightness Control
V0
V0
V0
V0
V0
H Phase Control
0
1
0
0
0
2D Y/C
(for evaluation)
0
0
0
0
0
(for evaluation)
V0
V0
V0
V0
V0
Gamma Control
0
0
0
0
0
Hold Down Level
(inhibited)
1
0
0
0
0
V-Ramp Size
0
0
0
0
0
V-Ramp Linearity
1
1
1
1
1
Cut Off (R)
V0
V0
V0
V0
V0
Drive (R)
V0
V0
V0
V0
V0
Cut Off (G)
V0
V0
V0
V0
V0
Drive (G)
V0
V0
V0
V0
V0
Cut Off (B)
V0
V0
V0
V0
V0
Drive (B)
V0
V0
V0
V0
V0
Intelligent Monitor (Analog)
0
0
0
0
0
Intelligent Monitor (Digital)
0
0
0
0
0
H VCO Adjust
0
0
0
0
0
INITIAL
02H
08H
08H
A0H
A0H
00H
15H
29H
28H
3BH
1EH
5EH
0EH
80H
08H
00H
40H
80H
10H
40H
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
NOTE: V0 / V1 ==> V- LATCH BIT
READ TABLE(output bytes)
SUB ADDRESS
60H
61H
62H
63H
D7
01100000
KILLER
01100001
01100010 B2 ROM MSB
01100011
D6
D5
D4
H COINCI
V COINCI
B_W
D3
IIC_STILL
B2 ROM
(not asigned)
D2
D1
D0
MV_180
DET NZ
K_MONI
BLKDETV
C Gain
(not asigned)
MITSUBISHI
15
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
Bus function
WRITE
FUNCTION
BIT SUB DATA
ADD
H STOP
Power Down
Input Video SW
X-ray Enable
Y/C through
Sync-tip Clamp
Ped Clamp
VRT Voltage
Sharpness Gain (Front)
Sharpness Delay (Front)
Sharpness Gain (Rear)
Sharpness Delay (Rear)
YNR SW
YNR Limiter Level
Y DL Time Adj.
Sharpness Limiter Level
Tint Control
Color Control
Contrast Control
OSD Level (R)
Half Tone
OSD Level (G)
RGB Matrix Ratio
OSD Level (B)
OSD Comp
Brightness Control
AFC2 H Phase
AFC1 Gain
H-free
2D Y/C
Black Stretch SW
Gamma Control
RGB Mute
Hold Down Level
V Shift
Service SW
V-Ramp Size
Test
V-Ramp Linearity
V-Ramp Invert
Cut Off(R)
1
2
4
1
1
3
1
2
6
2
6
2
7
1
2
6
7
7
7
6
2
6
2
6
2
8
5
1
1
1
1
1
1
3
3
1
7
1
7
1
9
Drive(R)
Cut Off(G)
7
9
Drive(G)
Cut Off(B)
7
9
Drive(B)
Intelligent Monitor (Analog)
Intelligent Monitor (Digital)
Intelligent Monitor(D) Enable
H VCO Adj.
7
4
5
1
8
00H
00H
01H
01H
01H
02H
02H
02H
04H
04H
05H
05H
06H
06H
06H
07H
08H
09H
0AH
0BH
0BH
0CH
0CH
0DH
0DH
0EH
0FH
0FH
0FH
10H
11H
12H
12H
13H
13H
13H
14H
14H
15H
15H
16H
17H
17H
18H
19H
19H
1AH
1BH
1BH
1CH
1DH
1DH
51H
D0
D1-D2
D3-D6
D7
D2
D0-D2
D7
D3-D4
D0-D5
D6-D7
D0-D5
D6-D7
D4
D0-D3
D5-D6
D0-D5
D0-D6
D0-D6
D0-D6
D0-D5
D6-D7
D0-D5
D6-D7
D0-D5
D6-D7
D0-D7
D0-D4
D5
D6
D4
D6
D0-D3
D7
D0-D2
D4-D6
D3
D0-D6
D7
D0-D6
D7
D0-D7
D7
D0-D6
D0-D7
D7
D0-D6
D0-D7
D7
D0-D6
D0-D3
D0-D4
D5
D0-D7
60H
60H
60H
60H
60H
60H
60H
60H
61H
62H
62H
63H
D0
D1
D2
D3
D4
D5
D6
D7
D0-D7
D7
D0-D1
D4-D7
DISCRIPTION
Horizontal output switch (0: H OUT, 1: H STOP)
Power down mode control (0: normal, 1: PD0, 2: PD1, 3: PD2)
Video SW Selector (1: TV, 2: EXT, 4: Y/C input, 9: YUV input)
X-ray protect function switch (0: X-ray Protect OFF, 1: X-ray Protect ON)
Y/C separation input switch (0: Y/C Sep ON, 1: Y/C Sep. through)
Sync-tip clamp switch (0: Clamp ON, 1: TV clamp OFF, 2: EXT clamp OFF, 4: Y clamp OFF)
Pedestal clamp switch (0: Pedestal clamp OFF, 1: Pedestal clamp ON)
Reference voltage adjustment for A/D
Over-shoot gain control by 6bit
Over-shoot width control (0: 0ns, 1: 70ns, 2: 140ns 3: 210ns)
Pre-shoot gain control by 6bit
Pre-shoot width control (0: 0ns, 1: 70ns, 2: 140ns 3: 210ns)
YNR control switch (0: YNR OFF, 1: YNR ON)
YNR limiter level control
Delay time adjustment of luminance signal (0: 0ns, 1: 70ns, 2: 140ns 3: 210ns)
Maximum level control of sharpness
Tint Control by 7bit
Color Saturation control by 7bit
Contrast control by 7bit
Digital OSD (R) level adjustment by 6bit
Setting of Half Tone mode
Digital OSD (G) level adjustment by 6bit
RGB Matrix ratio control
Digital OSD (B) level adjustment by 6bit
Digital OSD threshold voltage control of input signal
Brightness control by 8bit
Horizontal phase adjustment by 5bit
Horizontal AFC gain switch (0: Low, 1: High)
Horizontal forced free-running mode switch (0: OFF, 1: Forced Free-running)
Y/C separation mode switch (0: Y/C Sep ON, 1: Y/C Sep. through)
Black Stretch function ON/OFF switch (0: OFF, 1: ON)
RGB gamma threshold control (0:Gamma OFF)
RGB signal mute ON/OFF switch (0: Mute 1: RGB output)
Hold Down level adjustment by 3bit
V RAMP start timing adjustment 2Line/Step
Service mode switch (0: Vertical output ON, 1: Vertical output OFF)
V-Ramp amplitude adjustment by 7bit
No use for customer (Test mode)
V-Ramp linearity adjustment by 7bit
V-Ramp polarity switch
R OUT pedestal level adjustment by 9bit
R OUT amplitude adjustment by 7bit
G OUT pedestal level adjustment by 9bit
G OUT amplitude adjustment by 7bit
B OUT pedestal level adjustment by 9bit
B OUT amplitude adjustment by 7bit
Intelligent Monitor (Analog) mode selector
Intelligent Monitor (Digital) mode selector
Intelligent Monitor (Digital) function switch (0: OFF, 1: ON)
H VCO free-running frequency adjustment by 8bit
INITIAL NOTE
0
01
0001
0
0
000
0
01
100000
10
100000
10
0
0000
00
010101
0101001
0101000
0111011
011110
00
011110
10
011110
00
10000000
01000
0
0
0
0
0000
1
000
001
0
1000000
0
1111111
1
00000000
0
0000000
00000000
0
0000000
00000000
0
0000000
0000
00000
0
00000000
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
Read
K_MONI
DET_NZ
MV_180
IIC_STILL
B_W
V COINCI
H COINCI
KILLER
B2ROM
1
1
1
1
1
1
1
1
9
C Gain
BLKDETV
2
4
C-processor Killer det. output (1: C-pro Killer ON)
Noise Killer det. output (1: Noise Killer ON)
Reversed Burst signal (all reversed) det. output (1: Reversed Burst)
VCR Still mode det. output (1: Still mode)
PLL Killer (Chroma) det. output (1: PLL Killer ON)
Vertical Coincidence det. output (1: V Coincident)
Horizontal Coincidence det. output (1: H Coincident)
Color/Killer condition (1: color output, 0: Killer (color off) )
B2ROM output
ACC amplifier status
Black det. output of Black Stretch circuit
MITSUBISHI
16
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
M65580MAP I2C bus Standard data
Sub address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
data
00
08
08
21
C0
C0
00
15
40
40
40
1E
9E
1E
80
10
10
4A
8D
00
40
40
00
C0
00
C0
00
C0
00
00
Sub address
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
data
20
05
04
81
8D
63
79
50
55
25
21
19
B3
0F
06
08
00
01
C0
04
64
3D
15
00
83
00
A0
00
15
01
6E
38
Sub address
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
MITSUBISHI
data
00
00
00
35
22
94
14
A6
00
A6
00
00
00
80
17
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
DESCRIPTION OF PIN
Pin No.
1
Name
Peripheral circuit of pins
Note
Power source for
MCU.
Vss (MCU)
0V
2
2
FILT
Y
Power source for
MCU.
3
Vcc (MCU)
5.0V ± 5%
4
P27/XCOUT
5
P26/FSCIN/
XCIN
4
5
MITSUBISHI
18
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
M65580MAP-XXXFP
Peripheral circuit of pins
Name
Note
CMOS INPUT
Impedance>100k
6
Y
RESETB
VOL = 0V :
6
Reset state
VOH = 5V :
Release from Reset
state
CMOS IN/OUT 1
C
7
P22/SIN/AD8
8
P21/SOUT/AD8
9
P20/SCLK/AD6
10
P15/AD1/
INT3/FSCIN
Impedance>100k
(input)
Impedance 250
(output)
A
Y
CMOS IN/OUT 1
C
11
A
11
Impedance>100k
(input)
Impedance 250
(output)
Intelligent monitor
output
(Analog/Digital)
P16/AD2/TIM2
Y
12
Vss (Digital)
0V
MITSUBISHI
19
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
Name
M65580MAP-XXXFP
Note
Peripheral circuit of pins
CMOS IN/OUT 1
C
13
A
13
Impedance>100k
(input)
Impedance<100
(output)
OSD CLK
Y
14
Power source for
Digital block.
Vdd (Digital)
5.0V ± 5%
Impedance 400
ESD PROTECT
15
15
CLK OUT
CMOS INPUT
Impedance>100k
16
VIL = 0V :
Reset state
16
VIH = 5V :
RESET
Release from Reset
state
Y
Sync Sep. input
Impedance=N.A.
ESD PROTECT
17
C.Sync IN
17
DC 2.5V
MITSUBISHI
20
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
Name
M65580MAP-XXXFP
Note
Peripheral circuit of pins
Impedance 150
18
19
CVBS OUT
18
DC : 0.55V (sync)
AC : 1.75Vp-p (typ.)
Power source for
A/D etc.
Vdd (Input)
3.3V ± 5%
20
22
26
21
20
EXT(CVBS) IN
Y IN
TV(CVBS) IN
Impedance=N.A.
22
26
DC : 0.5V (sync)
AC : 1.0Vp-p (typ.)
Power source for
A/D etc.
Vss (Input)
0V
Impedance>50
23
23
VRT
25
VRB
DC : 1.7V (VRT)
0.5V (VRB)
25
Impedance 7.5k
24
24
C IN
DC : 1.0V
AC : 0.286Vp-p
(burst)
MITSUBISHI
21
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
Name
M65580MAP-XXXFP
Peripheral circuit of pins
Note
Impedance 400
27
27
VZ OUT
28
30
32
R OUT
G OUT
B OUT
DC : 2.05V
28
29
Impedance 1k
30
32
DC : 3V (blanking)
Power source for
D/A etc.
Vdd (Output)
3.3V ± 5%
31
Power source for
D/A etc.
Vss (Output)
0V
33
Power source for
VCXO etc.
Vdd (VCXO)
5.0V ± 5%
34
34
Impedance=N.A.
(Additional filter on
PCB board)
APC Filter
DC 2.9V
MITSUBISHI
22
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
Name
M65580MAP-XXXFP
Peripheral circuit of pins
Note
35
35
X'tal
Impedance 1k
Impedance>100k
36
X-ray
Protector
ESD PROTECT
0.0-3.0 : Normal
3.2-3.3 : Hold down
3.7-5.0 : Shut down
36
37
37
AFC1 Filter
Impedance=N.A.
(Additional filter on
PCB board)
DC 2.5V
Impedance 400
38
39
V RAMP OUT
38
HVCO F/B
2.5Vp-p (typ.)
39
Impedance=N.A.
(Additional filter on
PCB board)
DC 3.0V
Impedance 5k
40
Neck
Protector
40
MITSUBISHI
0.0-1.0 : RGB off
1.6-3.0 : Normal
4.0-5.0 : Test mode
23
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
41
Name
M65580MAP-XXXFP
Note
Peripheral circuit of pins
Power source for
Deflection block.
Vss (DEF)
0V
42
Power source for
Deflection block.
Vdd (DEF)
5.0V ± 5%
CMOS IN/OUT 1
C
Impedance>100k
(input)
Impedance<100
(output)
43
A
43
FBP IN
VIL = 0V :
RGB output
VIH = 5V :
Y
Blanking
CMOS IN/OUT 1
C
Impedance>100k
(input)
Impedance<100
(output)
44
A
44
VOL : 0V
VOH : 5V
H OUT
Y
CMOS IN/OUT 2
Impedance>100k
(input)
Impedance<100
(output)
C
A
45
45
VIL : 0V
VIH : 5V
SDA
Y
s
MITSUBISHI
24
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
Name
M65580MAP-XXXFP
Note
Peripheral circuit of pins
CMOS Schmitt IN
Impedance>100k
46
SCL
Y
s
46
V IL : 0V
V IH : 5V
CMOS IN/OUT 1
C
47
A
47
Impedance>100k
(input)
Impedance<100
(output)
VIL = 0V :
Half Tone IN
RGB output
VIH = 5V :
Half tone on
Y
CMOS IN/OUT 1
C
48
49
48
49
51
OSD(B) IN
OSD(G) IN
OSD(R) IN
51
A
Impedance>100k
(input)
Impedance<100
(output)
VIL : 0V
VIH : 5V
Y
C
50
A
50
Fast BLK IN
CMOS IN/OUT 1
Impedance>100k
(input)
Impedance<100
(output)
VIL = 0V :
RGB output
Y
MITSUBISHI
VIH = 5V :
OSD output
25
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
Name
M65580MAP-XXXFP
Note
Peripheral circuit of pins
CMOS IN/OUT 1
C
52
A
52
Impedance>100k
(input)
Impedance<100
(output)
VOL : 0V
VOH : 5V
V sync OUT
Y
CMOS IN/OUT 1
C
53
A
53
Impedance>100k
(input)
Impedance<100
(output)
VOL : 0V
VOH : 5V
H sync OUT
Y
CMOS INPUT
Impedance>100k
54
Y
P51/VSYNC
54
CMOS IN/OUT 1
Impedance>100k
(input)
Impedance<100
(output)
C
55
56
57
58
59
P52/R
P53/OUT1
P30/G
P31/B
P10/OUT2
A
Y
MITSUBISHI
26
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
M65580MAP-XXXFP
Note
Peripheral circuit of pins
Name
CMOS IN/OUT 1
C
60
P11/SCL1
61
P12/SCL2
62
P13/SDA1
63
P14/SDA2
Impedance>100k
(input)
Impedance 250
(output)
A
Y
CMOS IN/OUT
64
P00/PWM0
65
P01/PWM1
66
P02/PWM2
67
P03/PWM3
68
P04/PWM4
Impedance>100k
(input)
Impedance 250
(output)
Y
CMOS IN/OUT
Impedance>100k
(input)
Impedance 250
(output)
69
P05/AD3
70
P06/INT2/AD4
Y
CMOS IN/OUT
71
71
P07/INT1
Impedance>100k
(input)
Impedance 250
(output)
Y
MITSUBISHI
27
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
Name
M65580MAP-XXXFP
Note
Peripheral circuit of pins
CMOS IN/OUT 1
C
Impedance>100k
(input)
Impedance<100
(output)
A
72
P23/TIM3
73
P24/TIM2
Y
CMOS IN/OUT 1
C
74
A
74
Impedance>100k
(input)
Impedance 250
(output)
P25/AD5
Y
Impedance=N.A.
(Additional filter on
PCB board)
75
75
HLF
76
VHOLD
76
77
CV IN
77
MITSUBISHI
28
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
Pin No.
Name
M65580MAP-XXXFP
Note
Peripheral circuit of pins
CMOS IN/OUT
Impedance>100k
(input)
Impedance 250
(output)
78
78
CN VSS
79
X IN
80
X OUT
79
80
MITSUBISHI
29
Preliminary
Mitsubishi Semiconductor<Digital IC>
Note : This is not a final specification.
Some of information in this document are subject to changes.
Digital Video/Chroma/Deflection+MCU
M65580MAP-XXXFP
MEMORY MAP
Mask ROM version
000016
00BF16
00C016
00FF16
010016
RAM
(1152 bytes)
01FF16
020016
020F16
1000016
Zero page
SFR1 area
Not used
SFR2 area
Not used
030016
032016
ROM correction function
Vector 1: addresses 030016
Vector 2: addresses 032016
05BF16
OSD RAM
(128 bytes)
(note)
Not used
OSD ROM
(10K bytes)
080016
087F16
1140016
13BFF16
Not used
600016
Not used
Not used
ROM
(40K bytes)
FF0016
FFDE16
Interrupt vector area
Special page
FFFF16
1FFFF16
MITSUBISHI
30