RENESAS M65582AMF

M65582AMF-XXXFP
NTSC TV Signal Processor with MCU
REJ03F0093-0100Z
Rev.1.0
Sep.19.2003
Features
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1package solution with TV baseband signals (Video and Chroma) processor, deflection and 8bit MCU
High quality picture by 2 Dimension Adaptive Y/C Separation of 3 Line type
Built-in VM (Velocity Modulation) circuit emphasizing the picture outline by the changing of the Scanning Speed
Built-in the correction circuits of the picture distortion which is EAST-WEST function etc. for Flat TV
Available to use the software for best saled MCU M37272
Available to input External Video signal, S Video signal and Component Video signal
High performance OSD function with CCD and Half Tone Display
Analog Video Switch with 5 Video Inputs Composite Video : 3ch, S Video : 1ch, Component Video : 1ch
Built-in a high performance Blackstrech
Built-in YNR
Built-in 8bit MCU core M37272
ROM : 60Kbyte, RAM : 2048byte
Applications
NTSC color television receivers
Rev.1.0, Sep.19.2003, page 1 of 45
P27/Xcout
CNVss
Xin
Xout
VSS(MCU)
VDD(MCU)
FILT
HLF
VHOLD
CVIN
RESET
VSS(Digital)
VDD(Digital)
DCT FILTER
CVBS(X2) OUT
TV1 IN
VDD(Input)
Y(Y/C) IN
C(Y/C) IN
VSS(Input)
TV2 IN
VRT
TV3 IN
VRB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P02/PWM2
P01/PWM1
P00/PWM0
P10
P43
P42
P41
P40
P11/SCL1
P12/SCL2
P13/SDA1
P14/SDA2
ACL IN
AKB IN
H OUT
FBP IN
H CORRE
E-W
HVCO FB
VRAMP(+)
VRAMP(-)
VRAMP C
VDD(DEF)
AFC1 FILTER
M65582AMF-XXXFP
Pin Configuration
P44
P03/PWM3/AD1
P45
P04/PWM4/AD2
P05/AD3
P06/INT2/AD4
P07/INT1
P15
P16
P20/SCLK/AD5
P21/Sout/AD6
P22/Sin/AD7
P23/TIM3
P24/TIM2
P25/INT3
P26/Xcin
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
M65582AMF-XXXFP
Rev.1.0, Sep.19.2003, page 2 of 45
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
APC FILTER
TEST
N.C.
XTAL(NTSC)
VSS(DEF)
B OUT
VDD(VCXO)
G OUT
VSS(Output)
R OUT
VDD(Output)
VM
VZ OUT
V(YUV) IN
U(YUV) IN
Y(YUV) IN
M65582AMF-XXXFP
H OUT
HVCO F/B
37 38 39
FBP IN
46
VDD(Def)
36 42 49 50 41
VSS(Def)
TEST
N.C.
XTAL(NTSC)
34 40
AFC1 FILTER
51 52
APC FILTER
VDD(VCXO)
AKB IN
ACL IN
Block Diagram (Whole)
VRB
24
48
VRT
22
47
H Correction
E-W OUT
VRAMP C
TV1/2/3 IN / YC IN / YUV IN
43
V(YUV) IN
27
45
VRAMP(+)
U(YUV) IN
26
44
VRAMP(-)
Y(YUV) IN
25
C(Y/C) IN
19
Y(Y/C) IN
18
TV3 IN
VRAMP
OUT
12
VSS(Digital)
13
VDD(Digital)
23
32
VSS(Output)
TV2 IN
21
30
VDD(Output)
TV1 IN
SIGNAL PROCESSOR
35
B OUT
VDD(Input)
17
33
G OUT
31
R OUT
FILT
7
CVIN
10
VHOLD
9
HLF
8
VD PLS
Fast BLK
6
VZ OUT
R/G/B
OUT
VM OUT
29
RGB OUT
(OSD)
5
Half Tone
VSS(MCU)
VDD(MCU)
SDA
15
Intelligent
Monitor
SCL
14
RESET
DCT FILTER
CVBS(X2) OUT
HD PLS
28
20
OSD CLK
16
VSS(Input)
2
CNVSS
3
XIN
4
XOUT
11
MCU CORE
M37273
CCD
RESET IN
78
P24/TIM2
77
P23/TIM3
73
P16
P22/SIN/AD7
64
75
P21/SOUT/AD6
P01/PWM1
63
74
P20/SCLK/AD5
P00/PWM0
62
72
P15
P12/SCL2
55
71
P07/INT1
P14/SDA2
53
70
P06/INT2/AD4
I/O PORT
Rev.1.0, Sep.19.2003, page 3 of 45
P05/AD3
P04/PWM4/AD2
P45
P44
P03/PWM3/AD1
P43
P42
P41
P40
P11/SCL1
P25/INT3
P13/SDA1
P26/XCIN
P27/XCOUT
61 1 80 79 54 56 57 58 59 60 66 65 67 68 69
P10
EEPROM
76
P02/PWM2
Rev.1.0, Sep.19.2003, page 4 of 45
19
25
26
27
C IN
0.7Vp-p
Y IN
1.0Vp-p
U IN
0.7Vp-p
V IN
0.7Vp-p
52
ACL IN (0-3.3V)
Int. Mon Out
(ANA&DIG)
51
AKB IN (0-3.3V)
Int. Mon out
To MCU (Ana & Dig)
Reset
SCL (5V I/F)
18
Y IN
1.0Vp-p
From MCU
23
TV3 IN
1.23Vp-p
SDA (5V I/F)
21
TV2 IN
1.23Vp-p
DCT
* (AKB/ACL/
DCT SW)
* (Monitoring)
* IIC BUS CNTL
*Input
Selector
SEL
CVBS
or
Y/C
or
YUV
to
TV1-3
&
Y/C
&
YUV
Vdd(IVCXO)
=3.3V
Low-speed
10bit-A/D
34
8bit-A/D
37 38 39 40
VCXO
VCXO
4fsc
(Reference CLK)
*
22
8bit-A/D
24
VRB=0.5V VRT=1.7V
* C or U+V
SW
ACC
Amp
CVBS
or Y
X2
14 15
to
RGBMTX
* AKB&ABCL&DCT
Intelligent
Monitoring
IIC
Receiver
Clamp
Clamp
Clamp
Bias
Clamp
Clamp
Clamp
Clamp
20
Vss(Input)
16
17
DCT Filter
13
2DYCS
by 3lines
1H DL
SW
C.P.
P.D.
Burst
Gate
Sync
Separator
* (Slice Level)
* (CVBS/YC/YUV SW)
"OFF"@Y/C&YUV input
1/4
12
* (Sharpness, Y-Delay,
Black Stretch)
* (Drive, Cutoff)
Cutoff
10bit-D/A
Drive
Cutoff
10bit-D/A
Drive
Cutoff
10bit-D/A
Drive
8bit-D/A
Ref. Current
To MCU
To MCU
49
48
50
46
41
35
33
31
29
32
30
E-W
Gen.
E-W
Gen.
16bitD/A
16bitD/A
42
36
43
44
45
47
*(H-phase, H-stop)
* (H-size, parabola, trapezium,
upper corner, lower corner)
* (V-size, V-position, linearity,
S-correction, service SW)
HD
out
VD
out
*(V-shift)
V Sync Sep.
V Count Down
VZ OUT
41
H-AFC2
H OUT pulse Gen.
8fsc out
(for OSD)
BGP
RGB
Processor
(Inc. MTX)
H.T.
in
OSD(RGB)
in
From MCU
F.B.
in
* (Half tone, Blue back, ABCL,
Contrast, Gamma, Blue stretch)
H-AFC
H VCO
H Count Down
* (AFC1 gain)
C-processing
* (Color, Tint, Killer off)
Y-processing
* (CVBS/YC/YUV SW)
1H DL
C or U-V
signal
CVBS
Y-signal
Vdd(Digital)
=3.3V
VssDigital)
TV1 IN
1.23Vp-p
Vdd(Input)
=3.3V
To MCU
for CCD
Y-SW out
(2Vp-p)
FBP IN (0-3.3V)
H correction (0-3.3V)
H OUT (0-3.3V)
Connection to MCU block inside
Pins connected to external
Vdd(Def)
=3.3V
Vss(Def)
V RAMP(-) OUT (0-2Vp-p)
V RAMP(+) OUT (0-2Vp-p)
E-W OUT (0-2Vp-p)
HVCO F/B
AFC1 Filter
B OUT (0-1Vp-p)
G OUT (0-1Vp-p)
R OUT (0-1Vp-p)
VM OUT (0-1Vp-p)
Vss(Output)
Vdd(Output)
=3.3V
M65582AMF-XXXFP
Block Diagram (ASIC)
TEST
APC FILTER
N.C.
XTAL
M65582AMF-XXXFP
Absolute maximum ratings
Parameter
Symbol
Ratings
Unit
Conditions
Supply voltage (MCU : 5V)
VDD (MCU)
−0.3 to 6.0
V
Supply voltage (ASIC : 3.3V)
VDD (ASIC)
−0.3 to 4.0
V
Input Voltage (MCU)
Output Voltage (MCU)
VI (MCU)
VO (MCU)
−0.3 to Vcc+0.3
−0.3 to Vcc+0.3
V
V
All voltage are based
on Vss.Output
transistors are cut off.
Circuit current (MCU)
Circuit current (P00-P07, P10,
P15, P16, P20-P27, P40-P45)
IOH (MCU)
IOL1 (MCU)
0 to 1 (See note 1)
0 to 2 (See note 2)
mA
mA
Circuit current (P11-P14)
Circuit current (P24-P27)
IOL2 (MCU)
IOL3 (MCU)
0 to 6 (See note 2)
10 (See note 3)
mA
mA
Digital input voltage
Analog output current
VID (ASIC)
IOUT (ASIC)
−0.3 to Vcc+0.3
−30
V
mA
Power dissipation
Thermal derating
Pd
Kt
2000
20.0
mW
mW/°C
Operating temperature
Storage temperature
Topr
Tstg
−20 to 70
−40 to 125
°C
°C
Recommended Conditions
(Ta=25 to 70°C, Unless otherwise noted)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply voltage (MCU) (See note 4)
Supply voltage (Digital)
VDD (MCU)
VDD (Digital)
4.75
3.13
5.0
3.3
5.25
3.47
V
V
Supply voltage (Input)
Supply voltage (Output)
VDD (Input)
VDD (Output)
3.13
3.13
3.3
3.3
3.47
3.47
V
V
Supply voltage (VCXO)
Supply voltage (DEF)
VDD (VCXO)
VDD (DEF)
3.13
3.13
3.3
3.3
3.47
3.47
V
V
Supply voltage (MCU)
High Iutput voltage P00-P07, P10-P16, P20P27,
P40-P45, RESET, X IN
VSS (MCU)
VIH1 (MCU)
0
0.8 VDD
0
0
VDD
V
V
High Iutput voltage SCL1, SCL2, SDA1, SDA2
(When using I2C -Bus)
High Iutput voltage FBP IN
VIH2 (MCU)
0.7 VDD
VDD
V
VIH3 (ASIC)
0.8 VDD
VDD
V
Low Iutput voltage P00-P07, P10-P16, P20-P27
P40-P45
Low Iutput voltage SCL1, SCL2, SDA1, SDA2
(When using I2C-Bus)
VIL1 (MCU)
0
0.4 VDD
V
VIL2 (MCU)
0
0.3 VDD
V
Low Iutput voltage (See note 6) RESETB, X IN,
TIM2, TIM3, INT1, INT2, INT3, S IN, S CLK
Low Iutput voltage FBP IN
VIL3 (MCU)
0
0.2 VDD
V
VIL4 (ASIC)
0
High average output current (See note 1)
P10-P16, P20-P27, P40-P45
Rev.1.0, Sep.19.2003, page 5 of 45
IOH (MCU)
0.2 VDD
V
1
mA
M65582AMF-XXXFP
Limits
Parameter
Symbol
Low average output current (See note 2)
P00-P07, P10, P15, P16, P20-P27, P40-P45
Max.
Unit
IOL1(MCU)
2
mA
Low average output current (See note 2)
P11-P14
Low average output current (See note 3)
P24-P27
IOL2(MCU)
6
mA
IOL3(MCU)
10
mA
Oscillation frequency (for CPU operation) X IN
(See note 5)
Oscillation frequency (for sub-clock operation)
X CIN
f(XIN) (MCU)
7.9
8.0
8.1
MHz
f(XCIN) (MCU)
29
32
35
kHz
Input frequency TIM2, TIM3, INT1, INT2, INT3
Input frequency S CLK
fhs1 (MCU)
fhs2 (MCU)
100
1
kHz
MHz
Input frequency SCL1, SCL2
Input amplitude video signal CV IN
fhs3 (MCU)
VI (MCU)
400
2.5
kHz
V
Note
Min.
1.5
Typ.
2.0
1: The total current that flows out the MCU must be 20mA or less.
2: The total input current to MCU (IOL1+IOL2) must be 30mA or less.
3: The total average input current for ports P24-P27 to MCU must be 20mA or less.
4: Connect 0.1µF or more capacitor externally between the power source pins VDD-VSS so as to reduce power
source noise.
5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillator circuit. When using the data
slicer, use 8MHz.
6: P06, P07, P23-P25 have the hysteresis when these pins are used as interrupt input pins or timer pins.
2
P11-P14 have the hysteresis when these pins are used as multi-master I C-Bus interface ports.
P20-P22 have the hysteresis when these pins are used as serial I/O pins.
7: Pin name in each parameter is described pin names.
(1) Dedicated pins: dedicated pin name.
(2) Double-/Triple-function ports.
When the same limits: I/O port name.
When the limits of function except ports are different from I/O port limits: function pin name.
Rev.1.0, Sep.19.2003, page 6 of 45
M65582AMF-XXXFP
Thermal derating
THERMAL DERATING (MAXIMUM RATING)
POWER DISSIPATION Pd (W)
2.0
1.5
1.1
1.0
0.5
0.0
0
50 1
25
7075
100
125
AMBIENT TEMPERATURE Ta (°C)
Rev.1.0, Sep.19.2003, page 7 of 45
50
M65582AMF-XXXFP
I2C bus
2
I C bus table
Slave Sub
D7
D6
D5
D4
D3
D2
D1
D0
address address
00h
BAh
V STOP
Power Down
H STOP
BAh
01h
Input Video SW
SAW Filter
Line-delay Number
BAh
02h Pedestal Clamp
VRT Voltage
BAh
Sharpness Noise Coring Level
Aperture Frequency
04h
BAh
Sharpness Max Gain
EHT
05h
BAh
Y Delay
YNR SW
YNR Coring Level
06h
BAh
Tint
08h
BAh
Color
09h
BAh
Contrast
0Ah
BAh
Half Tone
OSD Level (R)
0Bh
BAh
RGB MTX
OSD Level (G)
0Ch
BAh
OSD COMP
OSD Level (B)
0Dh
BAh
Brightness
0Eh
BAh
H AFC2 Phase
0Fh AFC Free Run H AFC Gain
BAh
Y 2D Fix
G OUT Mute B OUT Mute C BPF Fix
Y Mute
10h RGB P-ON Mute Y THR 2D R OUT Mute
BAh
MANEXP
ALFA
11h
BAh
RGB ON
FSC SEL
FSC ORG
Blue Stretch
Gamma
12h
BAh
H OUT Duty H Free Up
13h
BAh
V BLK Stop
V Size
14h
BAh
V Linearity
15h
BAh
Cuttoff (R) L
16h
BAh
Drive (R)
17h Cutoff (R) H
BAh
Cuttoff (G) L
18h
BAh
Drive (G)
19h Cutoff (G) H
BAh
Cuttoff (B) L
1Ah
BAh
Drive (B)
1Bh Cutoff (B) H
BAh
Analog Monitoring Point
1Ch
BAh
TEST I/O
Digital Monitoring Point
1Dh
BAh
14H CLK DLY
DS CLK DLY
A/D CLK DLY
INV DS CLK
30h INV 14H CLK
BAh
VJP Width
VJP SW
ABL SEL
UV LPF ON
32h
BAh
Black Stretch Time 1
Black Stretch Time 2
33h
BAh
DS D/A CLK CTL
ABL Speed
DS D/ADither
34h
BAh
ABL SPE
ABL ASPE
35h
BAh
ABL Time Constant
ABL Gain
36h
BAh
UV Dither Test Enable
UV Dither ON
ABL ASPE2
37h
BAh
AKB Mode
EHT Gain
AKB P
38h
BAh
YCS HBPF Back
YCS HBPF Front
39h
BAh
Sharpness Overshoot Gain
3Ah
BAh
3Bh
Sharpness Preshoot Gain
BAh
BS T2 IF ON
THR NZV 1
Black Stretch Depth
Black Stretch SW
3Dh
BAh
THR NZV 2
3Eh
BAh
THR NZH 1
3Fh
BAh
THR NZH 2
40h
BAh
41h
Killer Level
BAh
AMP CTL
RRAY
42h
BAh
AMP1 OFF L
43h
BAh
AMP1 ON
44h AMP1 OFF H
BAh
ACC SW
MV2 SW
MV1 SW
MV
45h
BAh
46h
BGP POS
4FSC SW
HD SW
Killer SW
BAh
OSD Limit
C Delay
AVE SEL
Force Killer Clamp BITSEL
47h
BAh
AMP3 ACC
V Mask Time
AMP TIM
B2 AVE SEL
48h
BAh
Free Run Offset
49h YUV MPX SEL YUV CXUV YUV UV Inv.
UV Gain
BAh
Killer Threshold
4Bh
BAh
BG Start
SWAP
Free Run
4Ch
BAh
BW DET
4Dh
BW SEL
BAh
4Eh
Skew Corrector
VCXO CTRL
Skew Co. Ini.
BAh
H Charge Pump
Ramp Slew Rate
Auto Slice Up
Auto Slice Down
4Fh
BAh
50h
Ref Charge Pump
AFC1 Pull-in
VCXO Free Run
Ref VCO
BAh
51h
H VCO Free Run
52h
BAh
AFC2 Gain
I/M Test
V Sag
LPF SYNC V Ramp Filter OFF Macro OFF
Sync Sep Mask
BAh
53h EWV V Reset
Sync Slice Level (V)
Sync Slice Level (H)
4FSC SEL 2 8FSC SEL
B PLL C.P.
BAh
BGP C
VD Delay
V Free
V CD Mode
54h V-Latch OFF H BLK Stop V CD Mode 2
Note: Sub address 03h, 07h, 1Eh-2Fh, 31h, 3Ch, 4Ah and 5Eh-64h are not operational.
Rev.1.0, Sep.19.2003, page 8 of 45
Standard
data
00h
08h
08h
10h
0Fh
6Fh
40h
40h
40h
20h
A0h
20h
80h
20h
02h
02h
80h
02h
20h
20h
00h
C0h
00h
C0h
00h
C0h
00h
00h
03h
04h
F4h
04h
92h
05h
02h
60h
03h
20h
20h
34h
FFh
FFh
FFh
01h
C0h
5Ah
04h
30h
68h
42h
00h
00h
01h
90h
01h
14h
78h
61h
00h
2Ch
67h
29h
M65582AMF-XXXFP
Slave Sub
D7
D6
D5
D4
D3
D2
D1
D0
address address
BAh
AMP2 ON
55h AMP CTRL EN
BAh
AMP3 ON
56h
BAh
AMP2 OFF L
57h
BAh
AMP2 OFF H
58h
AMP3 OFF L
BAh
59h
Weak Sig Det Vth
AMP3 OFF H
BAh
5Ah
Weak Sig Chroma ATT
Weak Sig Video ATT
Spot Killer
BAh
5Bh
TEST I/O Control
5Ch
BAh
MEM TEST
TEST SEL
BAh
5Dh XTEST RST LPF SYNC ON Sync Slice Level (V/W)
V Aperture Coring Level
65h
BAh
V Aperture Gain
V Aperture Max Gain
66h
BAh
VM POL
VM Width
VM Coring Level
67h
BAh
VM Max Gain
VM Gain
68h
BAh
69h
VM Delay
Black Stretch Start Point Y Clamp ON Y Clamp Fix
BAh
S Correction
6Ah
BAh
6Bh
H Size
BAh
Parabola
6Ch
BAh
Trapezium
6Dh
BAh
6Eh
Upper Corner
BAh
Lower Corner
6Fh
BAh
LIM
70h
BAh
V Position
71h
BAh
AFC Bow
72h
BAh
73h
AFC Angle
BAh
V Free 2
AFC2 SEL
Angle OFF
AFC2 Ramp Pos
74h
BAh
H BLK F Position
75h
Clock SEL
BAh
76h
H BLK R Position
BAh
V BLK Pos
AKB Ref PLS Pos V BLK Half Kill
77h
FBP BLK
BAh
78h
VREF SEL
A/D Read Page
V Sync LPF 2
V Sync LPF 1
BAh
79h
DCT Vth
BAh
DCT Gain
7Ah
BAh
7Bh
AKB LIM 1
BAh
7Ch
AKB LIM 2
BAh
7Dh
AKB LIM 3
BAh
7Eh
AKB ADD 1
BAh
7Fh
AKB ADD 2
BAh
80h
AKB COMP (R) L
BAh
81h
AKB COMP (G) L
BAh
AKB COMP (B) L
82h
BAh
83h
AKB COMP (R) H
V EN OFF AKB Enable
AKB COMP (B) H
AKB COMP (G) H
BAh
A/D D/A Test EN
84h
BAh
85h
AXIS HYS
BAh
86h
AVE SEL AV
ROM HYS
BAh
87h
B2 COMP
BAh
88h
V In Offset
U In Offset
BAh
89h
ACL Gain
ACL ON
AKB SEL
AKB Speed
CLK SEL SAR A/D
BAh
8Ah
VM Gain 2
DS CLK Latch Pol DS CLK Latch ON
V PLS Width
DS CLK DIV SEL
BAh
AKB SWERR
8Bh
BAh
AKB ERRC
8Ch
BAh
AKB SWPON
8Dh
BAh
AKB PWERRC
8Eh
BAh
BBh
BBh
BBh
BBh
BBh
BBh
BBh
BBh
BBh
BBh
BBh
BBh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
S Det
H COIN
B2 ROM <8> Killer Status
AKB END
V COIN
AKB A/D (R) <9:8>
AKB New (R)
AKB A/D (G) <9:8>
AKB New (G)
AKB A/D (B) <9:8>
AKB New (B)
AKB NG
Still Det
B/W Out
B2 ROM <7:0>
AKB A/D (R) <7:0>
C Gain
AKB A/D (G) <7:0>
AKB A/D (B) <7:0>
Y A/D <7:0>
C A/D <7:0>
0
0
Rev.1.0, Sep.19.2003, page 9 of 45
1
0
DETNZ
MV 180
K MONI
Standard
data
84h
04h
40h
00h
40h
00h
00h
00h
80h
00h
0Fh
00h
8Fh
E6h
00h
20h
20h
20h
20h
20h
0Fh
20h
20h
20h
08h
81h
80h
02h
04h
1Eh
00h
04h
0Ch
15h
02h
06h
00h
00h
00h
2Ah
00h
1Eh
CAh
00h
88h
00h
40h
7Ch
14h
1Eh
02h
M65582AMF-XXXFP
2
I C bus function
Sub
address
00h
01h
02h
04h
05h
06h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
30h
Data Bit
D0
D1-D2
D3
D0
D2
D3-D7
D3-D4
D7
D0-D3
D4-D5
D0-D3
D4-D7
D0-D3
D4
D5-D6
D0-D6
D0-D6
D0-D6
D0-D5
D6-D7
D0-D5
D6-D7
D0-D5
D6-D7
D0-D7
D0-D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0-D1
D2-D3
D0-D1
D2-D3
D4-D5
D6
D7
D0
D1
D0-D5
D7
D0-D5
D0-D7
D7
D0-D6
D0-D7
D7
D0-D6
D0-D7
D7
D0-D6
D0-D3
D0-D4
D5
D0-D1
D2-D3
D4
Function
Description
Note
1
2
1
1
1
5
2
1
4
2
4
4
4
1
2
7
7
7
6
2
6
2
6
2
8
6
1
1
1
1
1
1
1
1
1
1
2
1
2
2
2
1
1
1
1
6
1
6
9
H STOP
Power Down
V STOP
Line-delay Number
SAW Filter
Input Video SW
VRT Voltage
Pedestal Clamp
Sharpness Noise coring level
Aperture Frequency
Sharpness Max Gain
EHT
YNR Coring Level
YNR SW
Y Delay
Tint
Color
Contrast
OSD Level (R)
Half Tone
OSD Level (G)
RGB MTX
OSD Level (B)
OSD COMP
Brightness
H AFC2 Phase
H AFC Gain
AFC Free Run
Y Mute
C BPF Fix
B OUT Mute
G OUT Mute
Y 2D Fix
R OUT Mute
Y THR 2D
RGB P-ON Mute
ALFA
MANEXP
Gamma
Blue Stretch
FSC ORG
FSC SEL
RGB ON
H Free Up
H OUT Duty
V Size
V BLK Stop
V Linearity
Cutoff (R)
H pulse stop
Power Down control (0: normal, 1: PD0, 2: PD1, 3: PD2)
V output stop
Y/C separation mode (0: 3-line mode, 1: 2-line mode)
Chroma BPF to high
Input video SW (01: TV1 IN, 02: TV2 IN, 04: TV3 IN, 08: Y/C IN, 10: YUV IN)
A/D Reference (0: 1.1V, 1: 1.2V, 2: 1.3V, 3: 1.4V)
Input clamp select (0: pedestal clamp, 1: sync-tip clamp)
Sharpness coring level (0: minimum –— F: maximum)
Sharpness f0 (0: 2-clk <—> 3: 5-clk)
Sharpness limiter level (0: minimum –— F: maximum)
EHT gain control (0: minimum –— F: maximum)
YNR limiter level (0: minimum –— F: maximum)
YNR enable
Y delay time (0: 0nsec–— 3: 210nsec)
Tint level control (00: -45˚ –— 7F: +45˚)
Color level control (00: 0% –— 7F: 200%)
Contrast control (00: 0% –— 7F: 200%)
R OSD level (00: 0% –— 7F: maximum)
Half tone level control (Picture/OSD ratio 0: 50%/50% –— 3: 12.5%/87.5%)
G OSD level (00: 0% –— 7F: maximum)
RGB matrix ratio (0: 12/8, 1: 13/8, 2: 14/8, 3: 14/8)
B OSD level (00: 0% –— 7F: maximum)
Contrast clip level for OSD (0: low –— 3: high)
Brightness control (00: -50% –— 7F: +50%)
H position (00: +2.6µsec –— 7F: -2.6µsec)
AFC1 Gain (0: low, 1: high)
AFC1 Force free-run
Y output mute
Chroma signal generate from H/V BPF only
B output mute
G output mute
Y signal generate from 2DYCS
R output mute
Y signal through 2D YCS
RGB output mute
Adaptive detection sensitivity (0: minimum –— 3: maximum)
Y/C separation force select (0: adaptive, 2: V, 3: H/V)
Gamma control (0: none –— 3: deep)
Blue stretch control (0: none –— 3: deep)
Chroma decoder phase select
Chroma decoder clock select
RGB output (0: RGB mute except OSD, 1: RGB output)
AFC1 Free-run frequency up (about 700Hz)
H pulse width (0: 25µsec, 1: 19µsec)
V ramp amplitude (00: -20% –— 3F: +20%)
V blanking off
V linearity (00: -3% –— 3F: +3%)
R cutoff control (000: dark –— 1FF: light)
7
9
Drive (R)
Cutoff (G)
R drive control (00: -2.5dB –— 7F: +3.5dB)
G cutoff control (000: dark –— 1FF: light)
V Latch
V Latch
7
9
Drive (G)
Cutoff (B)
G drive control (00: -2.5dB –— 7F: +3.5dB)
B cutoff control (000: dark –— 1FF: light)
V Latch
V Latch
7
4
5
1
2
2
1
Drive (B)
Analog Monitoring Point
Digital Monitoring Point
TEST I/O
A/D CLK DLY
DS CLK DLY
INV DS CLK
B drive control (00: -2.5dB –— 7F: +3.5dB)
Intelligent monitoring output select (Analog)
Intelligent monitoring output select (Digital)
Intelligent monitoring output enable (Digital)
A/D clock delay adjust (0: none –— 3: delay)
∆Σ D/A (for V-ramp and E-W) clock delay adjust (0: none –— 3: delay)
∆Σ D/A (for V-ramp and E-W) clock polarity (0: none –— 1: invert)
V Latch
Rev.1.0, Sep.19.2003, page 10 of 45
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
M65582AMF-XXXFP
Sub
address Data
30h D5-D6
D7
D1
32h
D2
D6
D7
33h D0-D3
D4-D7
34h D2-D3
D4
D5-D6
35h D0-D3
D4-D7
36h D0-D3
D4-D6
37h D0-D1
D2
D3-D5
38h D0-D5
D6
D7
39h
D0
D1-D2
3Ah D0-D5
3Bh D0-D5
3Dh
D0
D1-D3
D6
D4-D5
3Eh D0-D7
3Fh D0-D7
40h D0-D7
41h D0-D6
42h D0-D5
D6-D7
43h D0-D7
44h
D7
D0-D6
45h D0-D3
D4
D5
D6
46h D0-D4
D5
D6
D7
47h D0-D1
D2-D3
D4
D6
D7
48h D0-D1
D2-D3
D4-D6
D7
49h D0-D3
D4
D5
D6
D7
4Bh D0-D1
4Ch D0-D5
D6
D7
4Dh D0-D1
Bit
Function
2
1
1
1
1
1
4
4
2
1
2
4
4
4
3
2
1
3
6
1
1
1
2
6
6
1
3
1
10
14H CLK DLY
INV 14H CLK
UV LPF ON
ABL SEL
VJP SW
VJP Width
Black Stretch Time 2
Black Stretch Time 1
ABL Speed
DS D/A Dither
DS D/A CLK CTL
ABL ASPE
ABL SPE
ABL Gain
ABL Time Constant
ABL ASPE 2
UV Dither ON
UV Dither Test Enable
AKB P
EHT Gain
AKB Mode
YCS HBPF Front
YCS HBPF Back
Sharpness Overshoot Gain
Sharpness Preshoot Gain
Black Stretch SW
Black Stretch Depth
BS T2 IF ON
THR NZV
4fsc clock delay adjust (0: none –— 3: delay)
4fsc clock polarity (0: none, 1: invert)
UV LPF (digital) enable
ABL function (0: enable, 1: disenable)
Jump SW enable
Jump pulse width (0: normal, 1: wide +2-line)
Black stretch recover time (0: slow –— F: fast)
Black stretch attack time (0: slow –— F fast)
ABL processing speed (0: X1, 1: X2, 2: X4, 3: X8)
∆Σ D/A (for V-Ramp and E-W) dither enable
∆Σ D/A (for V-Ramp and E-W) clock select (0: 28M, 1: 24M, 2: 14M, 3: 16M)
ABL attack speed (0: slow –— 7: fast)
ABL recover speed (0: slow –— 7: fast)
ABL gain control (0: minimum –— 7: maximum)
ABL time constant (0: slow –— 7: fast)
ABL attack speed 2 (0: slow –— 7: fast)
UV dither enable
UV dither test select
AKB reference pulse height (00: minimum –— 3F: maximum)
EHT gain up (0: normal, 1: high)
AKB mode select (0: differential mode, 1: absolute mode)
Y/C separation front BPF band width (0: wide, 1: narrow)
Y/C separation rear BPF band width (0: none, 1: wide –— 2 and 3: narrow)
Sharpness overshoot gain (00: soft –— 3F: sharp)
Sharpness preshoot gain (00: soft –— 3F: sharp)
Black stretch SW (0: disenable, 1: enable)
Black stretch depth (0: shallow –— 7: deep)
Black stretch recover time constant (0: slow, 1: fast)
Noise detection threshold level in field (000: minimum –— 3FF: maximum)
16
THR NZH
Noise detection threshold level in line (0000: minimum –— FFFF: maximum)
7
6
2
9
Killer Level
RRAY
AMP CTL
AMP1 OFF
Color Killer threshold level (00: deep –— 7F: shallow)
R-Y phase offset (00: 0˚ –— 3F: 90˚)
Analog ACC amp maximum gain (0: 0dB –— 3: +30dB)
Analog ACC amp #1 on –>off level (000: minimum –— 1FF: maximum)
7
4
1
1
1
5
1
1
1
2
2
1
1
1
2
2
3
1
4
1
1
1
1
2
6
1
1
2
AMP1 ON
MV
MV1 SW
MV2 SW
ACC SW
BGP POS
Killer SW
HD SW
4FSC SW
AVE SEL
C Delay
OSD Limit
Clamp BITSEL
Force Killer
B2 AVE SEL
AMP TIM
V Mask Time
AMP3 ACC
Free Run Offset
UV Gain
YUV UV Inv.
YUV CXUV
YUV MPX SEL
Killer Threshold
BG Start
Free Run
SWAP
BW DET
Analog ACC amp #1 off –>on level (00: minimum –— 7F: maximum)
Macro vision (burst) detect level
Macro vision (burst) detect enable
Macro vision (burst) detect position
ACC enable
BGP (for chroma decoder) position
Killer detector mode select (0: synchronous detect, 1: amplitude detect)
HD out (for OSD) select (0: FBP, 1: AFC1 pulse)
A/D-LOGIC clock swap
Chroma decoder time constant (0: 32H, 1: 16H, 2: 8H, 3: 1H)
Chroma delay time (0: none –— 3: delay)
OSD limit select
Y digital clamp time constant (0: fast, 1: slow)
Forced killer
Accumulation time control of demodulation
Analog ACC hysteresis select
V masking time for demodulation
ACC maximum gain
VCXO free-run frequency adjust
U/V gain up
U/V invert
YC/YUV select
U/V multiplex select (0: 2fsc, 1: fsc)
PLL stop burst level
BGP (for PLL) timing control
VCXO force free-run
Burst PLL polarity (0: reverse, 1: normal)
PLL Killer threshold level
Rev.1.0, Sep.19.2003, page 11 of 45
Description
Note
V Latch
V Latch
M65582AMF-XXXFP
Sub
address
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
Data Bit
D2
D0
D1-D4
D5-D7
D0-D1
D2
D3-D4
D5-D7
D0
D1-D2
D4
D5-D7
D0-D7
D0
D1
D2-D3
D4
D5
D6
D7
D0
D1
D2
D3-D4
D5-D6
D7
D0-D1
D2
D3
D4
D5
D6
D7
D0-D6
D7
D0-D6
D0-D7
D0
D0-D7
D0
D1-D3
D0
D1-D3
D4-D6
D0-D7
D0-D2
D3
D4-D5
D6
D7
D0-D3
D0-D3
D4-D7
D0-D3
D4-D5
D6
D0-D3
D4-D7
D0-D3
D4
D5
D6-D7
D0-D5
D0-D5
D0-D5
Function
Description
1
1
4
3
2
1
2
3
1
2
1
3
8
1
1
2
1
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
7
1
7
9
BW SEL
Skew Co Ini.
VCXO CTRL
Skew Corrector
Auto Slice Down
Auto Slice Up
Ramp Slew Rate
H Charge Pump
Ref VCO
VCXO Free Run
AFC1 Pull-in
Ref Charge Pump
H VCO Free Run
Sync Sep Mask
V Sag
AFC2 Gain
Macro OFF
V Ramp Filter OFF
LPF SYNC
I/M Test
B PLL C.P.
8FSC SEL
4FSC SEL 2
Sync Slice Level (H)
Sync Slice Level (V)
EWV V Reset
V CD Mode
V Free
VD Delay
BGP C
V CD Mode 2
H BLK Stop
V-Latch OFF
AMP2 ON
AMP CTRL EN
AMP3 ON
AMP2 OFF
∆Σ D/A clock invert
Skew corrector reference phase
VCXO phase adjust
Skew corrector phase control
Auto slicer level down (0: up –— 3: down)
Auto slicer level up
AFC2 Ramp slew rate
AFC1 charge pump current (4: minimum – 5 – 6 – 7 – 0 – 1 – 2 – 3: maximum)
Ref PLL loop gain up
VCXO f0 adjust
AFC1 pull-in range wide
Ref PLL charge pump current (4: minimum – 5 – 6 – 7 – 0 – 1 – 2 – 3: maximum)
H VCO f0 adjust (In case of data is XYh, X decrease the f0, and Y increase the f0)
Sync separator masking control
V sag prevent on
AFC2 gain control (0: fast –— 3: slow)
Top vend (when macrovision) prevent off
V Ramp and E-W output filter off
Pre sync separation LPF f0 becomes low
Intelligent monitoring signal (Digital) enable to output to pin 51
Chroma APC charge pump current up (0: normal, 1: X5)
H rate clock select (0: 12MHz, 1: 4fsc skew clock)
4fsc skew force off (0: H rate clock, 1: Burst rate clock)
Sync slice level (H sync separation)
Sync slice level (V sync separation)
∆Σ D/A V reset on
V detect window switch timing (0: 5H, 1: 3H, 2: 1H, 3: force 1 window)
Force V free-run
VD pulse delay
BGP (for deflection block) width (0: normal, 1: Don't use. Useful only test mode)
V sub-counter enable
H blanking off
IIC V latch off (for test)
Analog ACC amp #2 off –>on level (00: minimum –— 7F: maximum)
Analog ACC amp #1, #2 and #3 enable
Analog ACC amp #3 off –>on level (00: minimum –— 7F: maximum)
Analog ACC amp #2 on –>off level (000: minimum –— 1FF: maximum)
9
AMP3 OFF
Analog ACC amp #3 on –>off level (000: minimum –— 1FF: maximum)
3
1
3
3
8
3
1
2
1
1
4
4
4
4
2
1
4
4
4
1
1
2
6
6
6
Weak Sig Det Vth
Spot Killer
Weak Sig Video ATT
Weak Sig Chroma ATT
TEST I/O Control
TEST SEL
MEM TEST
Sync Slice Level (V/W)
LPF SYNC ON
XTEST RST
V Aperture Coring Level
V Aperture Max Gain
V Aperture Gain
VM Coring Level
VM Width
VM POL
VM Max Gain
VM Gain
VM Delay
Y Clamp Fix
Y Clamp ON
Black Stretch Start Point
S Correction
H Size
Parabola
Noise detect level of RF weak signal (0: minimum –— 7: maximum)
Force spot Killer
Video attenuation control of RF weak signal (0: no attenuation –— 7: maximum)
Chroma attenuation control of RF weak signal (0: no attenuation –— 7: maximum)
Test mode I/O control (only factory use)
Test mode select (only factory use)
Memory test mode (only factory use)
Sync slice level (V sync separation within narrow window)
Pre sync separation LPF enable
Test mode select (only factory use)
V aperture coring level (0: minimum –— F: maximum)
V aperture limit level (0: minimum –— F: maximum)
V aperture gain (0: minimum –— F: maximum)
VM coring level (0: minimum –— F: maximum)
VM width (0: minimum –— 3: maximum)
VM polarity
VM limit level (0: minimum –— F: maximum)
VM gain (0: minimum –— F: maximum)
VM output delay (0: forward –— F: delay)
Y digital clamp control 1 (0: Y digital clamp enable, 1: Y digital clamp disenable)
Y digital clamp control 2 (0: clamp level is held, 1: clamp level is refleshed at all time)
Black stretch start point (0: 25%, 1: 31%, 2: 38%, 3: 44%)
V Ramp S correction (00: 0% –— 3F: +3%)
E-W output DC level (00: +250mV –— 3F: -250mV)
E-W output amplitude (00: 0.1Vp-p –— 3F: 0.7Vp-p)
Rev.1.0, Sep.19.2003, page 12 of 45
Note
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
V Latch
M65582AMF-XXXFP
Sub
address
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
Data Bit
D0-D5
D0-D5
D0-D5
D0-D3
D0-D5
D0-D5
D0-D5
D0-D3
D4
D6
D7
D0
D2-D7
D2-D7
D1
D2
D3-D4
D5
D0-D1
D2-D3
D4-D5
D6-D7
D0-D6
D0-D4
D0-D7
D0-D7
D0-D7
D0-D7
D0-D7
D0-D7
D0-D7
D0-D7
D0-D1
D2-D3
D4-D5
D6
D7
D0-D5
D0-D5
D0-D5
D6-D7
D0-D6
D0-D3
D4-D7
D0
D1
D2-D3
D4-D5
D6-D7
D0-D1
D2
D3
D4-D5
D6
D0-D7
D0-D7
D0-D7
D0-D7
6
6
6
4
6
6
6
4
1
1
1
1
6
6
1
1
2
1
2
2
2
2
7
5
8
8
8
8
8
8
8
8
2
2
2
1
1
6
6
6
2
7
4
4
1
1
2
2
2
2
1
1
2
1
8
8
8
8
Function
Trapezium
Upper Corner
Lower Corner
LIM
V Position
AFC Bow
AFC Angle
AFC2 Ramp Pos
Angle OFF
AFC2 SEL
V Free 2
Clock SEL
H BLK F Position
H BLK R Position
V BLK Half Kill
AKB Ref PLS Pos
V BLK Pos
FBP BLK
A/D Read Page
V Sync LPF 1
V Sync LPF 2
VREF SEL
DCT Vth
DCT Gain
AKB LIM 1
AKB LIM 2
AKB LIM 3
AKB ADD 1
AKB ADD 2
AKB COMP (R) L
AKB COMP (G) L
AKB COMP (B) L
AKB COMP (R) H
AKB COMP (G) H
AKB COMP (B) H
AKB Enable
V EN OFF
A/D D/A Test EN
AXIS HYS
ROM HYS
AVE SEL AV
B2 COMP
U In Offset
V In Offset
ACL ON
ACL Gain
CLK SEL SAR A/D
AKB Speed
AKB SEL
DS CLK DIV SEL
DS CLK Latch ON
DS CLK Latch Pol
VM Gain 2
V PLS Width
AKB SWERR
AKB ERRC
AKB SWPON
AKB PWERRC
Rev.1.0, Sep.19.2003, page 13 of 45
Description
Note
E-W trapezium (00: -50% –— 3F: +50%)
E-W upper corner (00: -200% –— 3F: +200%)
E-W lower corner (00: -200% –— 3F: +200%)
Chroma detect level for 2D YCS (0: minimum –— F: no limit)
V Ramp output DC level (00: -10% –— 3F: +10%)
AFC Bow (00: +1.5µsec –— 3F: -1.5µsec)
AFC Angle (00: +/-1.5µsec –— 3F: -/+1.5µsec)
AFC2 Ramp position (0: -5.2µsec –— F: +5.2µsec)
AFC Angle/Bow disenable
AFC Angle/Bow and H correction disenable
Adaptive vertical free-run mode (by H coincidence)
∆Σ D/A clock select (0: enable to select "DS D/A CLK CTL, 1: same clock as A/D)
H bllanking (right side) timing (00: +2.6µsec –— 3F: -2.6µsec)
H bllanking (left side) timing (00: +2.6µsec –— 3F: -2.6µsec)
V blanking half H killer enable
AKB reference pulse position (0: normal, 1: 3H delay)
V blanking width (0: normal –— 3: 3H wider, avairable only when AKB Ref PLS Pos="H")
H BLK mode select (0: adjustable by H BLK F/R Position, 1: FBP)
A/D read page select
V sync separation pre-LPF (rise edge) control (0: no filter –— 3: 2µsec)
V sync separation pre-LPF (fall edge) control (0: no filter –— 3: 2µsec)
A/D reference voltage source select (use Vz)
DC Transfer threshold level (0: low –— 7F: high)
DC Transfer ratio control (0: 100% –— 1F: 80%)
AKB LIM 1
AKB LIM 2
AKB LIM 3
AKB ADD1
AKB ADD 2
AKB COMP (R) LSB
AKB COMP (G) LSB
AKB COMP (B) LSB
AKB COMP (R) MSB
AKB COMP (G) MSB
AKB COMP (B) MSB
AKB enable (0: AKB level is held, 1: AKB level is refleshed at all time)
Disenable to reflesh ACC by vertinal rate
Test mode select for A/D and D/A (only factory use)
AXIS hys
Rom hys
Ave sel av
B2 comp
U input DC offset level (0: –10mV –— F: +10mV)
V input DC offset level (0: –10mV –— F: +10mV)
ACL enable
ACL gain up
SAR A/D clock select (0: 2fsc, 1: 4fsc, 2: 12MHz, 3: 6MHz)
AKB speed
AKB control (0: AKB disenable and available cutoff data, 1: AKB enable, 2: test mode)
∆Σ D/A clock divider select (0: 1/4, 1: 1/2, 2: 1/1, 3: clock off)
∆Σ D/A clock latched by 4fsc clock enable
∆Σ D/A clock latched by 4fsc clock polarity
VM gain2
V pulse width (0: standard, 1: wide)
AKB error detect threshold
AKB error detect time
AKB power on threshold
AKB power on time
V Latch
V Latch
V Latch
V Latch
M65582AMF-XXXFP
Sub
address
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
Data Bit
D2
D4
D5
D6
D7
D0
D2
D3
D4
D5
D6
D7
D0-D7
D0-D7
D6-D7
D3-D4
D5
D0-D7
D6-D7
D5
D0-D7
D6-D7
D5
D0-D7
D0-D7
D6-D7
Function
Description
Note
1
1
1
1
1
1
1
1
1
1
1
9
DETNZ
AKB NG
AKB END
S Det
H COIN
K MONI
MV 180
Still Det
B/W Out
V COIN
Killer Status
B2 ROM
Noise detector output
AKB NG output
AKB end output
S (Y/C) input detector output
Horizontal coincidence output
C-pro Killer detector output
Macrovision detector output
VCR still detector outut
Burst PLL Killer detector output
Vertical coincidence output
Color / Killer status output
B2 ROM data output
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
10
AKB A/D (R)
AKB A/D (R) output
Read
2
1
10
C Gain
AKB New (R)
AKB A/D (G)
Analog ACC amp status
AKB New (R) output
AKB A/D (G) output
Read
Read
Read
1
10
AKB New (G)
AKB A/D (B)
AKB New (G) output
AKB A/D (B) output
Read
Read
1
8
8
4
AKB New (B)
Y A/D
C A/D
0001
AKB New (B) output
Y A/D output monitoring
C A/D output monitoring
Product identification
Read
Read
Read
Read
Rev.1.0, Sep.19.2003, page 14 of 45
M65582AMF-XXXFP
Electrical characteristics (ASIC part)
P80
P79
P78
P77
P76
P75
P74
P73
P72
P71
P70
P69
P68
P67
P66
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
X1: Murata CSA8.00MTZ (8.00MHz)
X2: SIWARD 1-781-377-21 (14.31818MHz)
10K
VDD(5V)
VDD(3.3V)
1. Test circuit
P65
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
15p
P64
10K
2
63
P63
3
62
P62
P4
4
61
5
60
P60
6
59
P59
15p
47µ
64
P3
X1
A
10K
1
0.01µ
+
47µ
10K
100
Fast BLK
100
OSD(R)
100
7
58
P58
8
57
P57
OSD(G)
100
OSD(B)
100
9
56
P56
10
55
P55
SCL
10K
47µ
+
0.01µ
100
11
54
P54
12
53
P53
M65582AMF-XXXFP
52
P52
P14
14
51
P51
P15
15
50
P50
P16
16
49
P49
17
48
P48
13
SDA
10K
0.01µ
47µ
1µ
50
TV1 IN
+
0.01µ
0.1µ
Y(Y/C) IN
0.01µ
47µ
50
50
P18
18
47
P19
19
46
P46
20
45
P45
21
44
P44
22
43
P43
P47
0.1µ
+
C(Y/C) IN
0.01µ
0.01µ
50
2K
10µ
0.1µ
P22
TV3 IN
+
TV2 IN
0.1µ
P23
23
42
P24
24
41
0.01µ
0.1µ
+
50
0.1µ
0.1µ
47µ
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P35
P37
3.3K
+
220K
1K
+
0.22µ
22
22p
0.01µ
47µ
+
47µ
0.01µ
+
47µ
0.033µ
1µ
50
X2
2.2K
P41
P40
0.01µ
P33
6.8K
P31
0.01µ
P29
0.1µ
P28
0.1µ
0.1µ
P27
47µ
50
50
Y(YUV) IN
0.1µ
P26
U(YUV) IN V(YUV) IN
P25
47µ
8
7
6
5
4
3
2
1
15
16
9
10
11
12
13
14
4700p
Rev.1.0, Sep.19.2003, page 15 of 45
VR 20K
3K
M74LS221P
5.1K
3K
2200p
620
VR 20K
0.01µ
+
47µ
47µ
M65582AMF-XXXFP
2. Input Signal
SG No.
SG.A
Input signal (value at pin terminal is 50 )
NTSC system standard video signal.
APL can be varied. Vy=0.714V (APL
100%), unless otherwise noted.
The vertical signal should be interlaced
at 60Hz.
4.7µs
Vy
0.286V
0.286V
4.5µs
SG.B
The amplitude and frequency of Luminance signal can be varied by signal
SG.A. The typical amplitude is 0.714Vp-p.
The frequency of Luminance, (f) as
stated in test.
8.8µs
4.7µs
0.714V
0.286V
0.286V
f
4.5µs
SG.C
NTSC system mono-chroma video signal.
The amplitude and frequency of burst part
and chroma part can be varied.
The vertical signal should be interlaced
at 60Hz.
4.7µs
Veb
feb
4.5µs
fec
8.8µs
0°
NTSC system 2-phase chroma video
signal.
The vertical signal should be interlaced
at 60Hz.
90°
4.7µs
0.572V
0.286V
Standard condition:
Vy=0.286V
Veb=0.286V, Vec=0.572V
Peb=-180°, Pec1=0û, Pec2=90°
-180°
4.5µs
SG.E
Vec
0.286V
Standard condition:
Vy=0.286V
Veb=0.286V, Vec=0.572V
feb=fec=3.576545MHz
SG.D
8.8µs
0.286V
8.8µs 23.0µs
22.5µs
NTSC system rainbow color bar video signal.
The vertical signal should be interlaced at 60Hz.
External RGB (OSD) signals and
falt blanking signal should be synchronized with input video signal.
Vy=0.714V (APL100%), unless
otherwise noted.
4.7µs
Video
input
(pin16)
Vy
0.286V
SG.F
0.286V
4.5µs
Fast BLK (pin60)
Half Tone (pin61)
External R (pin59)
External G (pin58)
External B (pin57)
Rev.1.0, Sep.19.2003, page 16 of 45
8.8µs
3.3V
0V
20µs
24µs
M65582AMF-XXXFP
SG No.
Input signal (value at pin terminal is 50Ω)
Duty cycle 90%, frequency can be varied, amplitude can be varied (typ. 0.286Vp-p)
SG.G
0.286V
Duty cycle can be varied (typ. 95%), frequency can be varied (typ. 0.286Vp-p).
SG.H
0.286V
3. Setup instruction for evaluation PCB
3.1 Horizontal blanking pulse adjustment
The timing and pulse width of the horizontal blanking pulse should be as shown in the following figure by adjusting the
variable resistor of the single shot multi vibrator.
pin50 (H OUT)
8µs
FBP
12µs
The variable resistor at pin15 of TTL IC 'M74LS221P' is used to fix the timing at 8s and that at pin7 is used to fix the
pulse width at 12µs.
3.2. H VCO adjustment
Before measurement of M65582MF, HVCO must be adjusted by the following procedure.
Set the frequency at pin50 (H OUT) to about 15.734kHz by adjusting I2C-Bus data of H VCO control (51H D0-D7).
Rev.1.0, Sep.19.2003, page 17 of 45
M65582AMF-XXXFP
4. Electric characteristics
(Ta=25°C, Vdd=5.0, 3.3V)
Parameter
Symbol
Pins
Input signal
SG
Test
points
Max.
Typ.
Min.
Unit
Remarks
Standard conditions
3.3V supply current
DC
ICC33


A
140
180
220
mA
pin48 = 1.65V
Supply of ASIC
A/D reference voltage
(Top)
A/D reference voltage
(Bottom)
VRT


22
1.6
1.7
1.8
V
VRB


24
0.4
0.5
0.6
V
Parameter
Symbol
Test
points
Max.
Typ.
Min.
Unit
Standard conditions of
video parameter
Y
CVBS OUT output level
2AG
Luminance standard
output level
YOUT
Video frequency
characteristics
Input signal
Pins
SG
Limits
Limits
Remarks
pin48 = 1.65V
16,21,
23
16,21,
23
SG.A
15
1.8
2.0
2.2
Vpp
SG.A
31,33,
35
560
700
840
mVpp
FY
16,21,
23
SG.B
31,33,
35
−5
−2
1
dB
f=5MHz
VM output level
VM
16
SG.B
24
520
650
780
mVpp
f=3.58MHz
Parameter
Symbol
Test
points
Max.
Typ.
Min.
Unit
Standard conditions of
chroma parameter
C
ACC characteristic 1
ACC1
16
SG.C
31
−3
0
3
dB
Veb, Vec : +6dB of
typical input level
ACC characteristic 2
ACC2
16
SG.C
31
−3
0
3
dB
APC pull-in range
(upper)
APCU
16
SG.C
31
−300


Hz
Veb, Vec : -20dB of
typical input level
feb=fec : variable
APC pull-in range
(lower)
Demodulation phase
angle
APCL
16
SG.C
31


300
Hz
feb=fec : variable
DEMP
16
SG.D
31,35
85
90
95
deg
Input signal
Rev.1.0, Sep.19.2003, page 18 of 45
Pins
SG
Limits
Remarks
pin48 = 1.65V
M65582AMF-XXXFP
Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 04H 05H 06H 08H 09H 0AH 0BH 0CH 0DH 0EH 10H 12H 16H 17H 18H 19H 1AH 1BH 32H 3AH 3BH 51H 65H 66H 67H 68H 69H 79H 7AH 83H 89H
DC
00 08 6E 10 0F 6F 40 40 40 20 A0 20 80 02 80 00 C0 00 C0 00 C0 05 20 20 adj 00 83 00 8F 06 05 00 2A 00
ICC33
VRT
VRB
Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 04H 05H 06H 08H 09H 0AH 0BH 0CH 0DH 0EH 10H 12H 16H 17H 18H 19H 1AH 1BH 32H 3AH 3BH 51H 65H 66H 67H 68H 69H 79H 7AH 83H 89H
Y
00 08 6E 10 0F 6F 40 40 40 20 A0 20 80 02 80 00 C0 00 C0 00 C0 05 20 20 adj 00 83 00 8F 06 05 00 2A 00
2AG
00
YOUT
00
FY
00
VM
00
FF
Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 03H 08H 09H 0AH 0BH 0CH 0DH 0EH 10H 16H 17H 18H 19H 1AH 1BH 32H 41H 42H 45H 46H 47H 48H 49H 4CH 4DH 4EH 50H 51H 5DH 83H 89H
C
00 08 6E 08 40 40 40 20 A0 20 80 02 00 C0 00 C0 00 C0 05 01 C0 30 08 4B 00 00 91 04 14 71 adj 80 2A 00
ACC1
83
ACC2
83
APCU
83
APCL
83
DEMP
Rev.1.0, Sep.19.2003, page 19 of 45
M65582AMF-XXXFP
Input signal
Parameter
Symbol
Pins
SG
Standard conditions of
RGB parameter
RGB
Ouput Pedestal voltage
VPED
16
SG.A
Output Blanking voltage
VBLK
16
SG.A
Matrix ratio R/B
Matrix ratio G/B
MTXR
MTXB
16
16
AKB reference pulse
output level
OSD output level
AKBP
Test
points
Limits
Max.
Typ.
Min.
Unit
Remarks
pin48 = 1.65V
31,33,
35
31,33,
35
2.7
3.0
3.3
V
Vy = 0.0V
3.1

3.3
V
Vy = 0.0V
SG.E
SG.E
31,35
31,35
0.8
0.2
1.0
0.3
1.2
0.4


16
SG.A
200
300
400
mV
OSD
16,57,
58,59
SG.F
31,33,
35
31,33,
35
480
600
720
mVpp
Parameter
Symbol
Pins
Typ.
Min.
Standard conditions of
deflection parameter
DEF
Horizontal free-running
frequency
Horizontal pull-in range
(upper)
FH


50
15.48
15.73
15.98
kHz
FPHU
16
SG.G
50
600


Hz
Vary frequency of
input signal
Horizontal pull-in range
(lower)
Horizontal pulse
amplitude
FPHL
16
SG.G
50


−600
Hz
Vary frequency of
input signal
HOUT
16
SG.A
50
2.7
3.0
3.3
V
Horizontal pulse width
Vertical free-running
frequency
HPTW
FV
16

SG.A

50
50
17
57
19
60
22
63
µsec
Hz
Vertical pull-in range
(upper)
Vertical pull-in range
(lower)
FPVU
16
SG.H
44,45


64
Hz
FPVL
51
SG.H
44,45
56


Hz
Vertical output level
Vertical ramp output DC
voltage
VOUT
VDC
16
16
SG.A
SG.A
44,45
44,45
1.0
1.5
1.2
1.7
1.4
1.9
Vpp
V
E-W output level
E-W output DC voltage
EWOUT
EWDC
16
16
SG.A
SG.A
47
47
0.3
0.95
0.4
1.15
0.5
1.35
Vpp
V
Input signal
Rev.1.0, Sep.19.2003, page 20 of 45
SG
Test
points
Vy = 0.0V
Limits
Max.
Unit
Remarks
pin48 = 1.65V
Vary frequency of
input signal
Vary frequency of
input signal
M65582AMF-XXXFP
Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 04H 05H 08H 09H 0AH 0BH 0CH 0DH 0EH 10H 12H 16H 17H 18H 19H 1AH 1BH 32H 38H 3AH 3BH 51H 65H 66H 67H 68H 69H 79H 7AH 83H 89H
RGB
00 08 6E 10 0F 40 40 40 20 A0 20 80 02 80 00 C0 00 C0 00 C0 05 A0 20 20 adj 00 83 00 8F 06 05 00 2A 00
VPED
00
VBLK
00
MTXR
00
MTXB
00
AKBP
00
OSD
00
BF
Bus condition (Input initial data, unless otherwise noted. Refer to section 8.1 for the standard data.)
Symbol
00H 01H 02H 05H 0FH 13H 14H 15H 32H 34H 38H 46H 4CH 4FH 50H 51H 52H 53H 54H 5DH 6AH 6BH 6CH 6DH 6EH 6FH 71H 72H 73H 74H 75H 76H 77H 8AH
DEF
00 08 6E 0F 20 02 20 20 05 45 A0 08 91 60 71 adj 00 66 29 80 00 20 20 20 20 20 20 20 20 88 80 80 00 44
FH
FPHU
FPHL
HOUT
HPTW
FV
FPVU
FPVL
VOUT
VDC
EWOUT
EWDC
Rev.1.0, Sep.19.2003, page 21 of 45
M65582AMF-XXXFP
5. Electrical characteristics test method
Y BLOCK
2AG: CVBS OUT output level
1. Input SG.A to pin 16.
2. Measure the amplitude (peak to peak) at pin 15.
Note: Use sub address 01H to select TV1 IN, TV2 IN, TV3 IN, Y(Y/C) IN, Y(YUV) IN.
YOUT: Video standard output level
1. Input SG.A to pin 16.
2. Measure the amplitude (pedestal to top part) at pins 31, 33 and 35.
Note: Use sub address 01H to select TV1 IN, TV2 IN, TV3 IN, Y(Y/C) IN, Y(YUV) IN.
Blanking part
Output waveform
Pedestal
level
M
FY: Video frequency characteristic
1. Input SG.B (f=5MHz, 0.714Vp-p) to pin 16.
2. Measure the amplitude (peak to peak) except blanking part at pins 31, 33 and 35. The amplitude are defined as YB.
3. FY is defined as follows:
FY = 20 log
YB (Vp-p)
YOUT (Vp-p)
Blanking part
Pedestal
level
Output waveform
M
VM: VM output level
1. Input SG.B (f=3.58MHz, 0.714Vp-p) to pin 16.
2. Measure the amplitude (peak to peak) at pin 29.
C BLOCK
ACC1: ACC characteristic 1
1. Input SG.C (fec=feb+50kHz, Veb, Vec; standard level) to pin 16.
2. Measure the amplitude at pin 31. The amplitude is defined as CnorR.
3. And then, input SG.C (fec=feb+50kHz, Veb, Vec; +6dB) to pin 16.
4. Measure the amplitude at pin 31.
5. ACC1 is defined as follows:
ACC1 = 20 log
measured value (Vp-p)
CnorR (Vp-p)
Rev.1.0, Sep.19.2003, page 22 of 45
M65582AMF-XXXFP
ACC2: ACC characteristic 2
1. Input SG.C (fec=feb+50kHz, Veb, Vec; standard level) to pin 16.
2. Measure the amplitude at pin 31. The amplitude is defined as CnorR.
3. And then, input SG.C (fec=feb+50kHz, Veb, Vec; -20dB) to pin 16.
4. Measure the amplitude at pin 31.
5. ACC1 is defined as follows:
ACC2 = 20 log
measured value (Vp-p)
CnorR (Vp-p)
APCU: APC pull-in range (Upper)
APCL: APC pull-in range (Lower)
1. Input SG.C (fec=feb=3.579545MHz) to pin 16.
2. Increase the frequency until the waveform at pin 37 and input signal are asynchronous. And then, decrease the
frequency and note the point when the waveform at pin 37 and input signal are synchronous; fU.
3. Decrease the frequency until the waveform at pin 37 and input signal are asynchronous. And then, increase the
frequency and note the point when the waveform and input signal are synchronous; fL.
4. APCU and APCL are defined as follows:
APCU = fU - 3579545 (Hz)
APCL = fL - 3579545 (Hz)
DEMP: Demodulation phase angle
1. Input SG.D to pin 16.
2. Measure the amplitude at pin 31 (R-Y) and pin 35 (B-Y), and defined as VR-Y and VB-Y respectively.
3. DEMP is defined as follows:
DEMP = 180 - Cos-1
VR-Y (mVp-p)
(deg)
VB-Y (mVp-p)
RGB BLOCK
VPED: Output pedestal voltage
1. Input SG.A (Vy=0V) to pin 16.
2. Measure the voltage of pedestal part at pins 31, 33 and 35.
Blanking part
Output waveform
M
GND
VBLK: Output blanking voltage
1. Input SG.A (Vy=0V) to pin 16.
2. Measure the voltage of blanking part at pins 31, 33 and 35.
Blanking part
Output waveform
M
GND
Rev.1.0, Sep.19.2003, page 23 of 45
M65582AMF-XXXFP
AKBP: AKB reference pulse output level
1. Input SG.A (Vy=0V) to pin 16.
2. Measure the amplitude of AKB reference pulse at pins 31, 33 and 35.
Blanking part
Output waveform
AKB reference pulse
pedestal part
M
MTXRB: Matrix ratio R/B
MTXGB: Matrix ratio G/B
1. Input SG.E (rainbow color bar signal) to pin 16.
2. Measure the amplitude VR, VG and VB at pins 31, 33 and 35, respectively.
3. MTXRB and MTXGB are defined as follows:
VR (mVp-p)
VB (mVp-p)
VG (mVp-p)
MTXGB =
VB (mVp-p)
MTXRB =
Blanking part
Output waveform
M
OSD: OSD output level
1. Input SG.F to pins 16, 57, 58, 59 and 60.
2. Measure the output amplitude at pins 31, 33 and 35 except that at blanking part.
Blanking part
Pedestal
level
Output waveform
M
DEFLECTION BLOCK
FH: Horizontal free-running frequency
1. Measure the output frequency at pin 50 when no signal is input.
FHUP: H-free-up frequency
1. Measure the output frequency at pin 50 when I 2 C bus data of H-free up (Sub 13h D0) is set '1'.no signal is input.
2. FHUP is defined as follows:
FHUP = measured value(Hz) – FH (Hz)
Rev.1.0, Sep.19.2003, page 24 of 45
M65582AMF-XXXFP
FPHU: Horizontal pull-in range (Upper)
FPHL: Horizontal pull-in range (Lower)
1. Input SG.G to pin 16.
2. Change the frequency of SG.G, and measure the frequency when the output signal at pin 50 and the input signal are
synchronous. The horizontal pull-in range is measured by comparing with the horizontal frequency of video
signal.
3. FPHU and FPHL are defined as follows:
FPHU = measured value (Hz) – 15734 (Hz)
FPHL = measured value (Hz) – 15734 (Hz)
HOUT: Horizontal pulse amplitude
1. Input SG.A to pin 16.
2. Measure the amplitude at pin 50.
Output waveform
M
HPTW: Horizontal pulse width
1. Input SG.A to pin 16.
2. Measure the pulse width of output signal at pin 50.
Output waveform
M
FV: Vertical free-running frequency
1. Measure the output frequency at pins 44 and 45 when no signal is input.
FPVU: Vertical pull-in range (Upper)
FPVL: Vertical pull-in range (Lower)
1. Input SG.H to pin 16.
2. Change the vertical frequency of SG.H, and measure the frequency when the output signal at pins 44 and 45 and the
input signal are synchronous.
Rev.1.0, Sep.19.2003, page 25 of 45
M65582AMF-XXXFP
VOUT: Vertical ramp output level
VDC: Vertical ramp output DC voltage
1. Input SG.A to pin 16.
2. Measure the output amplitude at pin 45; VOUT.
3. Measure the DC volatge at pin 45 when the timing is 8.33µsec from start point of vertical ramp; VDC.
Output waveform
VOUT
8.33µsec
VDC
GND
EWOUT: E-W output level
1. Input SG.A to pin 16.
2. Measure the output amplitude at pin 47; EWOUT.
3. Measure the DC volatge at pin 47 when the timing is 8.33µsec from start point of E-W; EWDC.
Output waveform
EWOUT
8.33µsec
EWDC
GND
Rev.1.0, Sep.19.2003, page 26 of 45
M65582AMF-XXXFP
6. Example of the typical characteristics
Note: 1. These characteristics are for reference, and not guaranteed by shipment test.
2. Bus condition is standard, unless otherwise noted (Refer to page 8).
Sharpness
Gamma
10
800
Input SG.B, Vy=0.357V, f=variable
Color=00h
Brightness=FFh
700
Output amplitude (mVp-p)
5
Output gain (dB)
0
-5
-10
-15
-20
Sharpness=00h
Sharpness=20h
Sharpness=3Fh
-25
-30
0
1
2
31
4
5
6
Input SG.A, Vy=variable
Color=00h
600
500
400
300
200
100
7
8
9
0
0
Gamma=00h
Gamma=03h
0
10
20
301
Frequency (MHz)
VM
600
3.0
V aparture gain (dB)
VM output amplitude (V)
3.5
500
400
300
200
80
90
00
2.5
2.0
1.5
1.0
0.5
100
02
04
06
08
0A
0C
0E
0
00
10
02
VM gain data (hex)
04
06
08
0A
0C
0E
10
V aparture gain data (hex)
Color control
Tint control
60
300
Input SG.C, Vy=0.286V, Veb=Vec=0.286V
Brightness=FFh
Input SG.D, Signal is standard level
40
Color phase (deg)
250
Color gain (%)
70
Input SG.A, Vy=0.714V
Color=00h
Input SG.B, Vy=0.714V, f=3.58MHz
200
150
100
20
0
-20
-40
50
0
60
V aparture
700
00
50
4.0
800
0
40
Input luminance level (IRE)
0
10
20
8 30
40
50
Color data (hex)
Rev.1.0, Sep.19.2003, page 27 of 45
60
70
0
-60
0
10
20
8 30
40
50
Tint data (hex)
60
70
0
M65582AMF-XXXFP
Brightness control
Contrast control
1250
3.2
Input SG.A, Vy=variable
Color=00h
ACL: OFF, ABL: OFF
1000
750
500
250
0
10
20
8 30
40
50
60
70
2.8
2.6
2.4
2.2
2.0
1.8
Vy=0.714V
Vy=0.357V
0
Input SG.A, Vy=variable
Color=00h
ACL: OFF, ABL: OFF
3.0
Output pedestal voltage (V)
Output Video amplitude (mVp-p)
1500
1.6
0
Vy=0.0V
Vy=0.714V
0
20
40
60
Contrast data (hex)
Cutoff control
C0
E0
100
60
70
0
5
Input SG.A, Vy=0.0V
Color=00h
ACL: OFF, ABL: OFF
3.2
Input SG.A, Vy=0.714V
Color=00h
ACL: OFF, ABL: OFF
4
3
3.1
Output Signal gain (dB)
Output pedestal voltage (V)
A0
Drive control
3.3
3.0
2.9
2.8
2.7
2.6
2.5
2
1
0
-1
-2
-3
-4
0
40
80
C0
100
140
180
1C0
-5
200
0
10
20
Cutoff data (hex)
ACL characteristic
Input SG.A, Vy=0.714V
Color=00h
Brightness=40h
Analog ACL: ON
500
400
300
200
100
0
50
ABL characteristic
600
0
40
3.5
Video output DC voltage (V)
700
8 30
Drive data (hex)
800
Video output amplitude (mVp-p)
80
Brightness data (hex)
Input SG.A, Vy=0.714V
Color=00h
Brightness=FFh
Digital ABL: ON
Digital ABL Gain=00h
Digital ABL Gain=08h
Digital ABL Gain=0Fh
3.0
2.5
2.0
Analog ACL Gain=00h
Analog ACL Gain=01h
0.5
1.0
1.5
2.0
2.5
ACL input voltage (V)
Rev.1.0, Sep.19.2003, page 28 of 45
3.0
3.5
4.0
1.5
0
0.5
1.0
1.5
2.0
2.5
ACL input voltage (V)
3.0
3.5
4.0
M65582AMF-XXXFP
DCT
H-phase
3.3
8
Input SG.A, Vy=variable
Color=00h, Brightness=80h
Contrast=40h, DCTV=1Eh
3.2
Input SG.A, Vy=0.714V
pin 48=1.65V
Color=00h
ACL: OFF, ABL: OFF
7
3.1
Input signal
6
3.0
Time (µsec)
Output DC Voltage (V)
DCT Gain=00h
DCT Gain=10h
DCT Gain=1Fh
2.9
2.8
H OUT
5
4
2.7
3
2.6
2.5
0
10
20
30
40
50
60
70
80
90
2
100
00
08
10
18
Angle
Input SG.A, Vy=0.714V
pin 48=1.65V
H-phase=20h
Angle=20h
Angle=00h
Angle=20h
Angle=3Fh
Input signal
H OUT
38
40
Bow=00h
Bow=20h
Bow=3Fh
Input signal
H OUT
6
Time (µsec)
Time (µsec)
6
5
4
5
4
0
2
4
16
8
10
12
14
6
3
18
0
2
4
16
8
10
12
14
6
18
Time (msec)
Time (msec)
H-correction
EHT
1.2
VRAMP(–) Output amplitude (Vp-p)
8
7
6
Time (µsec)
30
7
Input SG.A, Vy=0.714V
pin 48=1.65V
H-phase=20h
Bow=20h
5
Input SG.A, Vy=0.714V
H-phase=20h
Color=00h
ACL: OFF, ABL: OFF
4
Input signal
3
H OUT
2
28
Bow
7
3
20
H-phase data (hex)
Input luminance level (IRE)
0
0.5
1.0
1.5
2.0
2.5
3.0
H-correction input voltage (V)
Rev.1.0, Sep.19.2003, page 29 of 45
3.5
4.0
1.15
1.1
Input SG.A, Vy=0.714V
EHT Mode=00h
V-position=20h
V-size=20h
V-Linearity=20h
S-correction=00h
1.05
EHT Gain=00h
EHT Gain=08h
EHT Gain=0Fh
1.0
0
0.5
1.0
4 1.5
2.0
2.5
ACL input voltage (V)
3.0
3.5
.0
M65582AMF-XXXFP
V-size
V-position
2.5
Input SG.A, Vy=0.714V
V-size=20h
V-Linearity=20h
S-correction=00h
VRAMP(–) Output voltage (V)
VRAMP(–) Output voltage (V)
2.5
2.0
1.5
1.0
V-positon=00h
V-positon=20h
V-positon=3Fh
0.5
0
2
4
16
8
10
12
14
6
Input SG.A, Vy=0.714V
V-position=20h
V-Linearity=20h
S-correction=00h
2.0
1.5
1.0
V-size=00h
V-size=20h
V-size=3Fh
0.5
18
0
2
4
16
Time (msec)
Input SG.A, Vy=0.714V
V-position=20h
V-size=20h
S-correction=00h
VRAMP(–) Output voltage (V)
VRAMP(–) Output voltage (V)
12
14
6
18
2.5
2.0
1.5
1.0
V-linearity=00h
V-linearity=20h
V-linearity=3Fh
0
2
4
16
8
10
12
14
6
Input SG.A, Vy=0.714V
V-position=20h
V-size=20h
V-Linearity=20h
2.0
1.5
1.0
S-correction=00h
S-correction=3Fh
0.5
18
0
2
4
16
Time (msec)
8
10
12
14
6
18
12
14
6
18
Time (msec)
H-Size
Parabola
2.5
2.5
Input SG.A, Vy=0.714V
Parabola=20h
Trapezium=20h
Upper-Corner=20h
Lower-Corner=20h
2.0
Input SG.A, Vy=0.714V
H-Size=20h
Trapezium=20h
Upper-Corner=20h
Lower-Corner=20h
H-Size=00h
H-Size=20h
H-Size=3Fh
E-W Output voltage (V)
E-W Output voltage (V)
10
S-correction
V-linearity
2.5
0.5
8
Time (msec)
1.5
1.0
2.0
1.5
1.0
Parabora=00h
Parabora=20h
Parabora=3Fh
0.5
0
2
4
16
8
10
Time (msec)
Rev.1.0, Sep.19.2003, page 30 of 45
12
14
6
18
0.5
0
2
4
16
8
10
Time (msec)
M65582AMF-XXXFP
Upper-Corner
Lower-Corner
2.5
Input SG.A, Vy=0.714V
H-Size=20h
Parabola=20h
Trapezium=20h
Lower-Corner=20h
2.0
E-W Output voltage (V)
E-W Output voltage (V)
2.5
1.5
1.0
0.5
Upper-Corner=00h
Upper-Corner=10h
Upper-Corner=20h
Upper-Corner=30h
Upper-Corner=3Fh
0
2
4
16
8
10
12
14
6
18
Trapezium
E-W Output voltage (V)
2.5
Input SG.A, Vy=0.714V
H-Size=20h
Parabola=20h
Upper-Corner=20h
Lower-Corner=20h
1.5
1.0
Trapezium=00h
Trapezium=20h
Trapezium=3Fh
0.5
0
2
4
16
8
10
Time (msec)
Rev.1.0, Sep.19.2003, page 31 of 45
2.0
1.5
1.0
0.5
Lower-Corner=00h
Lower-Corner=10h
Lower-Corner=20h
Lower-Corner=30h
Lower-Corner=3Fh
0
2
4
16
8
10
Time (msec)
Time (msec)
2.0
Input SG.A, Vy=0.714V
H-Size=20h
Parabola=20h
Trapezium=20h
Upper-Corner=20h
12
14
6
18
12
14
6
18
M65582AMF-XXXFP
Electrical characteristics (MCU part)
1. Electrical characteristics
(VDD=55%, VSS=0V, f(XIN)=8MHz, Ta=-20°C to 70°C, unless otherwise noted)
Limits
Parameter
Power source current
Symbol
System
operation
Min.
Icc
Wait mode
HIGH output voltage
P10-P16, P20-P27,
P40-P45
LOW output voltage
P00-P07,P10, P15, P16,
P20-P27, P40-P45
VOH
VOL
LOW output voltage
P11-P14,
Test
Circuit
Test
conditions
Typ.
Max.
Unit
15
30
mA
VDD=5.25V,
f(XIN)-8MHz
30
45
60
200
µA
2
4
mA
VDD=5.25V, f(XIN)=0,
f(XCIN)=32kHz, OSD OFF,
Data slicer OFF, Low-power
dissipation mode set
(CM5="0", CM6="1")
VDD=5.25V, f(XIN)-8MHz
25
100
µA
1
10
VDD=5.25V, f(XIN)=0,
f(XCIN)=32kHz, OSD OFF,
Data slicer OFF, Low-power
dissipation mode set
(CM5="0", CM6="1")
VDD=5.25V, f(XIN)=0,
f(XCIN)=0
V
VDD=4.75V, IOH=-0.5mA
V
VDD=4.75V, IOH=0.5mA
2.4
0.4
0.4
0.6
VDD=4.75V
OSD OFF
Data slicer
OFF
OSD ON
1
2
IOL=3mA
IOL=6mA
Hysteresis (See note 1)
RESET, INT1, INT2,
INT3, TIM2, TIM3, SIN,
SCLK, SCL1, SCL2,
SDA1, SDA2
HIGH input leak current
P00-P07, P10-P16,
P20-P27, P40-P45,
RESET
VT+VT-
1.3
V
VDD=5.0V
3
IIZH
5
µA
VDD=5.25V, VI=5.25V
4
LOW input leak current
P00-P07, P10-P16,
P20-P27, P40-P45,
RESET
2
I C-BUS·BUS switch
connection resistor
(between SCL1 and
SCL2, SDA1 and SDA2)
IIZL
5
µA
VDD=5.25V, VI=0V
4
RBS
130
Ω
VDD=4.75V
5
Notes : 1. P06, P07, P23-P25 have the hysteresis when these pins are used as interrupt input pins or timer input pins.
P11-P14
2
have the hysteresis when these pins are used as multi-master I C-BUS interface ports. P20-P22 have the
hysteresis when these pins are used as serial I/O pins.
Rev.1.0, Sep.19.2003, page 32 of 45
M65582AMF-XXXFP
2. Test circuit
Power source voltage
4.75V
1
2
A
Icc
Vdd
Vdd
XIN
8.00MHz
OSD
clock
XOUT
28.64MHz
Each output pin
V
Vss
Vss
Pin Vdd is made the operation state and is
measured the circuit, with a ceramic resonator.
VOH
or
VOL
After setting each output pin to HIGH level when measuring
VOH and to LOW level when measuring VOL, each pin is
measured
5.0V
5.25V
3
4
Vdd
Vdd
IIZH or IIZL
Each input pin
Each input pin
Vss
Vss
4.75V
5
Vdd
SCL1 or SDA1
IBS
A
RBS
SCL2 or SDA2
VBS
Vss
RBS = VBS/IBS
After setting each output pin OFF state, each pin is measured.
( 4 , 5 )
Rev.1.0, Sep.19.2003, page 33 of 45
IOH
or
IOL
A
M65582AMF-XXXFP
Application example
VDD(9V)
VDD(5V)
VDD(3.3V)
Note: If you will apply this application example to practice, please study it fully.
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
47µ
10K
X1: Murata CSA8.00MTZ (8.00MHz)
X2: SIWARD 1-781-377-21 (14.31818MHz)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
15p
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
10K
10K
10K
X1
15p
+
47µ 0.01µ
+
10K
10K
10K
10K
1K
220p
0.1µ
Reset IC
10K
10K
1M
12
+
13
0.1µ
47µ
1µ
+
52
14
3.3V
50
16
49
17
48
Y(Y/C) IN
18
47
C(Y/C) IN
19
46
20
45
21
44
22
43
23
42
24
41
0.1µ
47µ 0.01µ
3.3V
470p
10K
H OUT
560
TV1 IN
+
47µ
22µ
51
15
1000p
3.3V
10K
53
M65582AMF-XXXFP
AKB IN
+
+
47µ 0.01µ
ABCL IN
10K
FBP IN
H Correction
100
0.1µ
3.3V
2K
0.01µ
0.01µ
0.1µ
TV3 IN
0.1µ
0.01µ
0.01µ
10µ
+
0.1µ
+
TV2 IN
0.1µ
+
1µ
10K
0.1µ
47µ
+
0.01µ
0.033µ
1µ
6.8K
+
0.22µ 1K
47µ
47µ
47µ
0.01µ
0.01µ
220K
22p
2.2K
X2
+
3.3K
22
47µ 0.01µ
+
0.1µ
47µ 0.01µ
0.1µ
0.1µ
V(YUV) IN
Y(YUV) IN
U(YUV) IN
0.1µ
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
–
6.8K
–
V-RAMP(+)
+
+
+
6.8K
Rev.1.0, Sep.19.2003, page 34 of 45
+
0.01µ
+
+
+
+
3.3K
G_OUT
E-W
–
1K
–
1K
1µ
–
6.8K
3.3K
3.3K
3.3K
1K
3.3K
+
0.01µ
+
1K
VM_OUT
1K
–
B_OUT
+
1µ
–
R_OUT
3.3K
1K
3.3K
3.3K
6.8K
2.4K
V-RAMP(–)
M65582AMF-XXXFP
Description of Pin
Pin No.
Name
Note
Peripheral circuit of pins
0V
2
2
CN VSS
3
X IN
4
X OUT
3
4
5
Vss (MCU)
Power source for
MCU.
0V
6
Vdd (MCU)
Power source for
MCU.
5.0V ± 5%
7
7
FILT
Y
Rev.1.0, Sep.19.2003, page 35 of 45
M65582AMF-XXXFP
Pin No.
Name
Note
Peripheral circuit of pins
8
HLF
8
9
VHOLD
9
10
CVIN
10
Impedance=N.A.
(Additional filter on
PCB board)
CMOS INPUT
Impedance>100kΩ
11
12
13
RESET
Vss(Digital)
Vdd(Digital)
Rev.1.0, Sep.19.2003, page 36 of 45
Y
11
VOL = 0V :
Reset state
VOH = 5V :
Release from Reset
state
Power source for
Digital blocks.
0V
Power source for
Digital blocks.
3.3V ± 5%
M65582AMF-XXXFP
Pin No.
Name
14
DCT FILTER
Note
Peripheral circuit of pins
Impedance=N.A.
14
15
Impedance=150Ω
CVBS OUT
15
16
18
21
23
25
TV1 IN
Y(Y/C) IN
TV2 IN
TV3 IN
Y(YUV) IN
17
Vdd(Input)
19
C(Y/C) IN
DC : 0.55V (sync)
AC : 1.75Vp-p (typ.)
16
18
21
23
25
DC : 0.5V (sync)
AC : 1.0Vp-p (typ.)
Power source for
A/D etc.
3.3V ± 5%
Impedance=5kΩ
19
Rev.1.0, Sep.19.2003, page 37 of 45
Impedance=N.A.
DC : 1.0V
AC : 0.286Vp-p
(burst)
M65582AMF-XXXFP
Pin No.
Name
20
Vss(Input)
22
24
VRT
VRB
Note
Peripheral circuit of pins
Power source for
A/D etc.
0V
Impedance=50Ω
22
DC : 1.7V (VRT)
0.5V (VRB)
24
26
27
Impedance=N.A.
U(YUV) IN
V(YUV) IN
26
27
28
Impedance=400Ω
VZ OUT
28
29
31
33
35
VM
R OUT
G OUT
B OUT
Rev.1.0, Sep.19.2003, page 38 of 45
DC : 1.0V
AC : 0.7Vp-p (typ.)
DC : 2.05V
Impedance=500Ω
29
31
33
35
DC : 1.65V (VM)
3V (blanking)
M65582AMF-XXXFP
Pin No.
Name
Note
Peripheral circuit of pins
30
Vdd(Output)
Power source for
D/A etc.
3.3V±5%
32
Vss(Output)
Power source for
D/A etc.
0V
34
Vdd(VCXO)
Power source for
VCXO etc.
3.3V±5%
36
Vss(DEF)
Power source for
Deflection block.
0V
37
XTAL (NTSC)
Impedance 1kΩ
37
38
N.C.
39
TEST
Not useful
(Connect 0.01µF or more
capacitor externally)
39
40
APC FILTER
40
Rev.1.0, Sep.19.2003, page 39 of 45
Impedance=N.A.
(Additional filter on
PCB board)
M65582AMF-XXXFP
Pin No.
Name
41
AFC1 FILTER
Note
Peripheral circuit of pins
Impedance=N.A.
(Additional filter on
PCB board)
41
DC : 1.65V
42
Power source for
Deflection blocks.
Vdd(DEF)
3.3V± 5%
43
VRAMP C
Impedance 12.5kΩ
43
44
45
47
VRAMP(–)
VRAMP(+)
E-W
46
HVCO FB
Impedance 20kΩ
44
45
47
AC : 1.0Vpp (typ.)
Impedance=N.A.
(Additional filter on
PCB board)
46
DC : 1.65V
48
Impedance>1MΩ
Input voltage range :
0 to 3.3V
H CORRE
48
0V : H OUT +2.2µsec
3.3V : H OUT –2.2µsec
Rev.1.0, Sep.19.2003, page 40 of 45
M65582AMF-XXXFP
Pin No.
49
Name
Note
Peripheral circuit of pins
CMOS INPUT
FBP IN
Impedance>100kΩ
Y
50
H OUT
49
VIL=0V : RGB output
VIH=3.3V : Blanlking
A
CMOS IN/OUT 1
50
C
Impedance>100kΩ
(input)
Impedance<100Ω
(output)
Y
51
52
AKB IN
ACL IN
51
Input voltage range :
0 to 3.3V
52
14
53
54
55
56
P14/SDA2
P13/SDA1
P12/SCL2
P11/SCL1
B
C
53
54
55
56
A
Y
Rev.1.0, Sep.19.2003, page 41 of 45
CMOS IN/OUT 1
Impedance>100kΩ
(input)
Impedance<100Ω
(output)
M65582AMF-XXXFP
Pin No.
53
54
55
56
Name
P14/SDA2
P13/SDA1
P12/SCL2
P11/SCL1
Note
Peripheral circuit of pins
B
C
53
54
55
56
A
CMOS IN/OUT 1
Impedance>100kΩ
(input)
Impedance<100Ω
(output)
Y
57
58
59
60
61
65
67
P40
P41
P42
P43
P10
P44
P45
C
A
Y
62
63
64
71
P00/PWM0
P01/PWM1
P02/PWM2
P07/INT1
57
58
59
60
61
65
67
62
63
64
CMOS IN/OUT 1
Impedance>100kΩ
(input)
Impedance<100Ω
(output)
CMOS IN/OUT
Impedance>100kΩ
(input)
Impedance<100Ω
(output)
Y
66
68
69
70
P03/PWM3/AD1
P04/PWM4/AD2
P05/AD3
P06/INT2/AD4
66
68
69
70
Y
Rev.1.0, Sep.19.2003, page 42 of 45
CMOS IN/OUT
Impedance>100kΩ
(input)
Impedance<100Ω
(output)
M65582AMF-XXXFP
Pin No.
72
73
77
78
79
Name
P15
P16
P23/TIM3
P24/TIM2
P25/INT3
Note
Peripheral circuit of pins
C
CMOS IN/OUT 1
72
73
77
78
79
A
Impedance>100kΩ
(input)
Impedance<100Ω
(output)
Y
74
75
76
P20/SCLK/AD5
P21/SOUT/AD6
P22/SIN/AD7
C
CMOS IN/OUT
74
75
76
A
Impedance>100kΩ
(input)
Impedance<100Ω
(output)
Y
80
1
P26/XCIN
P27/XCOUT
80
1
Rev.1.0, Sep.19.2003, page 43 of 45
M65582AMF-XXXFP
Memory Map
M65582AMF-XXXFP
1000016
000016
RAM
(2048 bytes)
00BF16
00C016
00FF16
010016
SFR1 area
Zero page
01FF16
020016
020F16
SFR2 area
Not used
Not used
030016
ROM correction function
Vector 1: addresses 030016
Vector 2: addresses 032016
032016
05BF16
06FF16
Not used
OSD RAM
(128 bytes)
OSD ROM 1140016
(10k bytes) 13BFF16
080016
087F16
Not used
090016
0B3F16
Not used
100016
Not used
ROM
(60k bytes)
FF0016
FFDE16
FFFF16
Special page
Interrupt vector area
Rev.1.0, Sep.19.2003, page 44 of 45
1FFFF16
Rev.1.0, Sep.19.2003, page 45 of 45
e
y
b
40
x
41
24
65
64
25
D
HD
JEDEC Code
—
1
80
EIAJ Package Code
LQFP80-P-1420-0.8
Weight(g)
M
F
E
HE
Detail F
A
Lp
L
L1
Under Planning
Lead Material
Cu Alloy
b2
I2
MD
ME
x
y
A3
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
Symbol
Dimension in Millimeters
Min
Nom
Max
1.6
—
—
0.2
0.125
0.05
1.4
—
—
0.32
0.37
0.47
0.125
0.175
0.105
13.9
14.1
14.0
19.9
20.1
20.0
0.8
—
—
16.0
15.8
16.2
21.8
22.2
22.0
0.65
0.35
0.5
1.0
—
—
0.6
0.75
0.45
—
0.25
—
—
—
0.2
—
—
0.1
—
0˚
8˚
—
—
0.225
—
—
10
—
14.4
—
—
—
20.4
Recommended Mount Pad
l2
MD
Plastic 80pin 14✕20mm body LQFP
e
b2
MMP
A2
A1
ME
80P6U-A
M65582AMF-XXXFP
Package Dimensions
A3
c
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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