M68AW256M 4 Mbit (256K x16) 3.0V Asynchronous SRAM FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 2.7 to 3.6V 256K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns, 70ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN TSOP44, and TFBGA48 PACKAGES – Compliant with Lead-Free Soldering Processes – Standard or Lead-Free Option Figure 1. Packges 44 1 TSOP44 Type II (ND) FBGA TFBGA48 (ZH) 6 x 8mm FBGA TFBGA48 (ZB) 7 x 8mm April 2004 1/23 M68AW256M TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Figure 5. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . . 12 Figure 10.Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . 12 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 13.UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 14.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 15.TSOP44 II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . . . . . 18 Table 10. TSOP 44 II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . 18 Figure 16.TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Bottom View Package Outline19 Table 11. TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Package Mechanical Data . . 19 Figure 17.TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . 20 2/23 M68AW256M Table 12. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 20 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3/23 M68AW256M SUMMARY DESCRIPTION The M68AW256M is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 262,144 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW256 is available in TFBGA48 (6x8mm - 6x8 active ball array, 0.75mm pitch), TFBGA48 (7x8mm - 6x8 active ball array, 0.75 mm pitch) and in TSOP44 Type II packages. In addition to the standard version, both packages are also available in Lead-free version, in compliance with the JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. Figure 2. Logic Diagram Table 1. Signal Names A0-A17 Address Inputs DQ0-DQ15 Data Input/Output E Chip Enable G Output Enable W Write Enable UB Upper Byte Enable Input LB Lower Byte Enable Input G VCC Supply Voltage UB VSS Ground NC Not Connected Internally DU Don’t Use as Internally Connected VCC 18 16 A0-A17 DQ0-DQ15 W E M68AW256M LB VSS AI04870b 4/23 M68AW256M Figure 3. TSOP Connections A4 A3 A2 A1 A0 E DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 W A16 A15 A14 A13 A12 44 1 2 43 42 3 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 M68AW256M 12 33 13 32 14 31 15 30 16 29 28 17 27 18 26 19 25 20 24 21 22 23 A5 A6 A7 G UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 A17 AI04871b 5/23 M68AW256M Figure 4. TFBGA Connections (Top view through package) 1 2 3 4 5 6 A LB G A0 A1 A2 NC B DQ8 UB A3 A4 E DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSS DQ11 A17 A7 DQ3 VCC E VCC DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 W DQ7 H NC A8 A9 A10 A11 DU AI03955 6/23 M68AW256M Figure 5. Block Diagram VCC VSS A17 ROW DECODER MEMORY ARRAY A7 DQ15 (8) I/O CIRCUITS UB COLUMN DECODER DQ0 (8) LB A0 A6 (8) UB W UB E (8) LB LB G AI04833 7/23 M68AW256M OPERATION The device has four standard operating modes: Output Disabled, Read, Write and Standby/Power-Down. These modes are determined by the control inputs E, W, G, LB and UB as summarized in Table 2., Operating Modes. Output Disabled. The Output Enable signal, G, provides high-speed tri-state control of DQ0DQ15, allowing fast read/write cycles on the I/O data bus. The device is in Output Disabled mode when Output Enable, G, is High. In this mode, LB and UB are Don’t care and DQ0-DQ15 are high impedance. Read Mode. The M68AW256M is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight or sixteen, depending on the status of the signal UB and LB, of the 4,194,304 locations in the static memory array, specified by the 18 address inputs.If only one of the Byte Enable inputs is at VIL, the M68AW256M is in Byte Read mode. If the two Byte Enable inputs are at VIL, the M68AW256M is in Word Read mode. So depending on the status of the UB and LB signals, valid data will be available on the lower eight, the upper eight or all sixteen output pins, tAVQV after the last stable address, providing G is Low and E is Low. If either of E or G is asserted after tAVQV has elapsed, data access will be measured from the limiting parameter (tELQV, tGLQV or tBLQV) rather than the address. Data out may be indeterminate at tELQX, tGLQX and tBLQX but data lines will always be valid at tAVQV. Write Mode. The M68AW256M is in the Write mode whenever the W and E are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. When E (W) is Low, and UB or LB is Low, write cycle begins on the W (E)'s falling edge. When E and W are Low, and UB = LB = High, write cycle begins on the first falling edge of UB or LB. Therefore, address setup time is referenced to Write Enable, Chip Enable or UB/LB as tAVWL, tAVEL and tAVBL respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E, W or UB/LB. If the Output is enabled (E = Low, G = Low, LB or UB = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E, or for tDVBH before the rising edge of UB/LB whichever occurs first, and remain valid for tWHDX, tEHDX and tBHDX respectively. Standby/Power-Down. The M68AW256M has a Chip Enable power down feature which invokes an automatic standby mode whenever either Chip Enable is de-asserted (E = High) or LB and UB are de-asserted (LB and UB = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E, LB and UB as summarized in the Operating Modes table (see Table 2). Table 2. Operating Modes Operation E W G LB UB DQ0-DQ7 DQ8-DQ15 Power Deselected (Standby/Power-Down) VIH X X X X Hi-Z Hi-Z Standby (ISB) X X X VIH VIH Hi-Z Hi-Z Standby (ISB) Lower Byte Read VIL VIH VIL VIL VIH Data Output Hi-Z Active (ICC) Lower Byte Write VIL VIL X VIL VIH Data Input Hi-Z Active (ICC) Output Disabled VIL VIH VIH X X Hi-Z Hi-Z Active (ICC) Upper Byte Read VIL VIH VIL VIH VIL Hi-Z Data Output Active (ICC) Upper Byte Write VIL VIL X VIH VIL Hi-Z Data Input Active (ICC) Word Read VIL VIH VIL VIL VIL Data Output Data Output Active (ICC) Word Write VIL VIL X VIL VIL Data Input Data Input Active (ICC) Output Disabled VIH X VIH X X Hi-Z Hi-Z Active (ICC) Note: 1. X = VIH or VIL. 8/23 M68AW256M MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute Maximum Ratings Symbol Value Unit 20 mA Ambient Operating Temperature –55 to 125 °C TSTG Storage Temperature –65 to 150 °C TLEAD Lead Temperature during Soldering(2) 260(3) °C –0.5 to 4.6 V –0.5 to VCC +0.5 V 1 W IO (1) TA VCC VIO (4) PD Parameter Output Current Supply Voltage Input or Output Voltage Power Dissipation Note: 1. One output at a time, not to exceed 1 second duration. 2. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assermbly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 3. Not exceeding 250°C for more than 30s, and peaking at 260°C. 4. Up to a maximum operating VCC of 3.6V only. 9/23 M68AW256M DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 4. Operating and AC Measurement Conditions Parameter M68AW256M VCC Supply Voltage 2.7 to 3.6V Range 1 0 to 70°C Range 6 –40 to 85°C Ambient Operating Temperature Load Capacitance (CL) 30pF Output Circuit Protection Resistance (R1) 3.0kΩ Load Resistance (R2) 3.1kΩ Input Rise and Fall Times 1ns/V 0 to VCC Input Pulse Voltages Input and Output Timing Ref. Voltages VCC/2 Output Transition Timing Ref. Voltages VRL = 0.3VCC; VRH = 0.7VCC Figure 6. AC Measurement I/O Waveform Figure 7. AC Measurement Load Circuit VCC I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST OUT CL Output Timing Reference Voltage VCC 0V R2 0.7VCC 0.3VCC AI05831 CL includes probe and 1 TTLcapacitance AI05832 10/23 M68AW256M Table 5. Capacitance CIN COUT Test Condition Parameter(1,2) Symbol Input Capacitance on all pins (except DQ) Output Capacitance Min Max Unit VIN = 0V 8 pF VOUT = 0V 10 pF Note: 1. Sampled only, not 100% tested. 2. At TA = 25°C, f = 1 MHz, VCC = 3.0V. Table 6. DC Characteristics -L Symbol Parameter Unit Min ICC1 (1,2) Operating Supply Current ICC2 (3) Operating Supply Current ISB Standby Supply Current CMOS ILI Input Leakage Current ILO Output Leakage Current VIH -N Test Condition Max Min Max 70ns 20 10 mA 55ns 26 15 mA VCC = 3.6V, f = 1MHz, IOUT = 0mA 2 2 mA VCC = 3.6V, f = 0, E ≥ VCC –0.2V or LB=UB ≥ VCC –0.2V 20 20 µA VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA 0V ≤ VIN ≤ VCC –1 1 –1 1 µA 0V ≤ VOUT ≤ VCC (4) –1 1 –1 1 µA Input High Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL Input Low Voltage –0.3 0.6 – 0.3 0.6 V VOH Output High Voltage IOH = –1.0mA VOL Output Low Voltage IOL = 2.1mA Note: 1. 2. 3. 4. 2.4 2.4 0.4 V 0.4 V Average AC current, cycling at tAVAV minimum. E = VIL, LB OR/AND UB = VIL, VIN = VIL OR VIH. E ≤ 0.2V, LB OR/AND UB ≤ 0.2V, VIN ≤ 0.2V OR VIN ≥ VCC –0.2V. Output disabled. Figure 8. Address Controlled, Read Mode AC Waveforms tAVAV A0-A17 VALID tAVQV DQ0-DQ7 and/or DQ8-DQ15 tAXQX DATA VALID AI03956b Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low. 11/23 M68AW256M Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV A0-A17 VALID tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ15 VALID tBLQV tBHQZ UB, LB tBLQX AI03957c Note: Write Enable (W) = High. Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms E, UB, LB ICC ISB tPU tPD 50% AI03856 12/23 M68AW256M Table 7. Read and Standby Mode AC Characteristics M68AW256M Symbol Parameter Unit 55 70 tAVAV Read Cycle Time Min 55 70 ns tAVQV Address Valid to Output Valid Max 55 70 ns Data hold from address change Min 5 5 ns tBHQZ (2,3) Upper/Lower Byte Enable High to Output Hi-Z Max 20 25 ns tBLQV Upper/Lower Byte Enable Low to Output Valid Max 55 70 ns Upper/Lower Byte Enable Low to Output Transition Min 5 5 ns tEHQZ (2,3) Chip Enable High to Output Hi-Z Max 20 25 ns tELQV Chip Enable Low to Output Valid Max 55 70 ns Chip Enable Low to Output Transition Min 5 5 ns tGHQZ (2,3) Output Enable High to Output Hi-Z Max 20 25 ns tGLQV Output Enable Low to Output Valid Max 25 35 ns Output Enable Low to Output Transition Min 5 5 ns tPD (4) Chip Enable or UB/LB High to Power Down Max 0 0 ns tPU (4) Chip Enable or UB/LB Low to Power Up Min 55 70 ns tAXQX (1) tBLQX (1) tELQX (1) tGLQX (2) Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX, tBHQZ is less than tBLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters. 13/23 M68AW256M Figure 11. Write Enable Controlled, Write AC Waveforms tAVAV A0-A17 VALID tAVWH tELWH tWHAX E tWLWH tAVWL W tWHQX tWLQZ tWHDX DQ0-DQ15 DATA INPUT tDVWH tBLWH UB, LB AI03958c Figure 12. Chip Enable Controlled, Write AC Waveforms tAVAV VALID A0-A17 tAVEH tAVEL tELEH tEHAX E tWLEH W tEHDX DATA INPUT DQ0-DQ15 tDVEH tBLEH UB, LB AI03959c 14/23 M68AW256M Figure 13. UB/LB Controlled, Write AC Waveforms tAVAV A0-A17 VALID tAVBH tBHAX tELBH E tWLBH W tBHDX DQ0-DQ15 DATA (1) DATA INPUT tDVBH tAVBL tBLBH UB, LB AI03987c Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied. 15/23 M68AW256M Table 8. Write Mode AC Characteristics M68AW256M Symbol Parameter Unit 55 70 tAVAV Write Cycle Time Min 55 70 ns tAVBH Address Valid to LB, UB High Min 45 60 ns tAVBL Addess Valid to LB, UB Low Min 0 0 ns tAVEH Address Valid to Chip Enable High Min 45 60 ns tAVEL Address valid to Chip Enable Low Min 0 0 ns tAVWH Address Valid to Write Enable High Min 45 60 ns tAVWL Address Valid to Write Enable Low Min 0 0 ns tBHAX LB, UB High to Address Transition Min 0 0 ns tBHDX LB, UB High to Input Transition Min 0 0 ns tBLBH LB, UB Low to LB, UB High Min 45 60 ns tBLEH LB, UB Low to Chip Enable High Min 45 60 ns tBLWH LB, UB Low to Write Enable High Min 45 60 ns tDVBH Input Valid to LB, UB High Min 25 30 ns tDVEH Input Valid to Chip Enable High Min 25 30 ns tDVWH Input Valid to Write Enable High Min 25 30 ns tEHAX Chip Enable High to Address Transition Min 0 0 ns tEHDX Chip enable High to Input Transition Min 0 0 ns tELBH Chip Enable Low to LB, UB High Min 45 60 ns tELEH Chip Enable Low to Chip Enable High Min 45 60 ns tELWH Chip Enable Low to Write Enable High Min 45 60 ns tWHAX Write Enable High to Address Transition Min 0 0 ns tWHDX Write Enable High to Input Transition Min 0 0 ns Write Enable High to Output Transition Min 5 5 ns tWLBH Write Enable Low to LB, UB High Min 45 60 ns tWLEH Write Enable Low to Chip Enable High Min 45 60 ns Write Enable Low to Output Hi-Z Max 20 20 ns -L version Min 45 60 ns -N version Min 40 50 ns tWHQX (1) tWLQZ (1,2) tWLWH Write Enable Low to Write Enable High Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 16/23 M68AW256M Figure 14. Low VCC Data Retention AC Waveforms DATA RETENTION MODE 3.6V VCC 2.7V VDR > 1.5V tCDR tR E ≥ VDR – 0.2V or UB=LB ≥ VDR – 0.2V E, UB/LB AI03989 Table 9. Low VCC Data Retention Characteristics Symbol Parameter ICCDR (1) Supply Current (Data Retention) Test Condition VCC = 1.5V, E ≥ VCC –0.2V or UB = LB ≥ VCC –0.2V, f = 0 (3) Chip Deselected to Data tCDR (1,2) Retention Time tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention) Min E ≥ VCC –0.2V or UB = LB ≥ VCC –0.2V, f = 0 Typ Max Unit 4.5 9 µA 0 ns tAVAV ns 1.5 V Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤ 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V. 17/23 M68AW256M PACKAGE MECHANICAL Figure 15. TSOP44 II - 44 lead Plastic Thin Small Outline Type II, Package Outline D N E1 1 E N/2 ZD b e A2 A C A1 CP α L TSOP-d Note: Drawing is not to scale. Table 10. TSOP 44 II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data Symbol millimeters Typ Min A Max Typ Min 1.200 Max 0.0472 A1 0.050 0.150 0.0020 0.0059 A2 0.950 1.050 0.0374 0.0413 0.0047 0.0083 b 0.350 c 0.0138 0.120 0.210 D 18.410 – – 0.7248 – – E 11.760 – – 0.4630 – – E1 10.160 – – 0.4000 – – e 0.800 – – 0.0315 – – L 0.500 0.400 0.600 0.0197 0.0157 0.0236 ZD 0.805 – – 0.0317 – – 0 5 0 5 alfa CP N 18/23 inches 0.100 44 0.0039 44 M68AW256M Figure 16. TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Bottom View Package Outline D D1 FD FE SD SE BALL "A1" E E1 ddd e e b A A2 A1 BGA-Z26 Note: Drawing is not to scale. Table 11. TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 A1 0.0472 0.260 A2 0.0102 0.900 b Max 0.350 0.450 0.0354 0.0138 0.0177 D 6.000 5.900 6.100 0.2362 0.2323 0.2402 D1 3.750 – – 0.1476 – – ddd 0.100 0.0039 E 8.000 7.900 8.100 0.3150 0.3110 0.3189 E1 5.250 – – 0.2067 – – e 0.750 – – 0.0295 – – FD 1.125 – – 0.0443 – – FE 1.375 – – 0.0541 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – – 19/23 M68AW256M Figure 17. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline D D1 FD FE SD SE E E1 BALL "A1" ddd e e b A A2 A1 BGA-Z22 Note: Drawing is not to scale. Table 12. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 A1 0.0472 0.260 A2 0.0102 0.900 b Max 0.350 0.450 0.0354 0.0138 0.0177 D 7.000 6.900 7.100 0.2756 0.2717 0.2795 D1 3.750 – – 0.1476 – – ddd 0.100 0.0039 E 8.000 7.900 8.100 0.3150 0.3110 0.3189 E1 5.250 – – 0.2067 – – e 0.750 – – 0.0295 – – FD 1.625 – – 0.0640 – – FE 1.375 – – 0.0541 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – – 20/23 M68AW256M PART NUMBERING Table 13. Ordering Information Scheme Example: M68AW256 M L 55 ZB 6 T Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 256 = 4 Mbit (256K x16) Option 1 M = 1 Chip Enable; Write and Standby from UB and LB Option 2 L = L-Die N = N-Die Speed Class 55 = 55 ns 70 = 70 ns Package ND = TSOP 44 Type II ZH = TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch ZB= TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch Operative Temperature 1 = 0 to 70 °C 6 = –40 to 85 °C Shipping Blank = Standard Packing (Tray) T = Tape & Reel Packing E = Lead-Free Package, Standard Packing (Tray) F = Lead-Free Package, Tape and Reel Packing For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 21/23 M68AW256M REVISION HISTORY Table 14. Document Revision History Date Version Revision Details February 2002 -01 First Issue 13-Mar-2002 -02 Tables 4, 7 and 9 clarified Figure 14 clarified 17-Jun-2002 -03 ICCDR clarified (Table 9) ISB clarified (Table 6) 3.1 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 03 equals 3.0). Part number modified. 20-Feb-2004 4.0 TFBGA48 7x8 replaced by TFBGA48 6x7: Figure 16., TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Bottom View Package Outline and Table 11., TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Package Mechanical Data updated. ICC1 and ISB updated in Table 6., DC Characteristics. tWLWH updated in Table 8., Write Mode AC Characteristics . Minor content modifications. FEATURES SUMMARY, SUMMARY DESCRIPTION, Table 13., Ordering Information Scheme updated with Package Lead-free information. TLEAD parameter added in Table 3., Absolute Maximum Ratings. 27-Apr-2004 5.0 TFBGA48 7x8mm - 6x8 active ball array, 0.75mm pitch reintroduced. TFBGA 6x7mm -6x8mm active ball array replaced by TFBGA48 6x8mm- 6x8 active ball array, 0.75mm pitch. 09-Oct-2002 22/23 M68AW256M Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK® is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 23/23