M74HCT651 M74HCT652 HCT651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.) HCT652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE) . . . . . . . HIGH SPEED fMAX = 60 MHz (TYP.) AT VCC = 5V COMPATIBLE WITH TTL OUTPUTS VIH = 2 V (MIN.) AT VIL = 0.8V (MAX) LOW POWER DISSIPATION o ICC = 4 µA (MAX) AT TA = 25 C OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 6 mA (mIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS651/652 DESCRIPTION M74HCT651/652 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS (3-STATE), fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. Enable GAB and GBA are provided to control the transceiver functions. Select AB and Select BA control pins are provided to select whether real-time or stored data is transfered. A low input level selects real-time data, and a high selects stored data. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (CLOCK AB or CLOCK BA) regardless of the select or enable control pins. When select AB and select BA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. All inputs are equipped with protection circuits against static discharge and transient excess voltage.This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSCMOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. October 1993 B1R (Plastic Package) M1R (Micro Package) ORDER CODES : M74HCXXXM1R M74HCXXXB1R PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT GAB, GAB, CAB, SAB, SBA, CBA A, B 1/12 M74HCT651/652 LOGIC DIAGRAM (HCT651) Note : In case of 74HCT652 output inverter marked * at A bus and B bus are eliminated. TIMING CHART 2/12 M74HCT651/652 TRUTH TABLE HCT652 (The truth table for HCT651 is the same as this, but with the outputs inverted) GAB GBA CAB CBA SAB SBA X L X H X* X X* L X X* X H X Z Z X INPUTS INPUTS Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs X L OUTPUTS L INPUTS L The A bus are outputs and the B bus are inputs The data at the B bus are displayed at the A bus H H X L L H L H The data at the B bus ar displayed at the A bus. The data of the B bus are stored to the internal flip-flop on low to high transition of th clock pulse X H Qn X X H The data stored to the internal flip-flop are dispayed at the A bus The data at the B bus are stored to the internal flipflop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the A bus X* L X X* L X X The output functions of the A and B bus are disabled L L H H INPUTS OUTPUTS The A bus are inputs and the B bus are outputs L H L L H L The data at the A bus are displayed at the B bus H H The data at the A bus are displayed at the B bus. The data of the A bus are stored to the internal flipflop on low to high transition of the clock pulse X* H X X Qn The data stored to the internal flip-flops are displayed at the B bus X* H X L H L H the data at the A bus are stored to the internal flipflop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the B bus OUTPUTS OUTPUTS H FUNCTION Both the A bus and the B bus are inputs X H X B INPUTS X L X* A INPUTS X H H Qn Qn H H Qn Qn L Both the A bus and the B bus are outputs The data stored to the internal flip-flops are displayed at the A and B bus respactively The output at the A bus are displayed at the B bus, the output at the B bus are displayed at the A bus respectively X : DON’T CARE Z : HIGH IMPEDANCE Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS * : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF THE CLOCK INPUTS 3/12 M74HCT651/652 PIN DESCRIPTION PIN No 1 2 3 4, 5, 6, 7, 8, 9, 10, 11 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 12 24 SYMBOL CLOCK AB SELECT AB GAB A1 to A8 B1 to B8 GBA SELECT BA CLOCK BA GND VCC NAME AND FUNCTION A to B Clock Input (LOW to HIGH, Edge-Trigged) Select A to B Source Input Direction Control Input A data Inputs/Outputs B Data Inputs/Outputs Output Enable Input (Active LOW) Select B to A Source Input B to A Clock Input (LOW to HIGH, Edge-Triggered) Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOLS HCT651 4/12 HCT652 M74HCT651/652 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit VCC VI Supply Voltage DC Input Voltage -0.5 to +7 -0.5 to VCC + 0.5 V V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK IOK DC Input Diode Current DC Output Diode Current ± 20 ± 20 mA mA IO DC Output Source Sink Current Per Output Pin ± 35 mA DC VCC or Ground Current ± 70 mA 500 (*) mW ICC or IGND Parameter PD Power Dissipation Tstg TL Storage Temperature Lead Temperature (10 sec) -65 to +150 300 o o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage VI Input Voltage VO Top Output Voltage Operating Temperature: tr, tf Input Rise and Fall Time (VCC = 4.5 to 5.5V) Value 4.5 to 5.5 Unit V 0 to VCC V 0 to VCC -40 to +85 0 to 500 V C o ns 5/12 M74HCT651/652 DC SPECIFICATIONS Test Conditions Symbol Parameter TA = 25 oC Min. Typ. Max. 2.0 VIH High Level Input Voltage 4.5 to 5.5 V IL Low Level Input Voltage 4.5 to 5.5 V OH High Level Output Voltage VOL II -40 to 85 oC Min. Max. 2.0 0.8 4.5 VI = IO=-20 µA VIH IO=-6.0 mA or V IL 4.5 VI = IO= 20 µA VIH IO= 6.0 mA or V IL 5.5 Low Level Output Voltage Input Leakage Current (*) Value VCC (V) 4.4 4.5 4.4 4.31 4.13 0.0 0.17 V 0.8 4.18 Unit V V 0.1 0.26 0.1 0.33 V VI = VCC or GND ±0.1 ±1 µA IOZ 3 State Output Off State Current 5.5 VI = VCC or GND ±0.5 ±5.0 µA ICC ∆ICC Quiescent Supply Current Additional worst case supply current 5.5 5.5 VI = VCC or GND Per Input pin VI = 0.5V or V I = 2.4V Other Inputs at V CC or GND 1 2.0 10 2.9 µA mA (*): Applicable only to GAB, GBA, CAB, CBA, SAB, SBA input 6/12 M74HCT651/652 AC ELECTRICAL CHARACTERISTICS (Input t r = t f = 6 ns) Symbol Parameter Test Conditions VCC CL (V) (pF) Unit tTLH tTHL tPLH tPHL Output Transition Time 4.5 Propagation Delay Time (BUS - BUS) 4.5 50 20 30 38 ns tPLH tPHL Propagation Delay Time (CLOCK - BUS) tPLH tPHL Propagation Delay Time (SELECT - BUS) 4.5 4.5 4.5 4.5 150 50 150 50 25 29 34 24 38 44 52 34 48 55 65 43 ns ns ns ns tPZL tPZH 3-State Output Enable Time (GAB, GBA - BUS) tPLZ tPHZ fMAX Output Disable Time (GAB, GBA - BUS) Maximum Clock Frequency 4.5 4.5 4.5 4.5 150 50 150 50 29 22 27 24 42 33 41 35 53 41 51 44 ns ns ns ns 4.5 50 tW(H) tW(L) ts Minimum Clock Pulse Width 4.5 50 8 15 19 ns Minimum Set-up Time 4.5 50 3 10 13 ns th CIN Minimum Hold Time Input Capacitance 4.5 50 5 5 10 5 10 ns pF CI/O CPD (*) Bus Terminal Capacitance Power Dissipation Capacitance 50 Value TA = 25 C -40 to 85 oC Min. Typ. Max. Min. Max. 7 12 15 o RL = 1 KΩ RL = 1 KΩ RL = 1 KΩ for HCT651 for HCT652 31 55 13 38 39 25 ns MHz pF pF (*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC/8 (per Channel) 7/12 M74HCT651/652 SWITCHING CHARACTERISTICS TEST CIRCUIT AND WAVEFORM WAVEFORM 1 WAVEFORM 2 WAVEFORM 3 WAVEFORM 5 WAVEFORM 4 GAB = ”L” GBA = ”H” 8/12 M74HCT651/652 TEST WAVEFORM ICC (Opr.) INPUT TRANSITION TIME IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST. 9/12 M74HCT651/652 Plastic DIP24 (0.25) MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 1.27 D E 0.009 0.012 0.050 32.2 15.2 16.68 1.268 0.598 0.657 e 2.54 0.100 e3 27.94 1.100 F MAX. 14.1 0.555 I 4.445 0.175 L 3.3 0.130 P043A 10/12 M74HCT651/652 SO24 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A a1 MIN. TYP. MAX. 2.65 0.10 0.104 0.20 a2 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45° (typ.) D 15.20 15.60 0.598 0.614 E 10.00 10.65 0.393 0.420 e 1.27 0.05 e3 13.97 0.55 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 S 8° (max.) L s e3 b1 e a1 b A a2 C c1 E D 13 1 12 F 24 11/12 M74HCT651/652 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A 12/12