74LCX646 LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: tPD = 7.0 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 646 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LCX646 is a low voltage CMOS OCTAL BUS TRANSCEIVER AND REGISTER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. SOP TSSOP Table 1: Order Codes PACKAGE T&R SOP TSSOP 74LCX646RM13TR 74LCX646TTR This device consists of bus transceiver circuits with 3 state, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into register on the low to high transition of the appropriate clock pin (Clock AB or Clock BA). Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (Select AB select BA) can multiplex stored and real time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode Figure 1: Pin Connection And IEC Logic Symbols September 2004 Rev. 6 1/16 M74LCX646 AC/ACT family, combined with a lower power consumption. (enable G high), "A" data may be stored in one register and/or "B" data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. It has same speed performance at 3.3V than 5V All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description 2/16 PIN N° SYMBOL 1 CLOCK AB (CAB) 2 3 4, 5, 6, 7, 8, 9, 10, 11 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 SELECT AB (SAB) DIR A1 to A8 B1 to B8 G SELECT BA (SBA) CLOCK BA (CBA) 12 24 GND VCC NAME AND FUNCTION A to B Clock Input (LOW to HIGH, Edge-Triggered) Select A to B Source Input Direction Control Input A Data Inputs/Outputs B Data Inputs/Outputs Output Enable Input (Active LOW) Select B to A Source Input B to A Clock Input (LOW to HIGH, Edge Triggered) Ground (0V) Positive Supply Voltage M74LCX646 Table 3: Truth Table G DIR CAB CBA SAB SBA X H X X X X X* L X X* L X X* H X X* H X X X L X L X H X H X X L X H X X* X* L L X* X* X A B INPUTS Z INPUTS Z FUNCTION Both the A bus and the B bus are inputs The Output functions of the A and B bus are disabled Both the A and B bus are used as inputs to the internal INPUTS INPUTS flip-flops. Data at the bus will be stored on low to high transition of the clock inputs. INPUTS OUTPUTS The A bus are inputs and the B bus are outputs L L The data at the A bus are displayed at the B bus H H L L The data at the A bus are displayed at the B bus. The data of the A bus are stored to internal flip-flop on low H H to high transition of the clock pulse The data stored to the internal flip-flop are displayed at X Qn the B bus. L L The data at the A bus are stored to the internal flip-flop on low to high transition of the clock pulse. The states H H of the internal flip-flops output directly to the B bus. OUTPUTS INPUTS The B bus are inputs and the A bus are outputs. L L The data at the B bus are displayed at the A bus H H L L The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flop on H H low to high transition of the clock pulse. The data stored to the internal flip-flops are displayed Qn X at the A bus L L The data at the B bus are stored to the internal flip-flop on low to high transition of the clock pulse. The states H H of the internal flip-flops output directly to the A bus. X : Don’t Care Z : High Impedance Qn: The data stored to the internal flip-flops by most recent low to high transition of the clock inputs * : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs. 3/16 M74LCX646 Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays Figure 4: Timing Chart 4/16 M74LCX646 Table 4: Absolute Maximum Ratings Symbol VCC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (OFF State) -0.5 to +7.0 V VO DC Output Voltage (High or Low State) (note 1) IIK DC Input Diode Current IOK IO -0.5 to VCC + 0.5 V - 50 mA DC Output Diode Current (note 2) - 50 mA DC Output Current ± 50 mA ICC DC Supply Current per Supply Pin ± 100 mA IGND DC Ground Current per Supply Pin ± 100 mA Tstg Storage Temperature -65 to +150 °C TL Lead Temperature (10 sec) 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND Table 5: Recommended Operating Conditions Symbol VCC Parameter Supply Voltage (note 1) Value Unit 2.0 to 3.6 V 0 to 5.5 V VI Input Voltage VO Output Voltage (OFF State) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V) ± 24 mA IOH, IOL High or Low Level Output Current (VCC = 2.7V) ± 12 mA Top dt/dv Operating Temperature Input Rise and Fall Time (note 2) -55 to 125 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V 5/16 M74LCX646 Table 6: DC Specifications Test Condition Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Ioff IOZ ICC ∆ICC Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input Min. Max. 2.0 -55 to 125 °C Min. Unit Max. 2.0 V 2.7 to 3.6 0.8 0.8 2.7 to 3.6 IO=-100 µA VCC-0.2 VCC-0.2 2.7 IO=-12 mA 2.2 2.2 IO=-18 mA 2.4 2.4 IO=-24 mA 2.2 2.7 to 3.6 V V 2.2 IO=100 µA 0.2 0.2 IO=12 mA 0.4 0.4 IO=16 mA 0.4 0.4 IO=24 mA 0.55 0.55 2.7 to 3.6 VI = 0 to 5.5V ±5 ±5 µA 0 VI or VO = 5.5V 10 10 µA 2.7 to 3.6 VI = VIH or VIL VO = 0 to VCC ±5 ±5 µA 2.7 3.0 II -40 to 85 °C VCC (V) 3.0 VOL Value 2.7 to 3.6 VI = VCC or GND VI or VO= 3.6 to 5.5V VIH = VCC - 0.6V 2.7 to 3.6 10 10 ± 10 ± 10 500 500 V µA µA Table 7: Dynamic Switching Characteristics Test Condition Symbol VOLP VOLV Parameter Dynamic Low Level Quiet Output (note 1) TA = 25 °C VCC (V) 3.3 Value Min. CL = 50pF VIL = 0V, VIH = 3.3V Typ. 0.8 -0.8 Unit Max. V 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 6/16 M74LCX646 Table 8: AC Electrical Characteristics Test Condition Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZL tPZH Parameter Propagation Delay Time (CAB or CBA to An or Bn) Propagation Delay Time (An to Bn or Bn to An) Propagation Delay Time (SAB or SBA to An or Bn) Output Enable Time (G, DIR to An, Bn) tPLZ tPHZ Output Disable Time (G, DIR to An, Bn) tS Setup Time, HIGH or LOW level Data to CAB, CBA Hold Time, HIGH or LOW level Data to CAB, CBA CAB, CBA Pulse Width, HIGH or LOW Clock Pulse Frequency Output To Output Skew Time (note1, 2) th tW fMAX tOSLH tOSHL Value CL (pF) RL (Ω) ts = tr (ns) 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 3.0 to 3.6 50 500 2.5 3.0 to 3.6 50 500 2.5 VCC (V) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 -40 to 85 °C -55 to 125 °C Min. Max. Min. Max. 1.5 9.5 1.5 9.5 1.5 8.5 1.5 8.5 1.5 8.0 1.5 8.0 1.5 7.0 1.5 7.0 1.5 9.5 1.5 9.5 1.5 8.5 1.5 8.5 1.5 1.5 1.5 1.5 2.5 9.5 8.5 9.5 8.5 1.5 1.5 1.5 1.5 2.5 9.5 8.5 9.5 8.5 2.5 2.5 1.5 1.5 1.5 1.5 4.0 4.0 3.3 3.3 150 150 1.0 Unit ns ns ns ns ns ns ns ns MHz 1.0 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design Table 9: Capacitive Characteristics Test Condition Symbol Parameter Value TA = 25 °C VCC (V) Min. Typ. Unit Max. CIN Input Capacitance 3.3 VIN = 0 to VCC 6 pF CI/O I/O Capacitance 3.3 VIN = 0 to VCC 10 pF CPD Power Dissipation Capacitance (note 1) 3.3 fIN = 10MHz VIN = 0 or VCC 37 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit) 7/16 M74LCX646 Figure 5: Test Circuit TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V tPZH, tPHZ GND CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) Figure 6: Waveform - Propagation Delays, SAB, SBA, An, Bn, Times (f=1MHz; 50% duty cycle) 8/16 M74LCX646 Figure 7: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle) Figure 8: Waveform - Setup And Hold Time, CAB, CBA Maximum Frequency (f=1MHz; 50% duty cycle) 9/16 M74LCX646 Figure 9: Waveform - Pulse Width (f=1MHz; 50% duty cycle) 10/16 M74LCX646 SO-24 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 15.20 15.60 0.598 0.614 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 k 0° 8° 0° 8° ddd 0.100 0.004 0070769C 11/16 M74LCX646 TSSOP24 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.1 A1 0.05 0.15 A2 0.043 0.002 0.006 0.9 0.035 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 7.7 7.9 0.303 0.311 E 4.3 4.5 0.169 0.177 e 0.65 BSC 0.0256 BSC H 6.25 6.5 0.246 0.256 K 0° 8° 0° 8° L 0.50 0.70 0.020 0.028 A A2 A1 b K e L H c D E PIN 1 IDENTIFICATION 1 7047476B 12/16 M74LCX646 Tape & Reel SO-24 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 30.4 0.519 1.197 Ao 10.8 11.0 0.425 0.433 Bo 15.7 15.9 0.618 0.626 Ko 2.9 3.1 0.114 0.122 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 13/16 M74LCX646 Tape & Reel TSSOP24 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 14/16 TYP 0.504 22.4 0.519 0.882 Ao 6.8 7 0.268 0.276 Bo 8.2 8.4 0.323 0.331 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 M74LCX646 Table 10: Revision History Date Revision 15-Sep-2004 6 Description of Changes Ordering Codes Revision - pag. 1. 15/16 M74LCX646 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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