MAXIM MAX14611ETD

19-6276; Rev 0; 4/12
EVALUATION KIT AVAILABLE
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
General Description
The MAX14611 is a quad bidirectional logic-level translator that provides the level shifting necessary to allow data
transfer in a multivoltage system. Externally applied voltages, VCC and VL, set the logic levels on either side of
the device. A low-voltage logic signal present on the VL
side of the device appears as a high-voltage logic signal
on the VCC side of the device, and vice-versa.
The device is ideal for I2C bus as well as MDIO bus applications where open-drain operation is often required. The
device features a three-state output mode (TS). Drive TS
high to connect the pullup to the powered I/O port. This
allows for continuous, undisrupted I2C operation on the
powered side of the device while the level translation
function is off. The MAX14611 is a pin-to-pin compatible
upgrade to the MAX3378E in the TDFN package.
The MAX14611 features enhanced high-electrostaticdischarge (ESD) protection on all I/OVCC_ ports up to
±6kV HBM. The device operates over the -40NC to +85NC
extended temperature range and is available in 3mm x
3mm, 14-pin TDFN and 4.9mm x 5.1mm, 14-pin TSSOP
packages.
Applications
I2C,
SPI,
and MDIO
Level Translation
Mobile Phones
Low-Voltage ASIC
Level Translation
Telecommunications
Equipment
Benefits and Features
SImproved Interoperability
Meets I2C Specifications
10kI Internal Pullup Resistor
Pin-to-Pin Compatible with the MAX3377E and the MAX3378E

0.9V Operation on Low Voltage Supply
SRobust Logic-Level Translation
±0.5V Tolerances on All Pins
±6kV Human Body Model ESD Protection on
I/OVCC_ Lines
Thermal Short-Circuit Protection
Short to Ground Fault Protection on All Pins

-40NC to +85NC Operating Temperature Range
SIncreased Design Flexibility
Ultra-Low Supply Current
Pullup Resistor Enabled with a Single Power
Supply when TS = High
10I (max) Transmission Gate FET

Small, 14-Pin, 3.0mm x 3.0mm TDFN Package
and 14-Pin, 4.9mm x 5.1mm TSSOP Package
Ordering Information appears at end of data sheet.
POS Systems
Portable Electronics
Typical Operating Circuit
+1.8V
+3.3V
0.1µF
VL
VCC
1µF
TS
+1.8V SYSTEM
CONTROLLER
DATA
+3.3V
SYSTEM
MAX14611
I/OVL_
I/OVCC_
DATA
For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX14611.related.
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
VCC...........................................................................-0.5V to +6V
VL...........................................................................-0.5V to +5.5V
TS.............................................................................-0.5V to +6V
I/OVCC_..................................................... -0.5V to (VCC + 0.5V)
I/OVL_........................................................... -0.5V to (VL + 0.5V)
Short-Circuit Duration I/OVL_, I/OVCC_ to GND........Continuous
Continuous Current.......................................................... Q50mA
Continuous Power Dissipation (TA = +70NC)
TDFN (derate 24.4mW/NC above +70NC)................1951.2mW
TSSOP (derate 10mW/NC above +70NC) ..................796.8mW
Operating Temperature Range........................... -40NC to +85NC
Maximum Junction Temperature......................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN-EP
Junction-to-Ambient Thermal Resistance (qJA)............41°C/W
Junction-to-Case Thermal Resistance (qJC)...................8°C/W
TSSOP
Junction-to-Ambient Thermal Resistance (qJA­).......100.4°C/W
Junction-to-Case Thermal Resistance (qJC).................30°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = 0.9V to the lesser of VCC + 0.3V and 5V. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical
values are at VCC = +3.3V, VL = +1.8V, TA = +25NC, unless otherwise noted.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
VL Supply Range
VCC Supply Range
VL Supply Current
VCC Supply Current
VCC Shutdown Mode Supply
Current
VL Shutdown Mode Supply
Current
I/OVCC_, I/OVL_, TS Leakage
Current
TS Input Leakage Current
VL Shutdown Threshold
VCC Shutdown Threshold
I/OVL_ Pullup Resistor
I/OVCC_ Pullup Resistor
VL
0.9
5
V
VCC
1.65
5.5
V
IVL
I/OVCC_ = VCC, I/OVL_ = VL, TS = VL
1
FA
IVCC
I/OVCC_ = VCC, I/OVL_ = VL, TS = VL
35
FA
ISHDN_VCC
TS = GND, I/OVCC = unconnected
0.1
1
TS = VCC, VL = GND,
I/OVCC = unconnected
0.1
1
FA
TS = GND
0.1
1
ISHDN_VL
TS = VL, VCC = GND,
I/OVL_ = unconnected
0.1
1
ILEAK
TA = +25NC, TS = GND
0.1
1
FA
1
FA
VTH_VL
0.3
0.85
V
VTH_VCC
0.8
1.35
V
RVL_PU
10
kI
RVCC_PU
10
kI
ILEAK_TS
TA = +25NC
FA
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.65V to +5.5V, VL = 0.9V to the lesser of VCC + 0.3V and 5V. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical
values are at VCC = +3.3V, VL = +1.8V, TA = +25NC, unless otherwise noted.) (Notes 2, 3)
PARAMETER
I/OVL_ to I/OVCC_ DC
Resistance
I/OVL_ Input-Voltage High
SYMBOL
RIOVL_IOVCC
CONDITIONS
Inferred from VOL measurements
VIHL
VILL
I/OVCC_ Input-Voltage High
VIHC
I/OVCC_ Input-Voltage Low
VILC
I/OVL_ Output-Voltage High
VOHL
I/OVL_ source current = 10FA
I/OVL_ Output-Voltage Low
VOLL
I/OVL_ sink current = 2mA,
VI/OVCC_ P 50mV
I/OVCC_ Output-Voltage High
VOHC
I/OVCC_ source current = 10FA
I/OVCC_ Output Voltage Low
VOLC
I/OVCC_ sink current = 2mA,
VI/OVL_ P 150mV
VIH
TS Input-Voltage Low Threshold
VIL
TYP
MAX
UNITS
5
10
I
VL - 0.2
I/OVL_ Input-Voltage Low
TS Input-Voltage High Threshold
MIN
V
0.15
VCC - 0.4
V
V
0.2
0.7 x VL
V
V
0.4
0.7 x VCC
V
V
0.4
VL - 0.2
V
V
VL > 1.3V
Accelerator Pulse Duration
Inferred from timing measurements
VL Output Accelerator Source
Impedance
VL = 0.9V
70
VL = 3.3V
15
VCC Output Accelerator Source
Impedance
VCC = 1.65V
50
VCC = 5.0V
10
Thermal-Shutdown Threshold
20NC hysteresis
0.2
V
30
ns
I
I
+150
NC
ESD PROTECTION
I/OVCC_
Human Body Model, CVCC = 1FF,
CVL = 0.1FF
Q6
kV
All Other Pins
Human Body Model
Q2
kV
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
TIMING CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = +0.9V to the lesser of VCC + 0.3V and 5V, TS = VL, RL = 1Mω, CVCC = 1µF, CVL = 0.1µF, CI/OVCC_ = 15pF,
CI/OVL_ = 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are VCC = +3.3V, VL = +1.8V, and TA = +25NC.) (Note 4)
PARAMETER
SYMBOL
Push-pull driving (Figure 1)
40
Open-drain driving (Figure 2, Note 5)
50
Push-pull driving (Figure 3)
30
Open-drain driving (Figure 4, Note 5)
105
Push-pull driving (Figure 3)
30
Open-drain driving (Figure 4, Note 5)
30
I/OVL-VCC
Push-pull driving (Figure 1)
40
I/OVL-VCC
Open-drain driving (Figure 2, Note 5)
150
I/OVCC-VL
Push-pull driving (Figure 3)
30
I/OVCC-VL
Open-drain driving (Figure 4, Note 5)
105
Input rise time/fall time < 6ns, push-pull
driving
20
Input rise time/fall time < 6ns, open-drain
driving
50
Push-pull operation
20
Open-drain operation (Notes 5, 6)
6
tFVCC
I/OVL_ Rise Time
tRVL
I/OVL_ Fall Time
tFVL
Maximum Data Rate
MAX
100
I/OVCC_ Fall Time
Channel-to-Channel Skew
TYP
Open-drain driving (Figure 2, Note 5)
tRVCC
Propagation Delay
MIN
40
I/OVCC_ Rise Time
Propagation Delay
CONDITIONS
Push-pull driving (Figure 1)
tSKEW
UNITS
ns
ns
ns
ns
ns
ns
ns
Mbps
Note 2: All units are 100% production tested at TA = +25°C. Specifications over operating temperature range are guaranteed by
design.
Note 3:VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and
shutdown conditions.
Note 4: All timing is 10% to 90% for rise time and 90% to 10% for fall time.
Note 5: Not production tested; guaranteed by design.
Note 6: Requires the external pullup resistor.
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
tRVCC
VL
tFVCC
VCC
90%
VL
RS
50I
90%
VCC
TS
MAX14611
I/OVL_
50%
50%
I/OVCC_
GND
CI/OVCC_
RL
50%
50%
10%
10%
tPDLH
tPDHL
Figure 1. Push-Pull Driving I/OVL_
VL
VCC
tRVCC
VL
1kI
tFVCC
VCC
90%
1kI
TS
90%
MAX14611
I/OVL_
I/OVCC_
GND
50%
CI/OVCC_
50%
RL
50%
50%
10%
10%
tPDLH
tPDHL
Figure 2. Open-Drain Driving I/OVL_
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
tRVL
VL
VCC
VL
VCC
TS
RS
50I
MAX14611
I/OVL_
RL
50%
50%
I/OVCC_
90%
90%
GND
CI/OVL_
tFVL
50%
50%
10%
10%
tPDLH
tPDHL
Figure 3. Push-Pull Driving I/OVCC_
1kI
VL
VCC
VL
VCC
1kI
TS
MAX14611
I/OVL_
RL
tFVL
tRVL
50%
90%
I/OVCC_
50%
GND
CI/OVL_
50%
90%
50%
10%
10%
tPDLH
tPDHL
Figure 4. Open-Drain Driving I/OVCC_
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Typical Operating Characteristics
(VCC = +3.3V, VL = 1.8V, RL = 1Mω, CL = 15pF, TA = +25°C, data rate = 500kbps in open-drain operation and 8Mbps in push-pull
operation, unless otherwise noted.)
VCC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
50
600
400
500kbps,
OPEN-DRAIN
150
125
100
75
0
25
0
1.65 2.20 2.75 3.30 3.85 4.40 4.95 5.50
VCC (V)
300
250
200
150
500kbps,
OPEN-DRAIN
100
-15
10
35
60
85
TEMPERATURE (°C)
200
DRIVING I/OVL_
180
160
8Mbps,
PUSH-PULL
140
120
100
80
500kbps,
OPEN-DRAIN
60
40
50
20
0
0
1000
-15
10
35
60
35
40
45
VCC SUPPLY CURRENT
vs. CAPACITIVE LOAD
RISE/ FALL TIME
vs. CAPACITIVE LOAD
600
500kbps,
OPEN-DRAIN
100
8Mbps,
PUSH-PULL
300
80
50
70
60
50
40
tLH
30
200
20
100
10
0
DRIVING I /OVL_
500kbps, OPEN-DRAIN
90
RISE/FALL TIME (ns)
700
400
30
CAPACITIVE LOAD (pF)
800
500
25
TEMPERATURE (°C)
DRIVING I/OVL_
900
85
MAX14611 toc06
-40
MAX14611 toc07
SUPPLY CURRENT (µA)
8Mbps,
PUSH-PULL
-40
VL SUPPLY CURRENT
vs. CAPACITIVE LOAD
SUPPLY CURRENT (µA)
DRIVING I/OVCC_
350
0
1.65 2.20 2.75 3.30 3.85 4.40 4.95 5.50
VCC (V)
VCC SUPPLY CURRENT
vs. TEMPERATURE
400
500kbps,
OPEN-DRAIN
50
200
25
8Mbps,
PUSH-PULL
MAX14611 toc05
75
8Mbps,
PUSH-PULL
DRIVING I/OVCC_
175
SUPPLY CURRENT (µA)
100
800
MAX14611 toc04
125
500kbps,
OPEN-DRAIN
8Mbps,
PUSH-PULL
200
MAX14611 toc02
150
DRIVING I/OVL_
VL = 1.8V
1000
SUPPLY CURRENT (µA)
DRIVING I/OVL_
VL = 1.8V
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
175
1200
MAX14611 toc01
200
VL SUPPLY CURRENT
vs. TEMPERATURE
MAX14611 toc03
VL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
tHL
0
25
30
35
40
CAPACITIVE LOAD (pF)
45
50
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = 1.8V, RL = 1Mω, CL = 15pF, TA = +25°C, data rate = 500kbps in open-drain operation and 8Mbps in push-pull
operation, unless otherwise noted.)
tLH
10
8
6
4
tHI
2
5
tPHL
4
3
2
tPLH
4
2
35
40
45
30
35
40
45
50
10
75
tHL
DRIVING I/OVCC_
8Mbps, PUSH-PULL
9
8
RISE/FALL TIME (ns)
RISE/FALL TIME (ns)
100
25
35
40
45
50
RISE/ FALL TIME
vs. CAPACITIVE LOAD
MAX14611 toc11
DRIVING I/OVCC_
500kbps, OPEN-DRAIN
50
30
CAPACITIVE LOAD (pF)
RISE/FALL TIME
vs. CAPACITIVE LOAD
125
25
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
150
MAX14611 toc10
0
25
50
7
6
tHL
5
4
3
2
tLH
1
0
tLH
0
30
35
40
45
25
30
35
40
45
CAPACITIVE LOAD (pF)
PROPAGATION DELAY
vs. CAPACITIVE LOAD
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX14611 toc13
6
DRIVING I/OVCC_
500kbps, OPEN-DRAIN
5
50
CAPACITIVE LOAD (pF)
4
3
tPHL
2
tPLH
1
4.0
DRIVING I/OVCC_
8Mbps, PUSH-PULL
3.5
PROPAGATION DELAY (ns)
25
50
MAX14611 toc14
30
tPLH
1
0
25
tPHL
3
1
0
DRIVING I /OVL_
8Mbps, PUSH-PULL
5
MAX14611 toc12
12
6
6
PROPAGATION DELAY (ns)
14
PROPAGATION DELAY (ns)
RISE/FALL TIME (ns)
16
PROPAGATION DELAY
vs. CAPACITIVE LOAD
DRIVING I /OVL_
500kbps, OPEN-DRAIN
7
PROPAGATION DELAY (ns)
DRIVING I /OVL_
8Mbps, PUSH-PULL
18
8
MAX14611 toc08
20
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX14611 toc09
RISE/ FALL TIME
vs. CAPACITIVE LOAD
3.0
tPHL
2.5
2.0
1.5
tPLH
1.0
0.5
0
0
25
30
35
40
CAPACITIVE LOAD (pF)
45
50
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = 1.8V, RL = 1Mω, CL = 15pF, TA = +25°C, data rate = 500kbps in open-drain operation and 8Mbps in push-pull
operation, unless otherwise noted.)
RISE/FALL TIME (ns)
40
35
tLH
30
25
20
15
tHL
10
20
MAX14611 toc16
DRIVING I/OVCC_
4Mbps, OPEN-DRAIN
1kI EXTERNAL PULLUP
45
PROPAGATION DELAY (ns)
50
PROPAGATION DELAY
vs. CAPACITIVE LOAD
MAX14611 toc15
RISE/ FALL TIME
vs. CAPACITIVE LOAD
DRIVING I/OVL_
4Mbps, OPEN-DRAIN
1kI EXTERNAL PULLUP
16
12
tPLH
8
4
5
0
35
40
45
50
35
40
45
RISE/FALL TIME
vs. CAPACITIVE LOAD
PROPAGATION DELAY
vs. CAPACITIVE LOAD
35
30
6
tLH
25
20
15
tHL
10
DRIVING I/OVCC_
4Mbps, OPEN-DRAIN
1kI EXTERNAL PULLUP
4
SUPPLY CURRENT (µA)
40
30
CAPACITIVE LOAD (pF)
DRIVING I/OVL_
4Mbps, OPEN-DRAIN
1kI EXTERNAL PULLUP
45
25
CAPACITIVE LOAD (pF)
2
0
tPHL
-2
tPLH
-4
-6
5
0
50
MAX14611 toc18
50
30
MAX14611 toc17
25
RISE/FALL TIME (ns)
tPHL
0
50% I/O VCC_ TO 50% I/OVL_ (SEE TOC19)
-8
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
30
35
40
45
50
CAPACITIVE LOAD (pF)
LOW-TO-HIGH TRANSITION,
OPEN-DRAIN ZOOM
MAX14611 toc19
4ns/div
25
ENTERING AND EXITING THREE-STATE MODE
(DRIVING I/OVCC_, CLOAD = 50pF)
MAX14611 toc20
10ms/div
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Pin Configurations
TOP VIEW
I/OVL1
1
I/OVL2
2
TS
14 VCC
+
VL
1
13 I/OVCC1
I/OVL1
2
3
12 I/OVCC2
I/OVL2
3
N.C.
4
11 N.C.
I/OVL3
4
I/OVL3
5
10 VL
I/OVL4
5
I/OVL4
6
I/OVCC3
N.C.
I/OVCC4
GND
GND
MAX14611
*EP
7
9
8
+
14
VCC
13
I/OVCC1
12
I/OVCC2
11
I/OVCC3
10
I/OVCC4
6
9
N.C.
7
8
TS
TDFN
MAX14611
TSSOP
*CONNECT EXPOSED PAD TO GND.
Pin Description
PIN
NAME
FUNCTION
TDFN-EP
TSSOP
1
2
I/OVL1
Input/Output 1. Reference to VL.
2
3
I/OVL2
Input/Output 2. Reference to VL.
3
8
TS
4, 11
6,9
N.C.
5
4
I/OVL3
Input/Output 3. Reference to VL.
6
5
I/OVL4
Input/Output 4. Reference to VL.
7
7
GND
8
10
I/OVCC4 Input/Output 4. Reference to VCC.
9
11
I/OVCC3 Input/Output 3. Reference to VCC.
10
1
12
12
I/OVCC2 Input/Output 2. Reference to VCC.
13
13
I/OVCC1 Input/Output 1. Reference to VCC.
14
14
VCC
—
—
EP
VL
Three-State Select Input. Drive TS low to place the device in three-state output mode. I/OVCC_
and I/OVL_ are high impedance in three-state output mode.
Note: Logic referenced to VL (for logic thresholds, see the Electrical Characteristics table).
No Connection. Not internally connected.
Ground
Logic Supply Voltage Input, 0.9V P VL P min (5.0V, (VCC + 0.3V)). Connect a 0.1FF ceramic
capacitor as close as possible to the pin.
Power Supply Input. The supply range is 1.65V P VCC P 5.5V. Bypass VCC with a 1FF ceramic
capacitor as close as possible to the pin to achieve higher ESD protection (Q6kV HBM).
Exposed Pad (TDFN Only). EP is internally connected to GND. Connect to a large ground
plane to maximize thermal performance. Not intended as an electrical connection point.
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Functional Diagram
VL
TS
VCC
MAX14611
PU1
ONE-SHOT
BLOCK
ONE-SHOT
BLOCK
PU2
EN CONTROL
BLOCK
GATE
DRIVE
I/OVCC_
I/OVL_
N
Detailed Description
The MAX14611 ESD-protected level translator provides
the level shifting necessary to allow data transfer in a
multivoltage system. Externally applied voltages, VCC
and VL, set the logic levels on either side of the device.
A low-voltage logic signal present on the VL side of the
device appears as a high-voltage logic signal on the VCC
side of the device, and vice-versa.
The MAX14611 bidirectional level translator utilizes a transmission-gate based design (see the
Functional Diagram) to allow data translation in either
direction (VL ↔ VCC) on any single data line. The device
accepts VL from +0.9V to +5.0V and VCC from +1.65V
to +5.5V, making it ideal for data transfer between lowvoltage ASICs/PLDs and higher voltage systems.
The device features a three-state output mode, thermal
short-circuit protection, and Q6kV ESD protection on the
VCC side for greater protection in applications that route
signals externally.
Level Translation
For proper operation, ensure that +1.65V P VCC P +5.5V,
0.9V P VL P 5.0V, and VL P (VCC + 0.3V). It is permissible
for VL to exceed (VCC + 0.3V) during power-up sequencing. During power-supply sequencing, when VCC is
disconnected and VL is powered up, a current can be
sourced without a latchup or any damage to the device.
The maximum data rate of the MAX14611 depends
heavily on load capacitance (see the Typical Operating
Characteristics), output impedance of the driver, and
the operational voltage (see the Timing Characteristics
table).
Speed-Up Circuitry
The device features a one-shot generator that decreases
the rise time of the output. When triggered following a rising edge, MOSFETs PU1 and PU2 turn on for a short time
to pull up I/OVL_ and I/OVCC_ to their respective supplies (see the Functional Diagram). This greatly reduces
the rise time and propagation delay for the low-to-high
transition.
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Rise-Time Accelerators (Figure 5)
The device has internal rise-time accelerators, allowing
operation up to 20Mbps. The rise-time accelerators are
present on both sides of the device and act to speed
up the rise time of the input and output of the device,
regardless of the direction of the data. The triggering
mechanism for these accelerators is both level and edge
sensitive. To prevent false triggering of the rise-time
accelerators and to take full advantage of them, signal
rise/fall times of less than 2ns/V are recommended for
both sides of the device in open-drain driving. The recommendation applies only for fail time. Under less noisy
conditions, longer signal fall times can be acceptable.
Three-State Output Mode (TS)
Drive TS low to place the device in three-state output
mode. Connect TS to VL (logic-high) for normal operation. Activating the three-state output mode disconnects
the internal 10kI pullup resistors on the I/OVCC_ and
I/OVL_ lines. This forces the I/O lines to a high-impedance
state and decreases the supply current to less than 1FA.
The high-impedance I/O lines in three-state output mode
allow for use in a multidrop network. When in three-state
output mode, keep the I/OVL_ voltage below (VL + 0.3V),
and keep the I/OVCC_ voltage below (VCC + 0.3V).
Thermal Short-Circuit Protection
Thermal-overload detection protects the device from
short-circuit fault conditions. In the event of a short-circuit
fault and when the junction temperature (TJ) reaches
+150NC (typ), a thermal sensor signals the three-state
output mode logic to force the device into three-state output mode. When TJ has cooled to +130NC (typ), normal
operation resumes.
High ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/OVCC_ lines have extra protection against static
electricity. Maxim’s engineers have developed state-ofthe-art structures to protect these pins against ESD of
±6kV without damage.
The ESD structures withstand high ESD in all states:
normal operation, three-state output mode, and powered
down. After an ESD event, the device keeps working
without latchup, whereas competing products can latch
and must be powered down to remove latchup. ESD protection can be tested in various ways. The I/OVCC_ lines
of this product family are characterized for protection.to
±6kV using the Human Body Model.
ESD Test Conditions
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Applications Information
Power-Supply Decoupling
Bypass VL to ground with a 0.1FF capacitor to reduce
ripple and ensure correct data transmission. See the
Typical Operating Circuit. To ensure full Q6kV ESD
protection, bypass VCC to ground with a 1FF capacitor.
Place all capacitors as close as possible to the powersupply pins (VCC a
­ nd V­L).
Push-Pull vs. Open-Drain Driving
The device can be driven in a push-pull configuration.
The device includes internal 10kI resistors that pull
up I/OVL_ and I/OVCC_ to their respective power supplies, allowing operation of the I/O lines with open-drain
devices. See the Timing Characteristics table for maximum data rates when using open-drain drivers (Figure 1,
Figure 2, Figure 3, Figure 4).
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
VL = +1.8V
VCC = +3.3V
0.1µF
VL
+1.8V SYSTEM
CONTROLLER EN
I/OVL2
VL
SDA
VCC
I/OVL1
VL
SCL
+3.3V
SYSTEM
VCC
TS
VL
SDA
GND
1µF
I/OVCC1
MAX14611
I/OVCC2
SCL
VCC
I/OVCC3
I/OVL3
VL
VCC
I/OVL4
VCC
I/OVCC4
GND
SDA
SCL
SDA
SCL
GND
Figure 5. Open-Drain Operation
Applications Circuit
+1.8V
+3.3V
0.1µF
1µF
VL
VCC
TS
+1.8V SYSTEM
CONTROLLER
DATA
MAX14611
I/OVL1
I/OVCC1
I/OVL2
I/OVCC2
I/OVL3
I/OVCC3
I/OVL4
I/OVCC4
+3.3V
SYSTEM
DATA
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MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Package Information
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX14611ETD+
-40NC to +85NC
14 TDFN-EP*
MAX14611EUD+**
-40NC to +85NC
14 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
Chip Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
14 TDFN-EP
T1433+2
21-0137
90-0063
14 TSSOP
U14+1
21-0066
90-0113
PROCESS: BiCMOS
���������������������������������������������������������������� Maxim Integrated Products 14
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Revision History
REVISION
NUMBER
REVISION
DATE
0
4/12
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011
Maxim Integrated Products 15
Maxim is a registered trademark of Maxim Integrated Products, Inc.