19-0363; Rev 2; 3/11 KIT ATION EVALU E L B AVAILA 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA The MAX2831/MAX2832 direct conversion, zero-IF, RF transceivers are designed specifically for 2.4GHz to 2.5GHz 802.11g/b WLAN applications. The MAX2831 completely integrates all circuitry required to implement the RF transceiver function, providing an RF power amplifier (PA), RF-to-baseband receive path, basebandto-RF transmit path, VCO, frequency synthesizer, crystal oscillator, and baseband/control interface. The MAX2832 integrates the same functional blocks except for the PA. Both devices include a fast-settling sigma-delta RF synthesizer with smaller than 20Hz frequency steps and a digitally tuned crystal oscillator allowing use of a low-cost crystal. The devices also integrate on-chip DC-offset cancellation and I/Q errors and carrier leakage-detection circuits. Only an RF bandpass filter (BPF), crystal, RF switch, and a small number of passive components are needed to form a complete 802.11g/b WLAN RF frontend solution. The MAX2831/MAX2832 completely eliminate the need for an external SAW filter by implementing on-chip monolithic filters for both the receiver and transmitter. The baseband filters are optimized to meet the IEEE 802.11g standard and proprietary turbo modes up to 40MHz channel bandwidth. These devices are suitable for the full range of 802.11g OFDM data rates (6Mbps to 54Mbps) and 802.11b QPSK and CCK data rates (1Mbps to 11Mbps). The ICs are available in a small, 48-pin TQFN package measuring only 7mm x 7mm x 0.8mm. Applications Features ♦ 2.4GHz to 2.5GHz ISM Band Operation ♦ IEEE 802.11g/b Compatible (54Mbps OFDM and 11Mbps CCK) ♦ Complete RF Transceiver, PA, and Crystal Oscillator (MAX2831) Best-in-Class Transceiver Performance 62mA Receiver Current 2.6dB Rx Noise Figure -76dBm Rx Sensitivity (54Mbps OFDM) No I/Q Calibration Required 0.1dB/0.35° Rx I/Q Gain/Phase Imbalance 33dB RF and 62dB Baseband Gain Control Range 60dB Range Analog RSSI per RF Gain Setting Fast Rx I/Q DC-Offset Settling Programmable Baseband Lowpass Filter 20-Bit Sigma-Delta Fractional-N PLL with < 20Hz Step Size Digitally Tuned Crystal Oscillator +18.5dBm Transmit Power (5.6% EVM with 54Mbps OFDM) 31dB Tx Gain Control Range Integrated Power Detector (MAX2831) Serial or Parallel Gain-Control Interface > 40dB Tx Sideband Suppression without Calibration Tx/Rx I/Q Error Detection ♦ Transceiver Operates from +2.7V to +3.6V Wi-Fi, PDA, VOIP, and Cellular Handsets ♦ PA Operates from +2.7V to +4.2V (MAX2831) Wireless Speakers and Headphones ♦ Low-Power Shutdown Mode General 2.4GHz ISM Radios ♦ Small 48-Pin TQFN Package (7mm x 7mm x 0.8mm) Ordering Information TEMP RANGE PIN-PACKAGE MAX2831ETM+T PART -40°C to +85°C 48 TQFN-EP* MAX2832ETM+T -40°C to +85°C 48 TQFN-EP* *EP = Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX2831/MAX2832 General Description MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA ABSOLUTE MAXIMUM RATINGS VCCTXPA, VCCPA and TXRF_ to GND ....................-0.3V to +4.5V VCCLNA, VCCTXMX, VCCPLL, VCCCP, VCCXTAL, VCCVCO, VCCRXVGA, VCCRXFL, and VCCRXMX_ to GND....-0.3V to +3.9V B6, B7, B3, B2, SHDN, B5, CS, SCLK, DIN, B1, TUNE, B4, TXBBI_, TXBBQ_, RXHP, RXTX, RXBBI_, RXBBQ_, RSSI, BYPASS, CPOUT, LD, CLOCKOUT, XTAL, CTUNE, RXRF_ to GND .......................................-0.3V to (Operating VCC + 0.3V) RXBBI_, RXBBQ_, RSSI, BYPASS, CPOUT, LD, CLOCKOUT Short-Circuit Duration ..........................................................10s RF Input Power ...............................................................+10dBm Continuous Power Dissipation (TA = +70°C) 48-Pin TQFN (derates 27.8mW/°C above +70°C) ..........2.22W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE DC ELECTRICAL CHARACTERISTICS (MAX2831 EV kit: VCC_ = 2.7V to 3.6V, VCCPA = VCCTXPA = 2.7V to 4.2V, TA = -40°C to +85°C, Rx set to the maximum gain. CS = high, RXHP = SCLK = DIN = low, RSSI and clock output buffer are off, no signal at RF inputs, all RF inputs and outputs terminated into 50Ω, receiver baseband outputs are open. 100mVRMS differential I and Q signals (54Mbps IEEE 802.11g OFDM) applied to I/Q baseband inputs of transmitter in transmit mode, fREF = 40MHz, and registers set to recommended settings and corresponding test mode, unless otherwise noted. Typical values are at VCC = 2.8V, VCCPA = 3.3V, and TA = +25°C, LO frequency = 2.437GHz, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETERS Supply Voltage CONDITIONS Rx I/Q Output Common-Mode Voltage Variation VCCPA, VCCTXPA 2.7 4.2 Rx mode TA = +25°C 20 TA = +25°C 28 TA = -40°C to +85°C TA = +25°C MAX2831, transmit section 82 104 258 82 MAX2831, PA, POUT = +18.2dBm 209 86 Rx calibration mode TA = +25°C 101 Tx calibration mode TA = +25°C 78 0.98 1.2 TA = -40°C (relative to TA = +25°C) -17 TA = +85°C (relative to TA = +25°C) 15 Tx Baseband Input Bias Current Source current 35 78 MAX2832 DC-coupled V µA 62 TA = -40°C to +85°C TA = +25°C at default common-mode setting UNITS 35 Tx mode, TA = +25°C, VCC = 2.8V, VCCPA = 3.3V, (Note 2) Tx Baseband Input CommonMode Voltage Operating Range 2 MAX 3.6 Standby mode Rx I/Q Output Common-Mode Voltage TYP 2.7 Shutdown mode, B7: B1 = 0000000, reference oscillator not applied Supply Current MIN VCC_ 0.9 _______________________________________________________________________________________ 1.33 mA V mV 1.3 V 22 µA 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA (MAX2831 EV kit: VCC_ = 2.7V to 3.6V, VCCPA = VCCTXPA = 2.7V to 4.2V, TA = -40°C to +85°C, Rx set to the maximum gain. CS = high, RXHP = SCLK = DIN = low, RSSI and clock output buffer are off, no signal at RF inputs, all RF inputs and outputs terminated into 50Ω, receiver baseband outputs are open. 100mVRMS differential I and Q signals (54Mbps IEEE 802.11g OFDM) applied to I/Q baseband inputs of transmitter in transmit mode, fREF = 40MHz, and registers set to recommended settings and corresponding test mode, unless otherwise noted. Typical values are at VCC = 2.8V, VCCPA = 3.3V, and TA = +25°C, LO frequency = 2.437GHz, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETERS CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS: SHDN, RXTX, SCLK, DIN, CS, B7:B1, RXHP VCC 0.4 Digital Input-Voltage High, VIH V Digital Input-Voltage Low, VIL 0.4 V Digital Input-Current High, IIH -1 +1 µA Digital Input-Current Low, IIL -1 +1 µA LOGIC OUTPUTS: LD, CLOCKOUT Digital Output-Voltage High, VOH Sourcing 100µA Digital Output-Voltage Low, VOL Sinking 100µA VCC 0.4 V 0.4 V AC ELECTRICAL CHARACTERISTICS—Rx Mode (MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25°C, fRF = 2.439GHz, fLO = 2.437GHz; receiver baseband I/Q outputs at 112 mVRMS (-19dBV), fREF = 40MHz, SHDN = CS = high, RXTX = SCLK = DIN = low, with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted. Unmodulated single-tone RF input signal is used with specifications which normally apply over the entire operating conditions, unless otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 2.5 GHz RECEIVER SECTION: LNA RF INPUT-TO-BASEBAND I/Q OUTPUTS RF Input Frequency Range RF Input Return Loss 2.4 High RF gain 18 Mid RF gain 11 Low RF gain Maximum gain, B7:B1 = 1111111 Total Voltage Gain Minimum gain, B7:B1 = 0000000 14 TA = +25°C 86 TA = -40°C to +85°C 83 TA = +25°C 98 dB 3 From high-gain mode (B7:B6 = 11) to medium-gain mode (B7:B6 = 10) -16 From high-gain mode (B7:B6 = 11) to low-gain mode (B7:B6 = 0X) -33 Gain change from high gain to medium gain, high gain to low, or medium gain to low gain; gain settling to within ±2dB of steady state; RXHP = 1 0.2 8 dB RF Gain Steps (Note 3) RF Gain-Change Settling Time dB µs _______________________________________________________________________________________ 3 MAX2831/MAX2832 DC ELECTRICAL CHARACTERISTICS (continued) MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS—Rx Mode (continued) (MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25°C, fRF = 2.439GHz, fLO = 2.437GHz; receiver baseband I/Q outputs at 112 mVRMS (-19dBV), fREF = 40MHz, SHDN = CS = high, RXTX = SCLK = DIN = low, with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted. Unmodulated single-tone RF input signal is used with specifications which normally apply over the entire operating conditions, unless otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER Baseband Gain Range DSB Noise Figure CONDITIONS From maximum baseband gain (B5:B1 = 11111) to minimum baseband gain (B5:B1 = 00000) In-Band Output P-1dB Out-of-Band Input IP3 (Note 4) TYP MAX UNITS 55 62 67 dB Voltage gain = maximum with B7:B6 = 11 2.6 Voltage gain = 50dB with B7:B6 = 11 3.2 Voltage gain = 45dB with B7:B6 = 10 16 Voltage gain = 15dB with B7:B6 = 0X In-Band Compression Point Based on EVM MIN -19dBVRMS baseband output EVM degrades to 9% dB 34 B7:B6 = 11 -41 B7:B6 = 10 -24 B7:B6 = 0X -6 Voltage gain = 90dB, with B7:B6 = 11 2.5 B7:B6 = 11 -12 B7:B6 = 10 -4 B7:B6 = 0X 24 dBm VP-P dBm I/Q Phase Error 1σ variation (without calibration) ±0.35 Degrees I/Q Gain Imbalance 1σ variation (without calibration) ±0.1 dB RX I/Q Output Load Impedance (R || C) Minimum differential resistance 10 kΩ Maximum differential capacitance 10 pF Tx-to-Rx Conversion Gain for Rx I/Q Calibration For receiver gain, B7:B1 = 1101111 (Note 5) 0.5 dB Baseband VGA Settling Time Gain change from B5:B1 = 10111 to B5:B1 = 00111; gain settling to within ±2dB of steady state 0.1 µs I/Q Output DC Step when RXHP Transitions from 1 to 0 in Presence of 802.11g Short Sequence After switching RXHP to logic 0 from initial logic 1, during ideal short sequence data at -55dBm input in AWGN channel, for -19dBV output; normalized to RMS signal on I and Q outputs; transition point varied from 0 to 0.8µs in steps of 0.1µs -5 dBc I/Q Output DC Droop After switching RXHP to 0, D13:D12, Register 7 (A3:A0 = 0111) ±1 V/s I/Q Static DC Offset RXHP = 1, B7:B1 = 1101110, 1σ variation ±1 mV Spurious Signal Emissions from LNA input RF = 1GHz to 26.5GHz -51 dBm RECEIVER BASEBAND FILTERS Gain Ripple in Passband 10kHz to 8.5MHz at baseband ±1.3 DBP-P Group-Delay Ripple in Passband 10kHz to 8.5MHz at baseband ±45 nsP-P 4 _______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA (MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25°C, fRF = 2.439GHz, fLO = 2.437GHz; receiver baseband I/Q outputs at 112 mVRMS (-19dBV), fREF = 40MHz, SHDN = CS = high, RXTX = SCLK = DIN = low, with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted. Unmodulated single-tone RF input signal is used with specifications which normally apply over the entire operating conditions, unless otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS At 8.5MHz 3.2 At 15MHz 27 At 20MHz 50 At > 40MHz 80 RSSI Minimum Output Voltage RLOAD ≥ 10kΩ || 5pF 0.4 RSSI Maximum Output Voltage RLOAD ≥ 10kΩ || 5pF 2.4 V 30 mV/dB Baseband Filter Rejection (Nominal Mode) dB RSSI RSSI Slope RSSI Output Settling Time To within 3dB of steady state +32dB signal step 200 -32dB signal step 600 V ns _______________________________________________________________________________________ 5 MAX2831/MAX2832 AC ELECTRICAL CHARACTERISTICS—Rx Mode (continued) MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS—Tx Mode (MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fRF = 2.439GHz , fLO = 2.437GHz. fREF = 40MHz, SHDN = RXTX = CS = high, and SCLK = DIN = low, with power matching for the differential RF pins using the typical applications circuit. 100mVRMS sine and cosine signal (or 100mVRMS 54Mbps IEEE 802.11g I/Q signals wherever OFDM is mentioned) applied to baseband I/Q inputs of transmitter (differential DC-coupled). Registers set to recommend settings and corresponding test mode, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 2.5 GHz TRANSMIT SECTION: Tx BASEBAND I/Q INPUTS TO RF OUTPUTS RF Output Frequency Range 2.4 54Mbps 802.11g OFDM signal Output power adjusted to meet 5.6% EVM, and spectral mask 18.5 B6:B1 = 000000 -7.5 MAX2831 802.11b signal, 141mVRMS, IEEE802.11b I/Q signals Output Power MAX2832 dBm Output power adjusted to meet spectral mask 21 -3dB VGA back off -5.3 B6:B1 = 000000 -31.5 Unwanted Sideband Suppression Without I/Q calibration, B6:B1 = 100001 -42 dBc Carrier Leakage at Center Frequency of Channel Without DC offset correction -30 dBc Transmitter Spurious Signal Emissions (MAX2831) Transmitter Spurious Signal Emissions (MAX2832) 6 B6:B1 = 111000, OFDM signal B6:B1 = 111111, OFDM signal 1/3 x fLO -67 < 1GHz -36 > 1GHz -47 2/3 x fLO -64 4/3 x fLO -42 5/3 x fLO -65 8/3 x fLO -51 2 x fLO -33 3 x fLO -54 1/3 x fLO -78 < 1GHz -65 > 1GHz -72 2/3 x fLO -78 4/3 x fLO -46 5/3 x fLO -72 8/3 x fLO -46 2 x fLO -60 3 x fLO -75 _______________________________________________________________________________________ dBm/ MHz dBm/ MHz 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA (MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fRF = 2.439GHz , fLO = 2.437GHz. fREF = 40MHz, SHDN = RXTX = CS = high, and SCLK = DIN = low, with power matching for the differential RF pins using the typical applications circuit. 100mVRMS sine and cosine signal (or 100mVRMS 54Mbps IEEE 802.11g I/Q signals wherever OFDM is mentioned) applied to baseband I/Q inputs of transmitter (differential DC-coupled). Registers set to recommend settings and corresponding test mode, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER RF Output Return Loss CONDITIONS Off-chip balun + match, singleended MIN TYP MAX2831 -20 MAX2832 -10 MAX UNITS dB Tx I/Q Input Load Impedance (R || C) Minimum differential resistance 20 kΩ Maximum differential capacitance 0.7 pF Baseband -3dB Corner Frequency D1:D0 = 01, Register 8 (A3:A0 = 1000) 11 MHz Baseband Filter Rejection At 30MHz, in nominal mode 62 dB Minimum Power Detector Output Voltage Short sequence transmitter power = +9dBm 0.3 V Maximum Power Detector Output Voltage Short sequence transmitter power = +19dBm 1.2 V 0.3 µs Nominal mode RF Power Detector Response Time TRANSMITTER LO LEAKAGE AND I/Q CALIBRATION USING LO LEAKAGE AND SIDEBAND DETECTOR (see the Tx/Rx Calibration Mode section) Tx BASEBAND I/Q INPUTS TO RECEIVER OUTPUTS LO Leakage and Sideband Detector Output Amplifier Gain Range Lower -3dB Corner Frequency Calibration register, D12:D11 = 00, A3:A0 = 0110 Output at 1 x fTONE (for LO leakage = -29dBc), fTONE = 2MHz, 100mVRMS -34 Output at 2 x fTONE (for LO leakage = -240dBc), fTONE = 2MHz, 100mVRMS -44 D12:D11 = 00 to D12:D11 = 11, A3:A0 = 0110 dBVRMS 30 dB 1 MHz _______________________________________________________________________________________ 7 MAX2831/MAX2832 AC ELECTRICAL CHARACTERISTICS—Tx Mode (continued) MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS—Frequency Synthesis (MAX2831 EV kit: VCC_ = 2.7V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, PLL loop bandwidth = 150kHz, and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 2.5 GHz FREQUENCY SYNTHESIZER RF Channel Center Frequency 2.4 Channel Center Frequency Programming Minimum Step Size 20 Hz Charge-Pump Comparison Frequency 20 MHz Reference Frequency Range Reference Frequency Input Levels Reference Frequency Input Impedance (R || C) Closed-Loop Phase Noise Closed-Loop Integrated Phase Noise 20 AC-coupled to XTAL pin 44 800 Resistance (XTAL) Capacitance (XTAL) mVP-P 5 kΩ 4 pF fOFFSET = 1kHz -86 fOFFSET = 10kHz -94 fOFFSET = 100kHz -94 fOFFSET = 1MHz -110 fOFFSET = 10MHz -120 RMS phase jitter; integrate from 10kHz to 10MHz offset Charge-Pump Output Current Reference Spurs 20MHz offset VCO Frequency Error Measured from Tx-Rx or Rx-Tx transition MHz dBc/Hz 0.9 Degrees 1 mA -55 dBc 3µs to 9µs 50 > 9µs 1 kHz VOLTAGE-CONTROLLED OSCILLATOR Pushing Referred to 2400MHz LO, VCC varies by 0.3V VCO Tuning Voltage Range LO Tuning Gain 8 210 0.5 kHz 2.2 VTUNE = 0.5V 103 VTUNE = 2.2V 86 _______________________________________________________________________________________ V MHz/V 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA (MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, fLO = 2.437GHZ, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS CRYSTAL OSCILLATOR On-Chip Tuning Capacitance Range Maximum capacitance, A3:A0 = 1110, D6:D0 = 1111111 15.4 Minimum capacitance, A3:A0 = 1110, D6:D0 = 0000000 0.5 On-Chip Tuning Capacitance Step Size pF 0.12 pF ON-CHIP TEMPERATURE SENSOR TA = -40°C Output Voltage A3:A0 = 1000, D9:D8 = 01 0.35 TA = +25°C 1 TA = +85°C 1.6 V AC ELECTRICAL CHARACTERISTICS—Timing (MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, PLL loop bandwidth = 150kHz, and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS SYSTEM TIMING (See Figure 3) From SHDN rising edge to LO settled within 1kHz using external reference frequency input Turn-On Time 60 µs Crystal Oscillator Turn-On Time 90% of final output amplitude level 1 ms Channel Switching Time Loop BW = 150kHz, fRF = 2.5GHz to 2.4GHz 25 µs 2 Rx/Tx Turnaround Time Measured from Tx or Rx enable rising edge; signal settling to within ±2dB of steady state Rx to Tx µs Tx to Rx, RXHP = 1 Tx Turn-On Time (from Standby Mode) From Tx-enable active rising edge; signal settling to within ±2dB of steady state Tx Turn-Off Time (from Standby Mode) From Tx-enable inactive rising edge Rx Turn-On Time (from Standby Mode) Rx Turn-Off Time (from Standby Mode) 2 1.5 µs 1 µs From Rx-enable active rising edge; signal settling to within ±2dB of steady state 1.9 µs From Rx-enable inactive rising edge 0.1 µs _______________________________________________________________________________________ 9 MAX2831/MAX2832 AC ELECTRICAL CHARACTERISTICS—Miscellaneous Blocks MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA AC ELECTRICAL CHARACTERISTICS—Timing (continued) (MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, PLL loop bandwidth = 150kHz, and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 3-WIRE SERIAL-INTERFACE TIMING (See Figure 2) SCLK Rising Edge to CS Falling Edge Wait Time, tCSO 6 ns Falling Edge of CS to Rising Edge of First SCLK Time, tCSS 6 ns DIN to SCLK Setup Time, tDS 6 ns DIN to SCLK Hold Time, tDH 6 ns SCLK Pulse-Width High, tCH 6 ns SCLK Pulse-Width Low, tCL 6 ns Last Rising Edge of SCLK to Rising Edge of CS or Clock to Load Enable Setup Time, tCSH 6 ns CS High Pulse Width, tCSW 20 ns Time Between the Rising Edge of CS and the Next Rising Edge of SCLK, tCS1 6 ns Clock Frequency, fCLK 20 MHz Rise Time, tR 2 ns Fall Time, tF 2 ns Note 1: Min and max limits are guaranteed by test at TA = +25°C and +85°C and guaranteed by design and characterization at TA = -40°C. The power-on register settings are not production tested. Recommended register setting must be loaded after VCC is supplied. Note 2: Guaranteed by design and characterization. Note 3: The nominal part-to-part variation of the RF gain step is ±1dB. Note 4: Two tones at +25MHz and +48MHz offset with -35dBm/tone. Measure IM3 at 2MHz. Note 5: Tx I/Q inputs = 100mVRMS. 10 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA TA = +85°C 40 35 LNA = MEDIUM GAIN 20 15 61 10 0 Rx EVM vs. PIN Rx EVM vs. VOUT LNA = LOW GAIN LNA = HIGH GAIN 20 18 3.0 MAX2831/32 toc05 22 LNA = MEDIUM GAIN 2.5 PIN = -50dBm LNA = HIGH GAIN 16 LNA MEDIUM/HIGHGAIN SWITCH POINT 2.0 EVM (%) LNA MEDIUM/LOWGAIN SWITCH POINT EVM (%) 14 -3 -4 LNA = LOW GAIN 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 BASEBAND GAIN SETTINGS 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 BASEBAND GAIN SETTINGS MAX2831/32 toc04 -2 LNA = MEDIUM GAIN 20 0 Rx IN-BAND OUTPUT P-1dB vs. GAIN -1 40 5 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V) 0 50 30 LNA = HIGH GAIN 10 TA = -40°C 60 MAX2831/32 toc06 TA = +25°C 25 GAIN (dB) NF (dB) 64 62 LNA = HIGH GAIN 80 30 63 12 10 8 -5 1.5 1.0 6 4 -6 0.5 2 0 75 85 0 -80 95 OFDM EVM WITH OFDM JAMMER vs. OFFSET FREQUENCY PIN = -62dBm fOFFSET = 20MHz -60 -50 -40 -30 PIN (dBm) -20 -10 0 -50 -60 -80 dBM fOFFSET = 25MHz -90 -120 -20 LOW GAIN -25 -140 PJAMMER (dBm) -15 HIGH GAIN -130 fOFFSET = 40MHz -35 MID GAIN -10 -110 -45 -5 RBW = 300kHz LNA = LOW GAIN -100 -55 LNA INPUT RETURN LOSS vs. RF FREQUENCY MAX2831/32 toc08 -40 -70 -65 -29 -27 -25 -23 -21 -19 -17 -15 -13 -11 -9 VOUT (dBVRMS) Rx EMISSION SPECTRUM, LNA INPUT MAX2831/32 toc07 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -70 INPUT RETURN LOSS (dB) 45 55 GAIN (dB) 4x VCO 35 1.5 VCO LEAKAGE 25 2x VCO LEAKAGE 3x VCO 15 MAX2831/32 toc09 -7 VCO LEAKAGE OUTPUT P-1dB (dBVRMS) 90 70 65 ICC (mA) LNA = LOW GAIN MAX2831/32 toc03 66 100 MAX2831/32 toc02 45 MAX2831/32 toc01 67 EVM (%) Rx VOLTAGE GAIN vs. BASEBAND GAIN SETTING NOISE FIGURE vs. BASEBAND GAIN SETTINGS Rx ICC vs. VCC -25 -30 DC 26.5GHz 2300 2350 2400 2450 2500 RF FREQUENCY (MHz) 2550 ______________________________________________________________________________________ 2600 11 MAX2831/MAX2832 Typical Operating Characteristics (MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) Typical Operating Characteristics (continued) (MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) Rx RSSI STEP RESPONSE (+32dB LNA GAIN STEP) Rx RSSI OUTPUT vs. INPUT POWER Rx RSSI STEP RESPONSE (-32dB LNA GAIN STEP) MAX2831/32 toc11 MAX2831/32 toc10 3.0 LNA = HIGH GAIN 2.5 RSSI OUTPUT (V) MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/32 toc12 3V 3V 0 0V 1.45V 1.5V LNA = MEDIUM GAIN 2.0 1.5 1.0 LNA = LOW GAIN 0.5 0.45 0V 0 200ns/div 200ns/div Rx I/Q DC OFFSET SETTLING RESPONSE (+8dB BB VGA GAIN STEP) Rx I/Q DC OFFSET SETTLING RESPONSE (-8dB BB VGA GAIN STEP) Rx I/Q DC OFFSET SETTLING RESPONSE (-16dB BB VGA GAIN STEP) MAX2831/32 toc13 MAX2831/32 toc14 -120 -100 -80 -60 -40 PIN (dBm) -20 0 20 MAX2831/32 toc15 3V 2.5V 2.0V 0V 0V 0V 10mV 10mV 10mV 5mV 5mV 5mV 0V 0mV 0V 40ns/div 40ns/div 400ns/div Rx I/Q DC OFFSET SETTLING RESPONSE (-32dB BB VGA GAIN STEP) I/Q OUTPUT DC ERROR DROOP (RxHP = 1→0; 100Hz MODE) Rx BB VGA SETTLING RESPONSE (+8 GAIN STEP) MAX2831/32 toc16 MAX2831/32 toc17 MAX2831/32 toc18 3V 3V 3V 0V 0V 0V 0V 10mV -5mV 500mV 5mV -10mV 0V -500mV 0V 400ns/div 12 20ms/div 40ns/div ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA Rx BB VGA SETTLING RESPONSE (-8 GAIN STEP) Rx BB VGA SETTLING RESPONSE (-16 GAIN STEP) MAX2831/32 toc19 Rx BB VGA SETTLING RESPONSE (-32 GAIN STEP) MAX2831/32 toc20 MAX2831/32 toc21 3V 3V 3V 0V 0V 0V 500mV 500mV 500mV 0V 0V 0V -500mV -500mV -500mV 40ns/div 40ns/div 40ns/div RF LNA SETTLING RESPONSE (HIGH TO MEDIUM) RF LNA SETTLING RESPONSE (HIGH TO LOW) Rx BB FREQUENCY RESPONSE vs. FINE SETTING (COARSE SETTING = 8.5MHz) MAX2831/32 toc23 3V 20 3V MAX2831/32 toc24 MAX2831/32 toc22 0 0V 0V 500mV 500mV 0V 0V -500mV -500mV dB -20 -40 -60 -80 -100 1 100ns/div Rx BB FREQUENCY RESPONSE vs. COARSE SETTING (FINE SETTING = 010) RX BASEBAND FILTER GROUP DELAY MAX2831/32 toc25 0 100 HISTOGRAM: Rx STATIC DC OFFSET MAX2831/32 toc26 20 10 FREQUENCY (MHz) 78 65 MAX2831/32 toc27 100ns/div MEAN: 0mV STD: 0.977mV SAMPLE SIZE: 1006 -20 52 dB 20ns/div -40 -60 39 26 -80 13 -100 -120 0 1 10 FREQUENCY (MHz) 100 1 12 1σ/div FREQUENCY (MHz) ______________________________________________________________________________________ 13 MAX2831/MAX2832 Typical Operating Characteristics (continued) (MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) Typical Operating Characteristics (continued) (MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) HISTOGRAM: Rx PHASE IMBALANCE 95 Tx ICC vs. VCC 88 MAX2831/32 toc29 MAX2831/32 toc28 MEAN: 0dB STD: 0.064dB SAMPLE SIZE: 951 115 114 MEAN: 0.3° STD: 0.314° SAMPLE SIZE: 1013 MAX2831/32 toc30 HISTOGRAM: Rx GAIN IMBALANCE 138 TA = +85°C 86 92 76 69 57 46 38 23 19 0 82 80 0 TA = -40°C 78 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V) HISTOGRAM: Tx LO LEAKAGE HISTOGRAM: Tx SIDEBAND SUPPRESSION HISTOGRAM: Tx OUTPUT POWER VARIATION 60 12 MAX2831/32 toc32 MAX2831/32 toc31 72 MEAN: -42dBc STD: 1.9dB SAMPLE SIZE: 1000 32 48 8 24 36 6 16 24 4 8 12 2 0 MEAN: 18.5dBm GAIN ADJUSTED TO ACHIEVE 5.6% EVM 10 0 0 1σ/div 1σ/div 0.1dB/div Tx BASEBAND FREQUENCY RESPONSE Tx OUTPUT POWER vs. FREQUENCY (B6:B1 = 111111) (MAX2832 ONLY) Tx OUTPUT POWER vs. GAIN SETTING (MAX2832 ONLY) -1.0 TA = -40°C POUT (dBm) -30 -40 -50 -60 -70 -80 -1.5 TA = +25°C -2.0 -2.5 TA = +85°C 0.1 1 10 BASEBAND FREQUENCY (MHz) 100 -5 -10 -15 -20 -25 -3.0 -30 -3.5 -35 -40 -4.0 -90 MAX2831/32 toc36 -20 -0.5 POUT (dBm) -10 0 MAX2831/32 toc35 0 MAX2831/32 toc34 0 MAX2831/32 toc33 1σ/div MEAN: -33.45dBc STD: 6.31dB SAMPLE SIZE: 999 40 84 1σ/div 48 14 ICC (mA) TA = +25°C FILTER RESPONSE (dB) MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA 2.40 2.42 2.44 2.46 FREQUENCY (GHz) 2.48 2.50 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 GAIN SETTINGS ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA 11g SPECTRAL MASK (MAX2832 ONLY) 2.00 1.75 1.50 1.25 -24 -18 -12 -6 OUTPUT POWER (dBm) -70 -79 -80 -89 -90 -99 -100 2387 0 2407 2467 -110 2487 DC 26.5GHz Tx GAIN VARIATION vs. FREQUENCY (B6:B1 = 101001) VCCPA = 2.7V 4 250 TA = -40°C TA = +25°C 220 1dB/div VCCPA = 3.0V MAX2831/32 toc40 VCCPA = 3.3V 280 PA SUPPLY CURRENT (mA) MAX2831/32 toc39a VCCPA = 4.2V 5 2447 PA SUPPLY CURRENT vs. POUT 8 6 2427 FREQUENCY (MHz) Tx EVM vs. POUT 7 -60 -69 2x VCO -50 -59 3x VCO -40 -49 MAX2831/32 toc41 -30 TA = +85°C 190 VCCPA = 4.2V 160 3 VCCPA = 2.7V, 3.0V, 3.3V 130 2 2 4 6 0 8 10 12 14 16 18 20 22 POUT (dBm) 2 TA = +25°C 19 2.40 8 10 12 14 16 18 20 22 24 POUT (dBm) -9 MAX2831/32 toc42 GAIN ADJUSTED TO ACHIEVE 5.6% EVM 6 -19 POUT = 18.64dBm EVM = 5.6% -29 2.42 2.44 2.46 FREQUENCY (GHz) 2.48 2.50 802.11g POUT vs. GAIN SETTING (UPPER GAIN CONTROL RANGE) 11g SPECTRAL MASK Tx OUTPUT POWER vs. FREQUENCY 20 4 22 MAX2831/32 toc44 0 MAX2831/32 toc43 20 dBm -39 18 -49 POUT (dBm) EVM (%) -30 -39 -109 1.00 POUT (dBm) -20 4x VCO dBm EVM (%) 2.25 RBW = 1MHz 802.11g SIGNAL 2x RF 2.50 -29 MAX2831/32 toc38 -10 dBm 2.75 POUT = -2.17dBm EVM = 2.12% -19 RF VCO -9 MAX2831/32 toc36a 3.00 Tx OUTPUT SPURS (MAX2832 ONLY) MAX2831/32 toc37 EVM vs. Tx OUTPUT POWER (MAX2832 ONLY) -59 -69 18 16 -79 17 -89 TA = +85°C TA = -40°C 16 2.40 2.42 2.44 2.46 FREQUENCY (GHz) 14 -99 2.48 2.50 -109 2387 12 2407 2427 2447 FREQUENCY (MHz) 2467 2487 40 44 48 52 56 GAIN SETTINGS 60 ______________________________________________________________________________________ 64 15 MAX2831/MAX2832 Typical Operating Characteristics (continued) (MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) Typical Operating Characteristics (continued) (MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) 1.2 fRF = 2.5GHz 0.8 0.6 1.0 0.8 0.6 0.4 0.2 0.2 0 0 4 2 4 50mV TA = -40°C, +25°C 0.6 0 2 4 6 8 10 12 14 16 18 20 22 POUT (dBm) PA OUTPUT POWER HISTORGRAM FOR 1.1V POWER DETECTOR OUTPUT TX I/Q INPUT 12 MEAN = 18.5dBm 10 6 20dBm POWER DETECTOR MAX2831/32 toc47 0.8 8 -300mV 0V 1.0 6 8 10 12 14 16 18 20 22 OUTPUT POWER (dBm) -50mV 1V TA = +85°C 1.2 PA OUTPUT ENVELOPE RESPONSE MAX2831/32 toc48 300mV 1.4 0 0 POWER-DETECTOR OUTPUT PA ENVELOPE 1.6 0.2 6 8 10 12 14 16 18 20 22 OUTPUT POWER (dBm) 20dB GAIN STEP 1.8 0.4 VCCPA = 3.3V, 4.2V MAX2831/32 toc49 2 VCCPA = 2.7V, 3.0V 1.2 0.4 0 MAX2831/32 toc46 1.6 1.4 POWER DETECTOR OVER TEMPERATURE 2.0 POWER DETECTOR (V) 1.4 1.0 1.8 POWER DETECTOR (V) fRF = 2.4GHz 1.6 MAX2831/32 toc45 1.8 POWER DETECTOR OVER SUPPLY VOLTAGE 2.0 4 0 2 PA ENVELOPE -20dBm 0 100ns/div 0.1dB/div 1µs/div PA OUTPUT RETURN LOSS vs. RF FREQUENCY Tx OUTPUT SPURS -15 MAX2831/32 toc52 10 0 -10 VCO 2x RF 2x VCO 3x RF 4x RF -20 -30 -20 RBW = 1MHz 802.11g SIGNAL RF MAX2831/32 toc51 OUTPUT RETURN LOSS (dB) -10 -40 -50 -60 -25 -70 -80 -30 2300 16 2350 2400 2450 2500 RF FREQUENCY (MHz) 2550 2600 -90 DC 26.5GHz ______________________________________________________________________________________ MAX2831/32 toc50 POWER DETECTOR OVER FREQUENCY 2.0 POWER DETECTOR (V) MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA 2500 2450 2400 MAX2831/32 toc54 -60 -70 PHASE NOISE (dBc/Hz) 2550 LO FREQUENCY (MHz) -50 MAX2831/32 toc53 2600 CHANNEL SWITCHING FREQUENCY SETTLING (FROM 2500MHz TO 2400MHz) LO PHASE NOISE vs. OFFSET FREQUENCY LO FREQUENCY vs. VTUNE MAX2831/32 toc55 50kHz -80 -90 10kHz/ div -100 -110 -120 -130 2350 -140 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VTUNE (V) -150 0.001 PLL SETTLING TIME FROM SHUTDOWN TO STANDBY MODE 0 10 PLL SETTLING TIME FROM STANDBY TO Tx MAX2831/32 toc56 50kHz -50kHz 0.01 0.1 1 OFFSET FREQUENCY (MHz) 10kHz/ div Rx TO Tx TURNAROUND PLL SETTLING TIME MAX2831/32 toc57 50kHz 5kHz/ div -25kHz -50kHz 0 2ms 0 CRYSTAL OFFSET FREQUENCY (Hz) fCLOCK = 40MHz CLOAD = 5pF 3V 5kHz/div 0V -25kHz 0 50µs 10ns/div 50µs CRYSTAL-OSCILLATOR OFFSET FREQUENCY vs. CRYSTAL-OSCILLATOR TUNING BITS MAX2831/32 toc60 MAX2831/32 toc59 25kHz 0 30µs CLOCK OUTPUT Tx-Rx TURNAROUND PLL SETTLING TIME MAX2831/32 toc58 25kHz 10kHz/ div -50kHz 250µs 800 700 600 500 400 300 200 100 0 -100 -200 -300 -400 -500 -600 -700 -800 KYOCERA (CX-3225SB) MAX2831/32 toc61 2300 0 10 20 30 40 50 60 70 80 90 100110120130 CTUNE (DIGITAL BITS) ______________________________________________________________________________________ 17 MAX2831/MAX2832 Typical Operating Characteristics (continued) (MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25°C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA RX/TX GAIN CONTROL B3 TXRF+ TXRF- RX/TX GAIN CONTROL MODE CONTROL RXBBI- VCCRXVGA VCCRXFL TXBBQ- TXBBQ+ TXBBI- TXBBI+ RXBBI+ 37 MUX MAX2831 2 RSSI 36 35 TO RSSI MUX 3 MUX 34 4 33 5 32 90° 6 IMUX QMUX 31 0° PLL 7 AM DETECTOR 8 ÷ 9 30 29 CRYSTAL OSCILLATOR/ BUFFER 28 TEMP SENSOR TO RSSI MUX 10 27 POWER DETECTOR B2 11 SHDN 38 TEMP SENSOR RSSI 12 VCCTXPA 13 SERIAL INTERFACE RSSI MUX 14 15 RX/TX GAIN CONTROL 16 17 18 26 ÷ 19 SERIAL INPUTS 20 21 25 22 REFERENCE CLOCK BUFFER OUTPUT 23 RXBBQ+ RXBBQB4 BYPASS TUNE GNDVCO VCCVCO CTUNE XTAL VCCXTAL GNDCP VCCCP 24 CPOUT TX OUTPUT 39 B1 VCCPA 40 LD B7 41 CLOCKOUT RX GAIN CONTROL 42 VCCPLL RXRF- 43 DIN RXRF+ 44 VCCTXMX B6 45 RSSI RX/TX GAIN CONTROL 46 RX I OUTPUTS 1 B5 RX INPUT 47 CS GNDRXLNA VCCRXMX GNDTEST RXTX 48 VCCLNA RX BASEBAND HPF CORNER FREQUENCY CONTROL TX INPUT RXHP MODE CONTROL SCLK MAX2831/MAX2832 Block Diagrams/Typical Operating Circuits RX/TX GAIN CONTROL NOTE: ALL GROUND (PINS 2, 26, AND 31) AND BYPASS CAPACITORS’ GROUND REQUIRE THEIR OWN VIAS TO GROUND. DO NOT CONNECT THEM TO THE EXPOSED PADDLE GROUND. 18 ______________________________________________________________________________________ RX Q OUTPUTS RX/TX GAIN CONTROL 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA TXRF+ TXRFRX/TX GAIN CONTROL MODE CONTROL RXBBI- RXBBI+ VCCRXVGA VCCRXFL TXBBQ- TXBBQ+ TXBBI- TXBBI+ 5 36 35 MUX 34 32 90° 6 31 0° PLL 7 AM DETECTOR 8 ÷ 9 30 29 CRYSTAL OSCILLATOR/ BUFFER 28 TEMP SENSOR TO RSSI MUX 10 B2 11 SHDN 37 33 TEMP SENSOR RSSI 12 VCCTXPA 13 RSSI MUX 14 15 RX/TX GAIN CONTROL 27 SERIAL INTERFACE 16 17 18 SERIAL INPUTS 26 ÷ 19 DIN B3 38 4 SCLK RX/TX GAIN CONTROL RSSI VCCTXMX TX OUTPUT 39 TO RSSI MUX 3 IMUX QMUX VCCPA 40 20 21 25 22 REFERENCE CLOCK BUFFER OUTPUT 23 RXBBQ+ RXBBQB4 RX Q OUTPUTS RX/TX GAIN CONTROL BYPASS TUNE GNDVCO VCCVCO CTUNE XTAL VCCXTAL GNDCP VCCCP 24 CPOUT B7 41 MAX2832 2 RSSI RX GAIN CONTROL 42 B1 RXRF- 43 LD RXRF+ 44 CLOCKOUT B6 45 MUX CS RX/TX GAIN CONTROL 46 RX I OUTPUTS 1 B5 RX INPUT 47 VCCPLL GNDRXLNA VCCRXMX GNDTEST RXTX 48 VCCLNA RX BASEBAND HPF CORNER FREQUENCY CONTROL TX INPUT RXHP MODE CONTROL RX/TX GAIN CONTROL NOTE: ALL GROUND (PINS 2, 26, AND 31) AND BYPASS CAPACITORS’ GROUND REQUIRE THEIR OWN VIAS TO GROUND. DO NOT CONNECT THEM TO THE EXPOSED PADDLE GROUND. ______________________________________________________________________________________ 19 MAX2831/MAX2832 Block Diagrams/Typical Operating Circuits (continued) 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832 Pin Description 20 PIN NAME 1 VCCLNA 2 GNDRXLNA 3 B6 4 RXRF+ 5 RXRF- 6 B7 7 VCCPA 8 B3 9 TXRF+ 10 TXRF- 11 B2 12 SHDN 13 VCCTXPA FUNCTION LNA Supply Voltage LNA Ground Receiver and Transmitter Gain-Control Logic-Input Bit 6 LNA Differential Input. Input is internally AC-coupled and matched to 100Ω differential. Connect directly to a 2:1 balun. Receiver Gain-Control Logic-Input Bit 7 Supply Voltage for Second Stage of Power Amplifier Receiver and Transmitter Gain-Control Logic-Input Bit 3 Power-Amplifier Differential Output for the MAX2831. PA output must be AC-coupled. PA driver internally AC-coupled differential outputs and matched to 100Ω differential for the MAX2832. Connect directly to a 2:1 balun. Receiver and Transmitter Gain-Control Logic-Input Bit 2 Active-Low Shutdown and Standby Logic Input. See Table 31 for operating modes. Supply Voltage for First-Stage of PA and PA Driver 14 B5 Receiver and Transmitter Gain-Control Logic-Input Bit 5 15 CS Active-Low Chip-Select Logic Input of 3-Wire Serial Interface (See Figure 2) 16 RSSI 17 VCCTXMX 18 SCLK RSSI, PA Power Detector (MAX2831 Only) or Temperature-Sensor Multiplexed Analog Output Transmitter Upconverter Supply Voltage Serial-Clock Logic Input of 3-Wire Serial Interface (See Figure 2) 19 DIN 20 VCCPLL Data Logic Input of 3-Wire Serial Interface (See Figure 2) 21 CLOCKOUT 22 LD Lock-Detect Logic Output of Frequency Synthesizer. Output high indicates that the frequency synthesizer is locked. Output programmable as CMOS or open-drain output. (See Tables 16 and 20.) 23 B1 Receiver and Transmitter Gain-Control Logic-Input Bit 1 24 CPOUT Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT and TUNE (see the Block Diagrams/Typical Operating Circuits). 25 VCCCP PLL Charge-Pump Supply Voltage PLL and Registers Supply Voltage. Connect to the supply voltage to retain the register settings. Reference Clock Buffer Output 26 GNDCP Charge-Pump Circuit Ground 27 VCCXTAL Crystal Oscillator Supply Voltage 28 XTAL 29 CTUNE Connection for Crystal Oscillator Off-Chip Capacitors. When using an external reference clock input, leave CTUNE unconnected. 30 VCCVCO VCO Supply Voltage 31 GNDVCO 32 TUNE 33 BYPASS 34 B4 Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input. VCO Ground VCO TUNE Input (see the Block Diagrams/Typical Operating Circuits) On-Chip VCO Regulator Output Bypass. Bypass with a 0.1µF to 1µF capacitor to GND. Do not connect other circuitry to this point. Receiver and Transmitter Gain-Control Logic-Input Bit 4 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA PIN NAME 35 RXBBQ- FUNCTION 36 RXBBQ+ 37 RXBBI- 38 RXBBI+ 39 VCCRXVGA 40 RXHP 41 VCCRXFL Receiver Baseband Q-Channel Differential Outputs. In TX calibration mode, these pins are the LO leakage and sideband detector outputs. Receiver Baseband I-Channel Differential Outputs. In TX calibration mode, these pins are the LO leakage and sideband detector outputs. Receiver VGA Supply Voltage Receiver Baseband AC-Coupling High-Pass Corner Frequency Control Logic Input 42 TXBBQ- 43 TXBBQ+ 44 TXBBI- 45 TXBBI+ Receiver Baseband Filter Supply Voltage Transmitter Baseband I-Channel Differential Inputs Transmitter Baseband Q-Channel Differential Inputs 46 VCCRXMX Receiver Downconverters Supply Voltage 47 GNDTEST Connect to Ground 48 RXTX — EP RX/TX Mode Control Logic Input. See Table 31 for operating modes. Exposed Paddle. Connect to the ground plane with multiple vias for proper operation and heat dissipation. Do not share with any other pin grounds and bypass capacitors' ground. Detailed Description The MAX2831/MAX2832 single-chip, low-power, direct conversion, zero-IF transceivers are designed to support 802.11g/b applications operating in the 2.4GHz to 2.5GHz band. The fully integrated transceivers include a receive path, transmit path, voltage-controlled oscillator (VCO), sigma-delta fractional-N synthesizer, crystal oscillator, RSSI, PA power detector (MAX2831), temperature sensor, Rx and Tx I/Q error-detection circuitry, basebandcontrol interface and linear power amplifier (MAX2831). The only additional components required to implement a complete radio front-end solution are a crystal, a pair of baluns, a BPF, a switch, and a small number of passive components (RCs, no inductors required). Receiver The fully integrated receiver achieves a noise figure of 2.6dB in high-gain mode, and an input compression point of -6dBm in low-gain mode, while consuming only 62mA of supply current. The receiver integrates an LNA and VGA with a 95dB digitally programmable gain control range, direct-conversion downconverters, I/Q baseband lowpass filters with programmable LPF corner frequencies, analog RSSI and integrated DC-offset correction circuitry. A logic-low on the RXTX input (pin 48) and a logic-high on the SHDN input (pin 12) enable the receiver. LNA Input Matching The LNA features a differential input that is internally AC-coupled and internally matched to 100Ω. Connect a 2:1 balun transformer directly to the RXRF+ (pin 4) and RXRF- (pin 5) ports to convert the differential 100Ω input impedance to a single-ended 50Ω input. Provide electrically symmetrical input traces from the LNA input to the balun to maintain IP2 performance and RF common-mode noise rejection. LNA Gain Control The LNA has three gain modes: max gain, max gain 16dB, and max gain - 33dB. The three LNA gain modes can be serially programmed through the SPI™ interface by programming bits D6:D5 in Register 11 (A3:A0 = 1011) or programmed in parallel through the digital logic gain-control pins, B7 (pin 6) and B6 (pin 3). Set bit D12 = 1 in Register 8 (A3:A0 = 1000) to enable programming through the SPI interface, or set bit D12 = 0 to enable parallel programming. See Table 1 for LNA gain-control settings. Table 1. LNA Gain-Control Settings (Pins B7:B6 or Register A3:A0 = 1011, D6:D5) B7 OR D6 B6 OR D5 NAME DESCRIPTION 1 1 High Max gain 1 0 Medium Max gain - 16dB (typ) 0 X Low Max gain - 33dB (typ) SPI is a trademark of Motorola, Inc. ______________________________________________________________________________________ 21 MAX2831/MAX2832 Pin Description (continued) MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA Baseband Variable-Gain Amplifier The receiver baseband variable-gain amplifiers provide 62dB of gain control range programmable in 2dB steps. The VGA gain can be serially programmed through the SPI interface by setting bits D4:D0 in Register 11 (A3:A0 = 1011) or programmed in parallel through the digital logic gain-control pins, B5 (pin 14), B4 (pin 34), B3 (pin 8), B2 (pin 11), and B1 (pin 23). Set bit D12 = 1 in Register 8 (A3:A0 = 1000) to enable serial programming through the serial interface or set bit D12 = 0 to enable parallel programming through the external logic pins. See Table 2 for the gain-step value and Table 3 for baseband VGA gain-control settings. Receiver Baseband Lowpass Filter The receiver integrates lowpass filters that provide an upper -3dB corner frequency of 8.5MHz (nominal mode) with 50dB of attenuation at 20MHz, and 45ns of group delay ripple in the passband (10kHz to 8.5MHz). The upper -3dB corner frequency is tightly controlled on-chip and does not require user adjustment. However, provisions are made to allow fine tuning of the upper -3dB corner frequency. In addition, coarse frequency tuning allows the -3dB corner frequency to be set to 7.5MHz (11b mode), 8.5MHz (11g mode), 15MHz (turbo 1 mode), and 18MHz (turbo 2 mode) by programming bits D1:D0 in Register 8 (A3:A0 = 1000). See Table 4. The coarse corner frequency can be fine-tuned approximately ±10% in 5% steps by programming bits D2:D0 in Register 7 (A3:A0 = 0111). See Table 5 for receiver LPF fine -3dB corner frequency adjustment. Table 2. Receiver Baseband VGA GainStep Value (Pins B5:B1 or Register D4:D0, A3:A0 = 1011) Table 4. Receiver LPF Coarse -3dB Corner Frequency Settings in Register (A3:A0 = 1000) BITS (D1:D0) -3dB CORNER FREQUENCY (MHz) MODE 00 01 7.5 8.5 11b 11g 10 15 Turbo 1 11 18 Turbo 2 Table 5. Receiver LPF Fine -3dB Corner Frequency Adjustment in Register (A3:A0 = 0111) BITS (D2:D0) % ADJUSTMENT RELATIVE TO COARSE SETTING 2 000 90 4 001 95 B3/D2 8 010 100 B4/D3 16 011 105 32 100 110 PIN/BIT GAIN STEP (dB) B1/D0 B2/D1 B5/D4 Table 3. Baseband VGA Gain-Control Settings in Receiver Gain-Control Register (Pin B5:B1 or Register D4:D0, A3:A0 = 1011) 22 Baseband Highpass Filter and DC Offset Correction The receiver implements programmable AC and nearDC coupling of I/Q baseband signals. Temporary ACcoupling is used to quickly remove LO leakage and other DC offsets that could saturate the receiver outputs. When DC offsets have settled, near DC-coupling is enabled to avoid attenuation of the received signal. AC-coupling is set (-3dB highpass corner frequency of 600kHz) when a logic-high is applied to RXHP (pin 40). Near DC-coupling is set (-3dB highpass corner frequency of 100Hz nominal) when a logic-low is applied to RXHP. Bits D13:D12 in Register 7 (A3:A0 = 0111) allow the near DC-coupling -3B highpass corner frequency to be set to 100Hz (D13:D12 = 00), 4kHz (D13:D12 = X1), or 30kHz (D13:D12 = 10). See Table 6. Table 6. Receiver Highpass Filter -3dB Corner Frequency Programming RXHP A3:A0 = 0111, D13:D12 Max 1 XX 600k 11110 Max - 2dB 0 00 100 (recommended) 11101 Max - 4dB 0 X1 4k : : 0 10 30k 00000 Min B5:B1 OR D4:D0 GAIN 11111 -3dB HIGHPASS CORNER FREQUENCY (Hz) X = Don’t care. ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA Received Signal-Strength Indicator (RSSI) The RSSI output (pin 16) can be programmed to multiplex an analog output voltage proportional to the received signal strength, the PA output power (MAX2831), or the die temperature. Set bits D9:D8 = 00 in Register 8 (A3:A0 = 1000) to enable the RSSI output in receive mode (off in transmit mode). Set bit D10 = 1 to enables the RSSI output when RXHP = 1, and disable the RSSI output when RXHP = 0. Set bit D10 = 0 to enable the RSSI output independent of RXHP. See Table 7 for a summary of the RSSI output versus register programming and RXHP. The received signal strength indicator provides an analog voltage proportional to the log of the sum of the squares of the I and Q channels, measured after the receive baseband filters and before the variable-gain amplifiers. The RSSI analog output voltage is proportional to the RF input signal level and LNA gain state over a 60dB range, and is not dependent upon VGA gain. See the graph RX RSSI Output vs. Input Power in the Typical Operating Characteristics for further details. Register 8 (A3:A0 = 1000) and bit D5:D3 in Register 7 (A3:A0 = 0111). The -3dB corner-frequency is tightly controlled on-chip and does not require user adjustment. Additionally, provisions are made to fine tune the -3dB corner frequency through bits D5:D3 in the Filter Programming register (A3:A0 = 0111). See Tables 8 and 9. Table 7. RSSI Pin Truth Table INPUT CONDITIONS A3:A0 = 1000, D9:D8 A3:A0 = 1000, D10 RXHP RSSI OUTPUT X 0 0 No signal 00 0 1 RSSI 01 0 1 Temperature sensor 10 0 1 Power detector (MAX2831) 00 1 X RSSI 01 1 X Temperature sensor 10 1 X Power detector (MAX2831) X = Don’t care. Table 8. Transmitter LPF Coarse -3dB Corner Frequency Settings in Register (A3:A0 = 1000) -3dB CORNER FREQUENCY (MHz) MODE 00 8 11b Transmitter 01 11 11g The transmitter integrates baseband lowpass filters, direct-upconversion mixers, a VGA, a PA driver, and a linear RF PA with a power detector (MAX2831). A logic-high on the RXTX input (pin 48) and a logic-high on the SHDN input (pin 12) enable the transmitter. 10 16.5 Turbo 1 11 22.5 Turbo 2 Transmitter I/Q Baseband Inputs The differential analog inputs of the transmitter baseband amplifier I/Q inputs (TXBBI+, TXBBI-, TXBBQ+, TXBBQ-) have a differential impedance of 20kΩ || 1pF. The inputs require an input common-mode voltage of 0.9V to 1.3V, which is provided by the DC-coupled I and Q DAC outputs of the accompanying baseband IC. Transmitter Baseband Lowpass Filtering The transmitter integrates lowpass filters that can be tuned to -3dB corner frequencies of 8MHz (11b), 11MHz (11g), 16.5MHz (turbo 1 mode), and 22.5MHz (turbo 2 mode) through programming bits D1:D0 in BITS (D1:D0) Table 9. Transmitter LPF Fine -3dB Corner Frequency Adjustment in Register (A3:A0 = 0111) BITS (D5:D3) % ADJUSTMENT RELATIVE TO COARSE SETTING 000 90 001 95 010 100 011 105 100 110 (11g) 101 115 101–111 Not used ______________________________________________________________________________________ 23 MAX2831/MAX2832 Receiver I/Q Baseband Outputs The differential outputs (RXBBI+, RXBBI-, RXBBQ+, RXBBQ-) of the baseband amplifiers have a differential output impedance of ~300Ω, and are capable of driving differential loads up to 10kΩ || 10pF. The outputs are internally biased to a common-mode voltage of 1.1V and are intended to be DC-coupled to the inphase (I) and quadrature (Q) analog-to-digital data converter inputs of the accompanying baseband IC. Additionally, the common-mode output voltage can be adjusted from 1.1V to 1.4V through programming bits D11:D10 in Register 15 (A3:A0 = 1111). MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA Transmitter Variable-Gain Amplifier The variable-gain amplifier of the transmitter provides 31dB of gain control range programmable in 0.5dB steps over the top 8dB of the gain control range and in 1dB steps below that. The transmitter gain can be programmed serially through the SPI interface by setting bits D5:D0 in Register 12 (A3:A0 = 1100) or in parallel through the digital logic gain-control pins B6:B1 (pins 3, 6, 8, 11, 14, 23, and 34, respectively). Set bit D10 = 0 in Register 9 (A3:A0 = 1001) to enable parallel programming, and set bit D10 = 1 to enable programming through the 3-wire serial interface. See Table 10 for the transmitter VGA gain-control settings. Table 10. Transmitter VGA Gain-Control Settings NUMBER D5:D0 Or B6:B1 OUTPUT SIGNAL POWER 63 111111 Max 62 111110 Max - 0.5dB 61 111101 Max - 1.0dB The PA of the MAX2831 has a 100Ω differential output that is internally matched. The output has to be AC-coupled using two off-chip 1.5pF capacitors to a 100Ω:50Ω balun. Provide electrically symmetrical traces from the PA output to the balun to present a balanced load and to reduce out-of-band spurs. Power Detector (MAX2831) The MAX2831 integrates a voltage-peak detector at the PA output and provides an analog voltage proportional to PA output power. See the Power Detector Over Frequency and Power Detector Over Supply Voltage graphs in the Typical Operating Characteristics. Set bits D9:D8 = 10 in Register 8 (A3:A0 = 1000) to multiplex the power-detector analog output voltage to the RSSI output (pin 16). : : : 49 110001 Max - 7dB 48 110000 Max - 7.5dB 47 101111 Max - 8dB 46 101110 Max - 8dB 45 101101 Max - 9dB Synthesizer Programming 44 101100 Max - 9dB The MAX2831/MAX2832 integrate a 20-bit sigma-delta fractional-N synthesizer, allowing the device to achieve excellent phase-noise performance (0.9° RMS from 10kHz to 10MHz), fast PLL settling times, and an RF frequency step-size of 20Hz. The synthesizer includes a divide-by-1 or a divide-by-2 reference frequency divider, an 8-bit integer portion main divider with a divisor range programmable from 64 to 255, and a 20-bit fractional portion main-divider. Bit D2 in Register 5 (A3:A0 = 0101) sets the reference oscillator divider ratio to 1 or 2. Bits D7:D0 in Register 3 (A3:A0 = 0011) set the integer portion of the main divider. The 20-bit fractional portion of the main-divider is split between two registers. The 14 MSBs of the fractional portion are set in Register 4 (A3:A0 = 0100), and the 6 LSBs of the fractional portion of the main divider are set in Register 3 (A3:A0 = 0011). See Tables 11 and 12. : : : 5 000101 Max - 29dB 4 000100 Max - 29dB 3 000011 Max - 30dB 2 000010 Max - 30dB 1 000001 Max - 31dB 0 000000 Max - 31dB Power-Amplifier Driver Output Matching (MAX2832) The PA driver of the MAX2832 has a 100Ω differential output with on-chip AC-coupling capacitors. Provide electrically symmetrical traces to present a balanced load to the PA driver output to help maintain driver linearity and RF common-mode rejection. 24 Power-Amplifier Bias, Enable Delay and Output Matching (MAX2831) The MAX2831 integrates a 2-stage PA, providing +18.5dBm of output power at 5.6% EVM (54Mbps OFDM signal) in 802.11g mode while exceeding the 802.11g spectral mask requirements. The first and second stage PA bias currents are set through programming bits D2:D0 and bits D6:D3 in Register 10 (A3:A0 = 1010), respectively. An adjustable PA enable delay, relative to the transmitter enable (RXTX low-to-high transition), can be set from 200ns to 7µs through programming bits D13:D10 in Register 10 (A3:A0 = 1010). ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA LO Frequency Divider = fRF / fCOMP = 2437MHz / 20MHz = 121.85 Integer Divider = 121 (d) = 0111 1001 (binary) Fractional Divider = 0.85 x (220 - 1) = 891289 (decimal) = 1101 1001 1001 1001 1001 See Table 13 for integer and fractional divider ratios for 802.11g/b systems using a 20MHz comparison frequency. Table 11. Integer Divider Register (A3:A0 = 0011) BIT RECOMMENDED D13:D8 00000 D7:D0 01111001 DESCRIPTION 6 LSBs of 20-Bit Fractional Portion of Main Divider 8-Bit Integer Portion of Main Divider. Programmable from 64 to 255. Table 12. Fractional Divider Register (A3:A0 = 0100) BIT RECOMMENDED D13:D0 11011001100110 DESCRIPTION 14 MSBs of 20-Bit Fractional Portion of Main Divider Table 13. IEEE 802.11g/b Divider-Ratio Programming Words INTEGER DIVIDER FRACTIONAL DIVIDER fRF (MHz) (fRF / fCOMP) A3:A0 = 0011, D7:D0 A3:A0 = 0100, D13:D0 A3:A0 = 0011, D13:D8 2412 120.6 0111 1000b 2666h 1Ah 2417 120.85 0111 1000b 3666h 1Ah 2422 121.1 0111 1001b 0666h 1Ah 2427 121.35 0111 1001b 1666h 1Ah 2432 121.6 0111 1001b 2666h 1Ah 2437 121.85 0111 1001b 3666h 1Ah 2442 122.1 0111 1010b 0666h 1Ah 2447 122.35 0111 1010b 1666h 1Ah 2452 122.6 0111 1010b 2666h 1Ah 2457 122.85 0111 1010b 3666h 1Ah 2462 123.1 0111 1011b 0666h 1Ah 2467 123.35 0111 1011b 1666h 1Ah 2472 123.6 0111 1011b 2666h 1Ah 2484 124.2 0111 1100b 0CCCh 33h ______________________________________________________________________________________ 25 MAX2831/MAX2832 Calculating Integer and Fractional Divider Ratios The desired integer and fractional divider ratios can be calculated by dividing the RF frequency (fRF) by fCOMP. For nominal 802.11g/b operation, a 40MHz reference oscillator is divided by 2 to generate a 20MHz comparison frequency (fCOMP). The following method can be used when calculating divider ratios supporting various reference and comparison frequencies: MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA Crystal Oscillator The crystal oscillator has been optimized to work with low-cost crystals (e.g., Kyocera CX-3225SB). See Figure 1. The crystal oscillator frequency can be fine tuned through bits D6:D0 in Register 14 (A3:A0 = 1110), which control the value of C TUNE from 0.5pF to 15.4pF in 0.12pF steps. See the Crystal-Oscillator Offset Frequency vs. Crystal-Oscillator Tuning Bits graph in the Typical Operating Characteristics. The crystal oscillator can be used as a buffer for an external reference frequency source. In this case, the reference signal is ACcoupled to the XTAL pin, and capacitors C1 and C2 are not connected. When used as a buffer, the XTAL input pin has to be AC-coupled. The XTAL pin has an input impedance of 5kΩ || 4pF, (set D6:D0 = 0000000 in Register 14 A3:A0 = 1110). MAX2831 MAX2832 XTAL C1 CTUNE C2 28 29 CTUNE 1.35kΩ FOR EXTERNAL REFERENCE CLOCK SET, C1 = C2 = OPEN Figure 1. Crystal Oscillator Schematic 26 5.9kΩ Reference Clock Output Divider/Buffer The reference oscillator of the MAX2831/MAX2832 has a divider and a buffered output for routing the reference clock to the accompanying baseband IC. Bit D10 in Register 14 (A3:A0 = 1110) sets the buffer divider to divide by 1 or 2, independent of the divide ratio for the reference frequency provided to the PLL. Bit B9 in the same register enables or disables the reference buffer output. See the Clock Output waveform in the Typical Operating Characteristics. Loop Filter The PLL charge-pump output, CPOUT (pin 24), connects to an external third-order, lowpass RC loop-filter, which in turn connects to the voltage tuning input, TUNE (pin 32), of the VCO, completing the PLL loop. The charge-pump output sink and source current is 1mA, and the VCO tuning gain is 103MHz/V at 0.5V tune voltage and 86MHz/V at 2.2V tune voltage. The RC loop-filter values have been optimized for a loop bandwidth of 150kHz, to achieve the desired Tx/Rx turnaround settling time, while maintaining loop stability and good phase noise. Refer to the MAX2831 EV kit schematic for the recommended loop-filter component values. Keep the line from this pinto the tune input as short as possible to prevent spurious pickup. Lock-Detector Output The PLL features a logic lock-detect output. A logic-high indicates the PLL is locked, and a logic-low indicates the PLL is not locked. Bit D5 in Register 5 (A3:A0 = 0101) enables or disables the lock-detect output. Bit D12 in Register 1 (A3:A0 = 0001) configures the lockdetect output as a CMOS or open-drain output. In opendrain output mode, bit D9 in Register 5 (A3:A0 = 0101) enables or disables an internal 30kΩ pullup resistor from the open-drain output. ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA The MAX2831/MAX2832 include 16 programmable, 18bit registers. The 14 most significant bits (MSBs) are used for register data. The 4 least significant bits (LSBs) of each register contain the register address. See Table 14 for a summary of the registers and recommended register settings. Register data is loaded through the 3-wire SPI/ MICROWIRE™-compatible serial interface. Data is MICROWIRE is a trademark of National Semiconductor Corp. Table 14. Recommended Register Settings* REGISTER DATA ADDRESS TABLE D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (A3:A0) 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0000 15 1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0001 16 2 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0010 17 3 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0011 18 4 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0100 19 5 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0101 20 6 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0110 21 7 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0111 22 8 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1000 23 9 0 0 0 0 1 1 1 0 1 1 0 1 0 1 1001 24 10 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1010 25 11 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1011 26 12 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1100 27 13 0 0 1 1 1 0 1 0 0 1 0 0 1 0 1101 28 14 0 0 0 0 1 1 0 0 1 1 1 0 1 1 1110 29 15 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1111 30 *The power-on register settings are not production tested. Recommended register settings must be loaded after VCC is supplied. BIT 1 DIN BIT 2 BIT 15 BIT 16 BIT 23 BIT 24 SCLK tCH tDS tCS1 tCL CS tCSO tCSS tDH tCSH tCSW Figure 2. 3-Wire SPI Serial-Interface Timing Diagram ______________________________________________________________________________________ 27 MAX2831/MAX2832 shifted in MSB first and is framed by CS. When CS is low, the clock is active, and data is shifted with the rising edge of the clock. When CS transitions high, the shift register is latched into the register selected by the contents of the address bits. See Figure 2. Only the last 18 bits shifted into the device are retained in the shift register. No check is made on the number of clock pulses. For programming data words less than 14 bits long, only the required data bits and the address bits need to be shifted, resulting in faster Rx and Tx gain control where only the LSBs need to be programmed. Programmable Registers and 3-Wire SPI-Interface MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA Table 15. Register 0 (A3:A0 = 0000) DATA BITS RECOMMENDED D13:D11 000 D10 1 D9:D0 1101000000 DESCRIPTION Set to recommended value. Fractional-N PLL Mode Enable. Set 1 to enable the fractional-N PLL or set 0 to enable the integer-N PLL. Set to recommended value. Table 16. Register 1 (A3:A0 = 0001) DATA BITS RECOMMENDED D13 0 Set to recommended value. DESCRIPTION D12 1 Lock-Detector Output Select. Set to 1 for CMOS Output. Set to 0 for open-drain output. Bit D9 in register (A3:A0 = 0101) enables or disables an internal 30kΩ pullup resistor in open-drain output mode. D11:D0 000110011010 Set to recommended value. Table 17. Register 2 (A3:A0 = 0010) DATA BITS RECOMMENDED D13:D0 01000000000011 DESCRIPTION Set to recommended value. This register contains the 8-bit integer portion and 6 LSBs of the fractional portion of the divider ratio of the synthesizer. Table 18. Register 3 (A3:A0 = 0011) BIT RECOMMENDED D13:D8 00000 D7:D0 01111001 DESCRIPTION 6 LSBs of 20-Bit Fractional Portion of Main Divider 8-Bit Integer Portion of Main Divider. Programmable from 64 to 255. Table 19. Register 4 (A3:A0 = 0100) BIT RECOMMENDED D13:D0 11011001100110 DESCRIPTION 14 MSBs of 20-Bit Fractional Portion of Main Divider Table 20. Register 5 (A3:A0 = 0101) 28 BIT RECOMMENDED D13:D10 0000 DESCRIPTION Set to recommended value. Lock-Detect Output Internal Pullup Resistor Enable. Set to 1 to enable internal 30kΩ pullup resistor or set to 0 to disable the resistor. Only available when lock-detect, open-drain output is selected (A3:A0 = 0010, D12 = 1). D9 0 D8:D6 010 D5 1 D4:D3 00 Set to recommended value. D2 1 Reference Frequency Divider Ratio to PLL. Set to 0 to divide by 1. Set to 1 to divide by 2. D1:D0 00 Set to recommended value. Set to recommended value. Lock-Detect Output Enable. Set to 1 to enable the lock-detect output or set to 0 to disable the output. The output is high impedance when disabled. ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA DATA BIT RECOMMENDED D13 0 Set to recommended value. D12:D11 00 Tx I/Q Calibration LO Leakage and Sideband Detector Gain-Control Bits. D12:D11 = 00: 9dB; 01 19dB; 10: 29dB; 11: 39dB. D10:D7 0000 D6 1 D5:D2 1000 DESCRIPTION Set to recommended value. Power-Detector Enable in Tx Mode. Set to 1 to enable the power detector or set to 0 to disable the detector. Set to recommended value. D1 0 Tx Calibration Mode. Set to 1 to place the device in Tx calibration mode or 0 to place the device in normal Tx mode when RXTX is set to 1 (see Table 31). D0 0 Rx Calibration Mode. Set to 1 to place the device in Rx calibration mode or 0 to place the device in normal Rx mode when RXTX is set to 0 (see Table 31). Table 22. Register 7 (A3:A0 = 0111) BIT RECOMMENDED DESCRIPTION D13:D12 01 D11:D6 000000 D5:D3 100 Transmitter Lowpass Filter Corner Frequency Fine Adjustment (Relative to Coarse Setting). See Table 8. Bits D1:D0 in A3:A0 = 1000 provide the lowpass filter corner coarse adjustment. D2:D0 010 Receiver Lowpass Filter Corner Frequency Fine Adjustment (Relative to Coarse Setting). See Table 5. Bits D1:D0 in A3:A0 = 1000 provide the lowpass filter corner coarse adjustment. Receiver Highpass Corner Frequency Setting for RXHP = 0. Set to 00 for 100Hz, X1 for 4kHz, and 10 for 30kHz. Set to recommended value. Table 23. Register 8 (A3:A0 = 1000) BIT RECOMMENDED DESCRIPTION D13 1 Set to recommended value. D12 0 Enable Receiver Gain Programming Through the Serial Interface. Set to 1 to enable programming through the 3-wire serial interface (D6:D0 in Register A3:A0 = 1011). Set to 0 to enable programming in parallel through external digital pins (B7:B1). D11 0 Set to recommended value. D10 0 RSSI Operating Mode. Set to 1 to enable RSSI output independent of RXHP. Set to 0 to disable RSSI output if RXHP = 0, and enable the RSSI output if RXHP = 1. D9:D8 00 RSSI, Power Detector or Temperature Sensor Output Select. Set to 00 to enable the RSSI output in receive mode. Set to 01 to enable the temperature sensor output in receive and transmit modes. Set to 10 to enable the power-detector output in transmit mode. See Table 7. D7:D2 001000 D1:D0 01 Set to recommended value. Receiver and Transmitter Lowpass Filter Corner Frequency Coarse Adjustment. See Tables 4 and 7. ______________________________________________________________________________________ 29 MAX2831/MAX2832 Table 21. Register 6 (A3:A0 = 0110) MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA Table 24. Register 9 (A3:A0 = 1001) BIT RECOMMENDED D13:D11 000 D10 0 D9:D0 1110110101 DESCRIPTION Set to recommended value. Enable Transmitter Gain Programming Through the Serial or Parallel Interface. Set to 1 to enable programming through the 3-wire serial interface (D5:D0 in Register A3:A0 = 1011). Set to 0 to enable programming in parallel through external digital pins (B6:B1). Set to recommended value. Table 25. Register 10 (A3:A0 = 1010) BIT RECOMMENDED D13:D10 0111 DESCRIPTION Power-Amplifier Enable Delay. Sets a delay between RXTX low-to-high transition and internal PA enable. Programmable in 0.5µs steps. D13:D10 = 0001 (0.2µs) and D13:D10 = 1111 (7µs). D9:D7 011 Set to recommended value. D6:D3 0100 Second-Stage Power-Amplifier Bias Current Adjustment. Set to XXXX for 802.11g/b. D2:D0 100 First-Stage Power-Amplifier Bias Current Adjustment. Set to XXX for 802.11g/b. Table 26. Register 11 (A3:A0 = 1011) BIT RECOMMENDED D13:D7 0000000 D6:D5 11 D4:D0 11111 DESCRIPTION Set to recommended value. LNA Gain Control. Set to 11 for high-gain mode. Set to 10 for medium-gain mode, reducing LNA gain by 16dB. Set to 0X for low-gain mode, reducing LNA gain by 33dB. Receiver VGA Control. Set D4:D0 = 00000 for minimum gain and D4:D0 = 11111 for maximum gain. Table 27. Register 12 (A3:A0 = 1100) BIT RECOMMENDED D13:D6 00000101 D5:D0 000000 DESCRIPTION Set to recommended value. Transmitter VGA Gain Control. Set D5:D0 = 000000 for minimum gain, and set D5:D0 = 111111 for maximum gain. Table 28. Register 13 (A3:A0 = 1101) BIT 30 RECOMMENDED DESCRIPTION D13:D10 0011 Set to recommended value. D9:D6 1010 Set to recommended value. D5:D0 010010 Set to recommended value. ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA BIT RECOMMENDED D13:D11 000 D10 0 Reference Clock Output Divider Ratio. Set 1 to divide by 2 or set 0 to divide by 1. D9 1 Reference Clock Output Enable. Set 1 to enable the reference clock output or set 0 to disable. D8:D7 10 Set to recommended value. D6:D0 XXXXXXX MAX2831/MAX2832 Table 29. Register 14 (A3:A0 = 1110) DESCRIPTION Set to recommended value. Crystal-Oscillator Fine Tune. Tunes crystal oscillator over ±20ppm to within ±1ppm. X = Don’t care. Table 30. Register 15 (A3:A0 = 1111) BIT RECOMMENDED DESCRIPTION D13:D12 00 Set to recommended value. D11:D10 00 Receiver I/Q Output Common-Mode Voltage Adjustment. Set D11:D10 = 00: 1.1V, 01: 1.2V, 10: 1.3V, 11: 1.45V. D9:D0 0101000101 Set to recommended value. Table 31. Operating Mode Table LOGIC PINS REGISTER SETTINGS CIRCUIT BLOCK STATES MODE Shutdown SHDN RXTX D1:D0 (A3:A0 = 0110) Rx PATH Tx PATH PLL, VCO, LO GEN, AUTO-TUNER CALIBRATION SECTIONS ON 0 0 00 Off Off Off None Standby 0 1 00 Off Off On None Rx 1 0 X0 On Off On None Tx 1 1 0X Off On On None Rx Calibration 1 0 X1 On (except LNA) Upconverters On Cal tone, RF phase shift, Tx filter Tx Calibration 1 1 1X Off On (except PA driver and PA) On AM detector, Rx I/Q buffers X = Don’t care. ______________________________________________________________________________________ 31 MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA Modes of Operation The modes of operation for the MAX2831/MAX2832 are shutdown, standby, transmit, receive, transmitter calibration, and receiver calibration. See Table 31 for a summary of the modes of operation. The logic-input pins, SHDN (pin 12) and RXTX (pin 48), control the various modes. Shutdown Mode The MAX2831/MAX2832 feature a low-power shutdown mode that disables all circuit blocks, except the serialinterface and internal registers, allowing the registers to be loaded and values maintained, as long as VCC is applied. Set SHDN and RXTX logic-low to place the device in shutdown mode. After supply voltage ramp up, supply current in shutdown mode could be high. Program the default value to SPI register 0 to eliminate high shutdown current. Standby Mode The standby mode is used to enable the frequency synthesizer block while the rest of the device is powered down. In this mode, the PLL, VCO, and LO generators are on, so that Tx or Rx modes can be quickly enabled from this mode. Set SHDN to a logic-low and RXTX to a logic-high to place the device in standby mode. Receive (Rx) Mode The complete receive signal path is enabled in this mode. Set SHDN to logic-high and RXTX to logic-low to place the device in Rx mode. Transmit (Tx) Mode The complete transmitter signal path is enabled in this mode. Set SHDN and RXTX to logic-high to place the device in Tx mode. Tx/Rx Calibration Mode The MAX2831/MAX2832 feature Rx/Tx calibration modes to detect I/Q imbalances and transmit LO leakage. In the Tx calibration mode, all Tx circuit blocks, except the PA driver and external PA, are powered on and active. The AM detector and receiver I and Q channel buffers are also on, along with multiplexers in the receiver side to route this AM detector’s signal. In this mode, the LO leakage calibration is done only for the LO leakage signal that is present at the center frequency of the channel (i.e., in the middle of the OFDM or QPSK spectrum). The LO leakage calibration includes the effect of all DC offsets in the entire baseband paths of the I/Q modulator and direct leakage of the LO to the I/Q modulator output. 32 The LO leakage and sideband detector output are taken at the receiver I and Q channel outputs during this calibration phase. During Tx LO leakage and I/Q imbalance calibration, a sine and cosine signal (f = fTONE) is input to the baseband I/Q Tx pins from the baseband IC. At the LO leakage and sideband-detector output, the LO leakage corresponds to the signal at fTONE and the sideband suppression corresponds to the signal at 2 x fTONE. The output power of these signals vary 1dB for 1dB of variation in the LO leakage and sideband suppression. To calibrate the Tx path, first set the power-detector gain to 9dB using D12:D11 in Register 5 (see Table 21). Adjust the DC offset of the baseband inputs to minimize the signal at fTONE (LO leakage). Then, adjust the baseband input relative magnitude and phase offsets to reduce the signal at 2 x fTONE. In Rx calibration mode, the calibrated Tx RF signal is internally routed to the Rx inputs. In this mode, the VCO/LO generator/PLL blocks are powered on and active except for the low-noise amplifier (LNA). Applications Information Layout Issues The MAX2831 EV kit can be used as a starting point for layout. For best performance, take into consideration grounding and RF, baseband, and power-supply routing. Make connections from vias to the ground plane as short as possible. Do not connect the device ground pin to the exposed paddle ground. Keep the buffered clock output trace as short as possible. Do not share the trace with the RF input layer, especially on or inter-layer or back side of the board. On the high-impedance ports, keep traces short to minimize shunt capacitance. EV kit Gerber files can be requested at www.maxim-ic.com. Power-Supply Layout To minimize coupling between different sections of the IC, a star power-supply routing configuration with a large decoupling capacitor at a central VCC node is recommended. The VCC traces branch out from this node, each going to a separate VCC node in the circuit. Place a bypass capacitor as close as possible to each supply pin. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor for a low-inductance ground connection. Do not share the capacitor ground vias with any other branch and the exposed paddle ground. ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832 POWER SUPPLY ON POWER 3-WIRE SERIAL INTERFACE AVAILABLE IREF SHDN MAC SHUTDOWN MAX2831/MAX2832 RXTX MAC SPI CS CS (SELECT) SCLK SCLK (CLOCK) DIN DIN (DATA) SPI: CHANNEL FREQUENCY, PA BIAS, TRANSMITTER LINEARITY, RECEIVER RSSI OPERATION, CALIBRATION MODE, ETC. INTERNAL PA ENABLED 0 TO 7µs (DRIVES POWER RAMP CONTROL) SHUTDOWN MODE RECEIVE MODE STANDBY MODE PA ENABLE TRANSMIT MODE Figure 3. Timing Diagram Chip Information PROCESS: BiCMOS RXBBI- RXBBI+ VCCRXVGA RXHP VCCRXFL TXBBQ- TXBBQ+ TXBBI- TXBBI+ GNDTEST RXTX TOP VIEW VCCRXMX Pin Configuration Package Information 48 47 46 45 44 43 42 41 40 39 38 37 VCCLNA 1 GNDRXLNA 2 35 RXBBQ- B6 3 34 B4 RXRF+ 4 33 BYPASS RXRF- 5 32 TUNE B7 6 VCCPA 7 + 36 RXBBQ+ 31 GNDVCO MAX2831 MAX2832 30 VCCVCO B3 8 29 CTUNE TXRF+ 9 28 XTAL TXRF- 10 27 VCCXTAL B2 11 SHDN 12 For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 48 TQFN-EP T4877+4 21-0144 90-0130 26 GNDCP EP 25 VCCCP CPOUT B1 LD CLOCKOUT VCCPLL DIN SCLK RSSI VCCTXMX CS B5 VCCTXPA 13 14 15 16 17 18 19 20 21 22 23 24 TQFN ______________________________________________________________________________________ 33 MAX2831/MAX2832 2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA Revision History REVISION NUMBER REVISION DATE 0 10/06 Initial release 1 3/10 Removed MAX2832 future product reference and made minor corrections 2 3/11 Corrected conditions for Rx I/Q Output Common-Mode Voltage Variation in the DC Electrical Characteristics; corrected Tables 14, 17, and 27; added text to Shutdown Mode section DESCRIPTION PAGES CHANGED — 1, 2, 10, 18, 19, 20 2, 27, 28, 30, 32 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.