TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Integrated IF Transceiver for Broadband Wireless Applications FEATURES 1 • • • • • Integrated TX Chain (165–175 MHz / 330–350 MHz) – Baseband Amplifiers – Quadrature Modulator – Digitally Controlled VGA – TX Output IP3: 29.5 dBm – TX Output Noise: –166 dBc/Hz Integrated RX Chain (140–165 MHz / 280–330 MHz) – IF Amplifiers – Analog and Digital VGA – Quadrature Demodulator – Baseband Filters – ADC Buffers – IF SAW Filter Bypass – RX Noise Figure: 4.3 dB – RX Input IP3: 9.5 dBm Integrated TX and RX Synthesizers Integrated Cross-Polarization Interference Cancellation (XPIC) Support Auxiliary RX Chain APPLICATIONS • • • • Wireless Microwave Backhaul Point-to-Point Microwave Broadband Wireless Applications WiMAX IF Transceiver DESCRIPTION The TRF2443 is a highly integrated full-duplex intermediate frequency (IF) transceiver designed for broadband point-to-point wireless communications applications. The receiver chain integrates a quadrature (IQ) demodulator and provides more than 90 dB of gain range, obtained via a combination of analog- and digital-controlled VGAs. The integrated programmable baseband low-pass filter gives the TRF2443 the flexibility to receive signals with different bandwidths, while also helping to remove interferer signals before they reach the ADC. Additionally, the TRF2443 gives the flexibility to add an external IF filter to further remove unwanted signals. The TRF2443 transmitter chain integrates a quadrature (IQ) modulator driving a highly linear IF DVGA that provides 35 dB of gain range controlled via a serial programming interface (SPI). The TRF2443 includes the two synthesizers for the receiver and transmitter chains, removing the need for external LO generation circuitry and simplifying the implementation of a frequency-division duplexing (FDD) transceiver design. The TRF2443 also provides cross-polarization interference cancellation (XPIC) support via an integrated XPIC output amplifier and receiver chain. The TRF2443 is an ideal building block for implementing the IF transceiver function in the indoor unit (IDU), which is connected via a coaxial cable interface to the outdoor unit (ODU), of a point-to-point microwave backhaul split-architecture system. IF SAW IF_OUT RXAGC IF_IN XPIC OUT XPIC_IN XPIC AGC XPIC_BBI 0/90 AGC CNTL XPIC_BBQ from RXPLL RXBBI IFAMP RX_IN TEMPOUT 0/90 RXBBQ RX VGA Temperature Sensor RXPLL VCCs S P I 3 CLKSPI DATASPI LESPI From SPI 7 TXI_IN TX VGA TX_OUT TXPLL GNDs 0/90 Level Detect TXQ_IN TX_PWD 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TRF2443 DEVICE DESCRIPTION IF SAW IF_OUT RXAGC IF_IN XPIC OUT XPIC_IN XPIC AGC XPIC_BBI 0/90 AGC CNTL XPIC_BBQ from RXPLL RXBBI IFAMP RX_IN TEMPOUT 0/90 RXBBQ RX VGA Temperature Sensor RXPLL VCCs S P I 3 CLKSPI DATASPI LESPI From SPI 7 TXI_IN TX VGA TX_OUT TXPLL GNDs 0/90 TXQ_IN Level Detect TX_PWD Figure 1. TRF2443 Functional Block Diagram RECEIVER DESCRIPTION IF SAW RX_AGC IF_OUT AGC CNTL IF_IN BB AMP/FLT RX VGA RX_BBI LNA 0/90 RX_IN IFVGA1 IFVGA2 IFVGA3 RX _BBQ From SPI from RXPLL From SPI Figure 2. Receiver Chain Block Diagram The TRF2443 features a highly linear low-noise receiver chain with over 60 dB of analog-controlled gain range and more than 40 dB of gain range programmable via the serial programming interface (SPI) in 1-dB steps. Moreover, the TRF2443 gives the flexibility to add an external IF filter to further remove unwanted signals. Such an external filter can be bypassed using an internal path that can be enabled via SPI. The first block of the 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 receiver chain is a low-noise, highly linear IF amplifier (LNA). Its input is differential and internally matched to 50 Ω. The TRF2443 LNA attenuation is programmable from 0 dB to –19 dB, corresponding to an LNA gain of 17 dB to –2 dB (1-dB steps). The LNA is followed by three analog-controlled VGAs that provide more than 60 dB of gain range. The IFVGA1 output and IFVGA2 input can be connected externally (pins IFOUT and IFIN) through an external IF filter. An internal switch gives the flexibility to bypass the external filter. The VGAs provide a gain slope of 51 dB/V. The IFVGA3 drives the demodulator, which downconverts the IF input signal directly to baseband in-phase and quadrature. The demodulator block includes the local oscillator in-phase and quadrature generation circuitry followed by the LO buffer. The TRF2443 baseband section integrates a programmable-gain amplifier (PGA) and programmable low-pass filter. The baseband PGA minimum gain is 9 dB, and the maximum gain is 33 dB. The TRF2443 baseband low-pass filter cutoff frequency can be programmed from 2 MHz to 11 MHz by setting the cutoff-frequency control bits appropriately. The baseband output buffers (ADC drivers) are designed to drive directly an analog-to-digital converter (ADC), either dc- or ac-coupled. The output common mode of the ADC drivers is set externally via the RXBBCM pin (pin 40). When the TRF2443 is dc-connected to the ADC, the same dc common mode can be used for both the ADC and the TRF2443 baseband output. TRANSMITTER DESCRIPTION VCC From SPI TX_OUT From TX PLL To feedback switch TXI_IN 6 0/90 TXAMP VCC ATT Level Detect TXQ_IN TX_PWD Figure 3. Transmitter Chain Block Diagram The transmitter chain integrates an IQ modulator followed by a variable attenuator and the final transmitter amplification stage. The last two blocks provide over 35 dB of gain range. A power-alarm circuit monitors the level at the modulator output, and its digital output goes low if the signal level falls below the user-specified threshold level relative to the expected level. The first block of the transmitter chain is the IQ modulator, which upconverts the incoming in-phase and quadrature signals to the TX IF frequency. The TRF2443 can be either acor dc-coupled to the digital-to-analog converter (DAC). The IQ modulator drives a variable attenuator. This block provides 5.5 dB of total attenuation range in 0.5-dB steps. The output amplifier integrates five attenuation steps of 6 dB each for total of 30 dB. The output amplifier in combination with the variable attenuator provides over 35.5 dB of monotonic output power control (0.5-dB steps). SYNTHESIZERS DESCRIPTION TRF2443 integrates two complete integer synthesizers for the receiver and transmitter chain. The RXVCO operates at 16 times the typical RX input frequency, and the TXVCO operates at 8 times the typical TX output frequency. Each synthesizer is composed of: • High-frequency VCO (around 2720 MHz for the TX VCO and 2240 MHz for the RX VCO) • N-divider (driven by the high-frequency VCO) done by an 8/9 prescaler followed by an A-B counter that drives the phase-frequency detector • Phase-frequency detector (PFD) (driven by the N-divider) that compares the VCO divided by N to the reference clock divided by R signals • Charge pump (driven by the PFD) which creates up and down current pulses, based on the incoming signals from the PFD. Its output is filtered and transformed to voltage by the external loop filter and applied to the VCO input control voltage. • An external reference clock must be applied to the REFIN (pin 16). The incoming signal is buffered and goes through a programmable divider (R-divider). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 3 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com The VCO output is then routed through a programmable divider by 8 or 16 to create the TX and RX LO signals. The TRF2443 features a lock-detect output pin (LOCKDET, pin 5). This is a digital output that is high when both RX and TX synthesizers are locked, and it is low if one or both synthesizers are unlocked (or lose lock). XPIC DESCRIPTION The TRF2443 provides cross-polarization interference cancellation (XPIC) support via an integrated XPIC output amplifier and receiver chain. The XPIC output amplifier transmits the signal taken at the receiver demodulator input. The XPIC receiver section downconverts the input signal to baseband I and Q. It includes an IF VGA followed by a demodulator and a baseband amplifier. PINOUT DIAGRAM GNDRX IFOUTP IFOUTN RDBKSPI RXAGC VCCRX GND RXINN RXINP GNDRX GNDRX CLKSPI LESPI VCCSPI DATASPI TXOUTP VCCTX GNDTX TXOUTN GNDTX PFP Package (Top View) TXPWD 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 MIXINDN 2 59 GNDIFIN 58 57 IFINN VCCIFIN MIXINDP PWRDET 3 4 GNDIFIN IFINP LOCKDET 5 56 TXLOTEST 6 55 XPICOUTP VCCVCOTX 54 XPICOUTN GNDVCOTX 7 8 53 RXLOTEST VTUNETX 9 52 VCCVCORX CPOUTX 10 51 GNDVCORX GNDPLLTX 11 50 VTUNERX VCCPLLTX 12 49 CPOUTRX VCCDIGTX 13 48 GNDPLLRX GNDDIGTX 14 47 VCCPLLRX VCCREF 15 46 VCCDIGRX TRF2443 REFIN 16 45 GDNDIGRX GNDREFIN 17 44 RXBBIP GND 18 43 RXBBIN TXBBQN 19 42 RXBBQP TXBBQP 20 41 RXBBQN RXBBCM GNDRX2 LDCAP GND TEMPOUT XPICINP XPICINN GND VCCXPIC2 GND XPICAGC VCCXPIC XPICBBIP XPICBBIN XPICBBQP XPICBBQN XPICBBCM GNDXPIC TXBBIP TXBBIN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P0027-04 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 PIN FUNCTIONS PIN NAME NO. I/O DESCRIPTION CLKSPI 73 I SPI clock CPOUTRX 49 O RX PLL charge-pump output CPOUTX 10 O TX PLL charge-pump output DATASPI 74 I SPI data 18, 31, 32, 36, 66 – Ground GNDDIGRX 45 – RX PLL digital ground GNDDIGTX 14 – TX PLL digital ground 59, 60 – RX chain ground GNDPLLRX 48 – RX PLL ground GNDPLLTX 11 – TX PLL ground GNDREFIN 17 – Reference clock ground 61, 70, 71 – RX chain ground GND GNDIFIN GNDRX GNDRX2 39 – RX chain ground 79, 80 – TX chain ground GNDVCORX 51 – RX VCO ground GNDVCOTX 8 – TX VCO ground GNDXPIC 23 – XPIC ground IFINN 58 I IFVGA2 input: negative terminal IFINP 57 I IFVGA2 input: positive terminal IFOUTN 62 O IFVGA1 output: negative terminal IFOUTP 63 O IFVGA1 output: positive terminal LDCAP 38 I/O PLL lock detector decoupling capacitor pin LESPI 72 I SPI latch enable LOCKDET 5 O PLL lock detect output (digital HIGH = locked, LOW = unlocked) MIXINDN 2 O TX mixer output collector: negative terminal MIXINDP 3 O TX mixer output collector: positive terminal PWRDET 4 O Power alarm output (digital HIGH = output power above threshold; LOW = output power below threshold) RDBKSPI 64 O SPI data readback REFIN 16 I PLL reference clock input RXAGC 65 I RX AGC control input RXBBCM 40 I RX chain common-mode input RXBBIN 43 O RX baseband output I: negative terminal RXBBIP 44 O RX baseband output I: positive terminal RXBBQN 41 O RX baseband output Q: negative terminal RXBBQP 42 O RX baseband output Q: positive terminal RXINN 69 I RX input: negative terminal RXINP 68 I RX input: positive terminal RXLOTEST 53 O RX LO test pin TEMPOUT 37 O Temperature sensor output TXBBIN 21 I TX baseband I input: negative input TXBBIP 22 I TX baseband I input: positive input TXBBQN 19 I TX baseband Q input: negative input TXBBQP 20 I TX baseband Q input: positive input GNDTX Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 5 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com PIN FUNCTIONS (continued) PIN NAME NO. I/O DESCRIPTION TXLOTEST 6 O TX LO test pin TXOUTN 78 O TX IF output: negative terminal TXOUTP 77 O TX IF output: positive terminal TXPWD 1 I TX power down VCCDIGRX 46 – RX PLL digital power supply VCCDIGTX 13 – TX PLL digital power supply VCCIFIN 56 – RX chain power supply VCCPLLTX 12 – TX PLL power supply VCCPLLRX 47 – RX PLL power supply VCCREF 15 – Reference clock power supply VCCRX 67 – RX chain power supply VCCSPI 75 – SPI power supply VCCTX 76 – TX power supply VCCVCORX 52 – RX VCO power supply VCCVCOTX 7 – TX VCO power supply VCCXPIC 29 – XPIC power supply VCCXPIC2 33 – XPIC power supply VTUNERX 50 I RX VCO input control voltage VTUNETX 9 I VCO tune voltage input XPICAGC 30 I XPIC AGC control input XPICBBCM 24 I XPIC common-mode input XPICBBIN 27 O XPIC baseband I output: negative terminal XPICBBIP 28 O XPIC baseband I output: positive terminal XPICBBQN 25 O XPIC baseband Q output: negative terminal XPICBBQP 26 O XPIC baseband Q output: positive terminal XPICINN 34 I XPIC input XPICINP 35 I XPIC input XPICOUTN 54 O XPIC output XPICOUTP 55 O XPIC output 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) Input voltage range (2) VALUE UNIT –0.3 to 5 V ESD rating, HBM 2000 V ESD rating, CDM 500 V TJ Junction temperature range –40 to 150 °C Tstg Storage temperature range –65 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. THERMAL CHARACTERISTICS Over recommended operating free-air temperature (unless otherwise noted) PARAMETER θJA Thermal derating, junction-to-ambient MIN TYP High-K board, still air MAX 8.5 UNIT °C/W RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted) MIN TYP MAX VCC_3V 3.3-V power-supply voltage 3 3.3 3.6 V V_RXAGC Analog AGC voltage (pin 65) 0 2 V V_XPICAGC Analog AGC voltage (pin 30) 0 1 V TJ Operating junction temperature 0 125 °C TA Operating ambient temperature –40 85 °C MAX UNIT 65 UNIT DC CHARACTERISTICS VCC = 3.3 V; TJ = 65°C PARAMETER TEST CONDITIONS MIN TYP TX on; RX on (SAW off); XPIC off ICC Total supply current 947 TX on; RX on (SAW on); XPIC off 965 TX on; RX on (SAW on); XPIC on 1085 mA DIGITAL INTERFACE CHARACTERISTICS VCC = 3.3 V; TJ = 65°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage 2 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage VOL Low-level output voltage 0.8 VCC V 0.2 VCC Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 V 7 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER CHARACTERISTICS VCC_3V = 3.3 V ±5%, TJ = 65°C , IF SAW filter insertion loss = 10 dB (1) (unless otherwise noted) PARAMETER fIF TEST CONDITIONS MIN Input IF frequency TYP MAX 140 UNIT MHz From RX_IN to RX_BBI/RX_ BBQ Gmax (2) Gmin (2) Maximum voltage gain Minimum voltage gain LNA_ATT = 0; RXAGC = 2 V (3) 76 LNA_ATT = 0; RXAGC = 2 V (4) 69 LNA_ATT = 17; RXAGC = 2 V (3) 59 LNA_ATT = 17; RXAGC = 2 V (4) 52 86 LNA_ATT = 0; RXAGC = 0 V (3) 12 25 LNA_ATT = 0; RXAGC = 0 V (4) 12 27 LNA_ATT = 17; RXAGC = 0 V (3) 8 LNA_ATT = 17; RXAGC = 0 V (4) ΔGstep ΔGrange LNA attenuation step LNA_ATT = 17 (5) Digital gain step LNA attenuation setting through SPI (6) RXAGC from 0 V to 2 V Gain flatness From 110 MHz to 170 MHz 54 Gain control slope Noise figure (7) IP3 Input IP3 Γin Input return loss LNA_ATT = 0 (8) (9) 17.9 18.9 dB 62 dB 1.5 dB 51 dB/V 4.5 6 18.5 23 LNA_ATT = 0 (12) (13) -9.5 LNA_ATT = 17 Z0 = 50 Ω, differential 3 dB 1.05 LNA_ATT = 17 (10) (11) (14) (15) dB 10 16.9 Analog gain range NF dB 68 dBm 6.5 –25 dB –12 dB FROM RX_IN TO IF_OUT Gmax Maximum voltage gain ΔGdig Digital gain range ΔGstep Digital gain step ΔGanalog Analog gain range NF Noise figure IP3 Γin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) 8 Programmed by SPI 33 dB 20 dB 1.05 dB 34 dB LNA_ATT = 0, RXAGC = 2 V 3.5 LNA_ATT = 17, RXAGC = 2 V 19.5 Input IP3 LNA_ATT = 0, RXAGC = 2 V –13 Input return loss Z0 = 50 Ω, differential dB dBm –12 dB 10 dB includes SAW filter insertion loss plus matching/board loss Gain measured from transformer input to RXBBI/Q output. External transformer insertion loss = 0.5 dB SAW filter path enabled; baseband amplifier gain setting set to 9 SAW filter path disabled; baseband amplifier gain setting set to 0 Attenuation measured from LNA_ATT = 0 state. Monotonicity of RX gain versus VAGC is specified up to the maximum voltage gain spec and not the maximum VAGC voltage. Automated test equipment 1-sigma measurement uncertainty of 0.15 dB. SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 55 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path enabled; baseband amplifier gain setting set to 3; total gain = 66 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 38 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path enabled; baseband amplifier gain setting set to 3; total gain = 49 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path enabled; baseband amplifier gain setting set to 9; total gain = 33 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 35 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path enabled; baseband amplifier gain setting set to 9; total gain = 16 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 18 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER CHARACTERISTICS (continued) VCC_3V = 3.3 V ±5%, TJ = 65°C , IF SAW filter insertion loss = 10 dB (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FROM IF_IN TO RX_BBI (OR RX_BBQ) Gmax Maximum voltage gain RXAGC = 2 V, RXBB_GAIN = 9 58 dB ΔGdig Digital gain range Programmed by SPI 24 dB ΔGstep Digital gain step 1 dB ΔGanalog Analog gain range 28 dB NF Noise figure Image rejection RXAGC = 2 V, RXBB_GAIN = 9 12.5 RXAGC = 0 V, RXBB_GAIN = 9 28 See RX Image Rejection section -40 Output common mode Baseband output load Parallel capacitor Parallel resistor dB dB 1.5 V 15 pF 1 kΩ BASEBAND LOW-PASS FILTER fC_ON 3-dB cutoff frequency Filter on, programmed via SPI ATT30M Filter rejection at 30 MHz Filter bypassed 3-dB point with fC = 2.3 MHz 2 (16) 2.2 3-dB corner-frequency step (17) Rejection at 4.5 MHz with fC = 2.3 MHz (16) Rejection at 17.5 MHz with fC = 2.3 MHz (16) 8.3 Rejection at 18 MHz with fC = 8.5 MHz (16) 30 Rejection at 35 MHz with fC = 8.5 MHz (16) 65 Rejection at 70 MHz with fC = 8.5 MHz dB MHz 25 kHz 76 dB 80 3-dB point with fC = 8.5 MHz (16) (16) MHz 36 Rejection at 8.75 MHz with fC = 2.3 MHz (16) Filter rejection 11 1 MHz dB 80 (16) After room-temperature cutoff-frequency calibration (17) Baseband filter 3-dB corner frequency control step via SPI around fC = 2.3 MHz Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 9 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TRANSMITTER CHARACTERISTICS VCC_3V = 3.3 V ± 5%, TJ = 65°C (unless otherwise noted) PARAMETER fIout TEST CONDITIONS MIN TYP TX output frequency MAX 340 UNIT MHz FROM TXBBI/Q INPUTS TO TX RFOUT Pmax Maximum output power TX ATT set to 0 (1) Pmin Minimum output power TX ATT set to 35 Grange Gain range Programmed by SPI 31 Gstep 1-dB gain step Two consecutive 1-dB steps 0.8 2.5 dBm –28.5 dB 1.2 TX ATT set to 4 (2) –139 –135 TX ATT set to 31 (2) –166 –162 Nout Output noise floor OIP3 Output IP3 CS Carrier leakage Calibrated; TX ATT set to 4 (4) –55 –35 SBS Side-band suppression Uncalibrated (5) –50 –35 HD2 Second harmonic level See (1) HD3 Third harmonic level See (1) τoff TX turnoff time (6) TX off attenuation (7) VCM Baseband input common-mode voltage (8) ZBBin TX differential input impedance Γout Output return loss Two tones of –2.5 dBm each at TX output (3) 27.5 Two tones of –29.5 dBm each at TX output (3) 0.5 TX_PWD = high 30 dBm/Hz dBm dBm dB dBc –50 10 dB 29.5 –55 TX_PWD: low → high; dBm dBc 100 µs dB 1.4 V Parallel resistor 10 kΩ Parallel capacitor 0.1 pF Z0 = 50 Ω (9) –12 dB (11) dB POWER ALARM DETECTOR (See the Power Alarm Detector section) Detector threshold Response time (12) See (10) (specified by design) See See (11) (11) See µs (1) (2) (3) Measured after the transformer (0.7-dB insertion loss) and with a TXBBI (or TXBBQ) input level of –23 dBVrms No signal applied to TRF2443. This parameter is assured by characterization and is not production tested. Two tones of –26 dBVrms each at TXBBI and TXBBQ inputs at 5 MHz and 8 MHz; measured at transformer output (0.7-dB insertion loss). (4) Using internal common and dc offset control (5) TXIQ_PHASE set to 8; SPI-3, register 1, B<17,13> (6) See the TX Output Power Ramp-Down section. (7) Attenuation of output level from TX on. (8) Common mode input is set internally. It is possible to disable internal bias through SPI and apply external common mode. (9) Single-ended, measured at transformer output (10) Delta output power level at TX fixed gain that forces detector output low (power alarm). (11) Detector threshold and response time are fully programmable by the user. (See the Power Alarm Detector section.) (12) If output power is lower than threshold for more than user-specified value, power-alarm detector output goes low. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RF SYNTHESIZER CHARACTERISTICS VCC_3V = 3.3 V ±5%, TJ = 65°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2640 2800 MHz Divide-by-8 mode 330 350 Divide-by-16 mode 165 175 TXVCO ftxvco TXVCO frequency range ftxlo TXLO frequency range TXLO free-running phase noise KvTX See (1) fout = 340 MHz; offset = 10 kHz –92.5 fout = 340 MHz; offset = 100 kHz –117.5 fout = 340 MHz; offset = 1 MHz –140 fout = 340 MHz; offset = 20 MHz –150 TXVCO gain MHz dBc/Hz 45 MHz/V 20 MHz TXPLL fPFD PFD frequency TXLO closed-loop phase noise fout = 340 MHz; offset = 20 kHz –117 fout = 340 MHz; offset = 100 kHz –116 fout = 340 MHz; offset = 1 MHz –140 fout = 340 MHz; offset = 20 MHz Integrated TXLO noise Integrated from 1 kHz to 12 MHz; fout = 340 MHz Reference spur Measured at TXLOTEST (2720 MHz) Lock time From unlocked state to locked state (includes digital-calibration time) (3) TXLO closed-loop phase noise –150 (2) –56.5 –121 fout = 165 MHz; offset = 100 kHz –120 fout = 165 MHz; offset = 1 MHz –141 TJ = 65°C RXVCO frequency range See dBc µs 300 fout = 165 MHz; offset = 20 kHz PLL-lock minimum power supply dB –70 fout = 165 MHz; offset = 20 MHz Vccmin dBc/Hz dBc/Hz –147 2.8 V RXVCO frxvco frxlo RXLO frequency range RXLO free-running phase noise KvRX (1) 2240 2640 Divide-by-8 mode 280 330 Divide-by-16 mode 140 165 fout = 140 MHz; offset = 10 kHz –97.5 fout = 140 MHz; offset = 100 kHz –122.5 fout = 140 MHz; offset = 1 MHz –146 fout = 140 MHz; offset = 20 MHz –150 RXVCO gain MHz MHz dBc/Hz 45 MHz/V 20 MHz RXPLL fPFD PFD frequency Integrated RXLO noise RXLO closed-loop phase noise (1) (2) (3) (2) –62 Integrated from 1 kHz to 12 MHz; fout = 160 MHz (2) –60 Integrated from 1 kHz to 12 MHz; fout = 140 MHz fout = 140 MHz; offset = 20 kHz –122 fout = 140 MHz; offset = 100 kHz –121 fout = 140 MHz; offset = 1 MHz –146 fout = 140 MHz; offset = 20 MHz –150 Reference spur Measured at RXLOTEST (2240 MHz) Lock time From unlock state to lock state (includes digital-calibration time) (3) dB dBc/Hz –65 300 dBc µs Frequency range proven locked with PFD frequency = 20 MHz Optimized for lowest integrated noise; see the Reference-Clock Characteristics table for recommended reference clock performance. Charge-pump current = 1 mA, PFD frequency = 20 MHz, loop filter optimized (see Application Schematic section) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 11 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com REFERENCE-CLOCK CHARACTERISTICS VCC = 3.3 V PARAMETER fref TEST CONDITIONS MIN Reference frequency Phase noise Reference-clock input level TYP MAX 20 1 kHz –135 Floor –160 REFIN pin, ac-coupled on board (internally dc-coupled) UNIT MHz dBc/Hz 0.8 2 3 MIN TYP MAX VPP XPIC CHARACTERISTICS VCC_3V = 3.3 V ± 5%, TJ = 65°C (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT From RX_IN to XPIC_OUT fin Input frequency Pout Output power Pin = –32 dBm, LNA ATT set to 0 (1) Output power flatness From 110 MHz to 170 MHz Noise figure LNA ATT set to 0, total gain = 20 dB OIP3 Output IP3 Two tones of –16 dBm each at 136 MHz and 144 MHz (1) (2) (3) Γout Output return loss Z0 = 75 Ω, single-ended NF 140 –14 –12 MHz –10 1 15 11.5 dBm dB 22 13 dB dBm –12 dB FROM XPIC_IN TO XPIC_BBI/Q GMAX Maximum gain (4) XPIC_AGC = 0.7 V and XPICBB_GAIN set to 2 GMIN Minimum gain (4) XPIC_AGC = 0 V and XPICBB_GAIN set to 2 21 5 Gain control slope GDRange NF IP3 Γin Digital gain range Programmed via SPI Gain flatness Measured over 110 MHz to 170 MHz Noise figure XPICBB_GAIN set to 2; total gain = 21 dB Input IP3 12 dB 1 dB 22 XPICBB_GAIN set to 2; total gain = 10 dB 6 9.5 Z0 = 75 Ω, single-ended Output common mode (1) (2) (3) (4) dB/V 0 See RX Image Rejection section Parallel capacitor Parallel resistor dB 11 –4 Input return loss dB 10 46 XPICBB_GAIN set to 2; total gain = 21 dB Image rejection Baseband output load 27 25 dB dBm –40 dB –12 dB 1.5 V 15 pF 1 kΩ RXAGC voltage to have RXBBI (or RXBBQ) output level = –17 dBVrms LNA ATT set to 0; total power gain = 20 dB Measured at XPIC_OUT balun output (75-Ω characteristic impedance) Measured from differential output (XPICBBIP/N or XPICBBQP/N) to XPICINN input balun Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, SAW_EN = 0, LNA_ATT = 0, baseband gain setting = 0, 3-dB pad enabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX GAIN vs RX AGC VOLTAGE RX GAIN vs RX AGC VOLTAGE 90 90 TJ = 0°C TJ = 65°C TJ = 125°C 80 70 60 RX Gain (dB) RX Gain (dB) 70 50 40 30 50 40 30 20 10 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) 0 200 400 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) G001 Figure 4. Figure 5. RX INPUT IP3 vs RX GAIN RX INPUT IP3 vs RX GAIN G002 10 10 TJ = 0°C TJ = 65°C TJ = 125°C 0 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0 −10 RX Input IP3 (dBm) −10 RX Input IP3 (dBm) 60 20 0 −20 −30 −40 −50 −60 −20 −30 −40 −50 −60 −70 −70 −80 −80 −90 −90 0 10 20 30 40 50 60 70 80 RX Gain (dB) 90 0 10 20 30 40 50 60 70 80 90 RX Gain (dB) G003 G004 Figure 6. Figure 7. RX NOISE FIGURE vs RX GAIN RX NOISE FIGURE vs RX GAIN 50 50 TJ = 0°C TJ = 65°C TJ = 125°C 40 VCC = 3.1V VCC = 3.3V VCC = 3.5V 45 40 RX Noise Figure (dB) 45 RX Noise Figure (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V 80 35 30 25 20 15 35 30 25 20 15 10 10 5 5 0 0 0 10 20 30 40 50 RX Gain (dB) 60 70 80 90 0 G005 Figure 8. 10 20 30 40 50 60 70 80 RX Gain (dB) 90 G006 Figure 9. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 13 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 3, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX GAIN vs RX AGC VOLTAGE RX GAIN vs RX AGC VOLTAGE 90 90 TJ = 0°C TJ = 65°C TJ = 125°C 80 70 60 RX Gain (dB) RX Gain (dB) 70 50 40 30 50 40 30 20 10 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) 0 200 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) G007 Figure 11. RX INPUT IP3 vs RX GAIN RX INPUT IP3 vs RX GAIN G008 10 TJ = 0°C TJ = 65°C TJ = 125°C 0 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0 −10 RX Input IP3 (dBm) −10 −20 −30 −40 −50 −60 −20 −30 −40 −50 −60 −70 −70 −80 −80 −90 −90 0 10 20 30 40 50 60 70 80 90 RX Gain (dB) 0 10 20 30 40 50 60 70 80 90 RX Gain (dB) G009 G010 Figure 12. Figure 13. RX NOISE FIGURE vs RX GAIN RX NOISE FIGURE vs RX GAIN 50 50 TJ = 0°C TJ = 65°C TJ = 125°C 40 VCC = 3.1V VCC = 3.3V VCC = 3.5V 45 40 RX Noise Figure (dB) 45 35 30 25 20 15 35 30 25 20 15 10 10 5 5 0 0 0 10 20 30 40 50 RX Gain (dB) 60 70 80 90 0 G011 Figure 14. 14 400 Figure 10. 10 RX Input IP3 (dBm) 60 20 0 RX Noise Figure (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V 80 10 20 30 40 50 RX Gain (dB) 60 70 80 90 G012 Figure 15. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 6, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX GAIN vs RX AGC VOLTAGE RX GAIN vs RX AGC VOLTAGE 100 100 TJ = 0°C TJ = 65°C TJ = 125°C 90 80 80 70 RX Gain (dB) RX Gain (dB) 70 60 50 40 50 40 30 20 20 10 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) 0 200 400 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) G013 Figure 16. Figure 17. RX INPUT IP3 vs RX GAIN RX INPUT IP3 vs RX GAIN 10 G014 10 TJ = 0°C TJ = 65°C TJ = 125°C 0 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0 −10 RX Input IP3 (dBm) −10 RX Input IP3 (dBm) 60 30 0 −20 −30 −40 −50 −60 −20 −30 −40 −50 −60 −70 −70 −80 −80 −90 −90 0 10 20 30 40 50 60 70 80 90 RX Gain (dB) 0 10 20 30 40 50 60 70 80 90 RX Gain (dB) G015 G016 Figure 18. Figure 19. RX NOISE FIGURE vs RX GAIN RX NOISE FIGURE vs RX GAIN 50 50 TJ = 0°C TJ = 65°C TJ = 125°C 40 VCC = 3.1V VCC = 3.3V VCC = 3.5V 45 40 RX Noise Figure (dB) 45 RX Noise Figure (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V 90 35 30 25 20 15 35 30 25 20 15 10 10 5 5 0 0 0 10 20 30 40 50 RX Gain (dB) 60 70 80 90 0 G017 Figure 20. 10 20 30 40 50 60 70 80 RX Gain (dB) 90 G018 Figure 21. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 15 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 9, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX GAIN vs RX AGC VOLTAGE RX GAIN vs RX AGC VOLTAGE 100 100 TJ = 0°C TJ = 65°C TJ = 125°C 90 80 80 70 RX Gain (dB) RX Gain (dB) 70 60 50 40 50 40 30 20 20 10 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) 0 200 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) G019 Figure 23. RX INPUT IP3 vs RX GAIN RX INPUT IP3 vs RX GAIN G020 10 TJ = 0°C TJ = 65°C TJ = 125°C 0 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0 −10 RX Input IP3 (dBm) −10 −20 −30 −40 −50 −60 −20 −30 −40 −50 −60 −70 −70 −80 −80 −90 −90 0 10 20 30 40 50 60 70 80 90 100 RX Gain (dB) 0 10 20 30 40 50 60 70 80 90 100 RX Gain (dB) G021 G022 Figure 24. Figure 25. RX NOISE FIGURE vs RX GAIN RX NOISE FIGURE vs RX GAIN 50 50 TJ = 0°C TJ = 65°C TJ = 125°C 40 VCC = 3.1V VCC = 3.3V VCC = 3.5V 45 40 RX Noise Figure (dB) 45 35 30 25 20 15 35 30 25 20 15 10 10 5 5 0 0 0 10 20 30 40 50 60 RX Gain (dB) 70 80 90 100 0 10 G023 Figure 26. 16 400 Figure 22. 10 RX Input IP3 (dBm) 60 30 0 RX Noise Figure (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V 90 20 30 40 50 60 RX Gain (dB) 70 80 90 100 G024 Figure 27. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX LNA ATTENUATION vs LNA ATTENUATION SETTING RX LNA ATTENUATION vs LNA ATTENUATION SETTING 0 0 TJ = 0°C TJ = 65°C TJ = 125°C −4 −6 −8 −10 −12 −14 −16 −18 −6 −8 −10 −12 −14 −16 −20 0 2 4 6 8 10 12 14 16 18 20 LNA Attenuation Setting (SPI-3, REG2<9,6>) 0 2 4 6 8 10 12 14 16 18 20 LNA Attenuation Setting (SPI-3, REG2<9,6>) G037 G038 Figure 29. RX LNA CUMULATIVE ATTENUATION ERROR vs LNA ATTENUATION SETTING RX LNA CUMULATIVE ATTENUATION ERROR vs LNA ATTENUATION SETTING RX LNA Cumulative Attenuation Error (dB) Figure 28. 2.0 TJ = 0°C TJ = 65°C TJ = 125°C 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 2.0 VCC = 3.1V VCC = 3.3V VCC = 3.5V 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LNA Attenuation Setting (SPI-3, REG2<9,6>) LNA Attenuation Setting (SPI-3, REG2<9,6>) 32 30 G086 Figure 30. Figure 31. RX BASEBAND GAIN vs RXBB GAIN SETTING RX BASEBAND GAIN vs RXBB GAIN SETTING 32 30 TJ = 0°C TJ = 65°C TJ = 125°C 28 26 RX Baseband Gain (dB) RX LNA Cumulative Attenuation Error (dB) −4 −18 −20 RX Baseband Gain (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V −2 RX LNA Attenuation (dB) RX LNA Attenuation (dB) −2 24 22 20 18 16 14 12 10 8 G087 VCC = 3.1V VCC = 3.3V VCC = 3.5V 28 26 24 22 20 18 16 14 12 10 8 0 2 4 6 8 10 12 14 16 18 20 RXBB Gain Setting (SPI-3, REG2<15,11>) 22 24 0 2 G039 Figure 32. 4 6 8 10 12 14 16 18 20 22 RXBB Gain Setting (SPI-3, REG2<15,11>) 24 G040 Figure 33. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 17 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER TYPICAL CHARACTERISTICS (continued) fin= 140 MHz (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) 3.0 2.5 RX BASEBAND CUMULATIVE GAIN ERROR vs RXBB GAIN SETTING RX Baseband Cumulative Gain Error (dB) RX Baseband Cumulative Gain Error (dB) RX BASEBAND CUMULATIVE GAIN ERROR vs RXBB GAIN SETTING TJ = 0°C TJ = 65°C TJ = 125°C 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 0 2 4 6 8 10 12 14 16 18 20 RXBB Gain Setting (SPI-3, REG2<15,11>) 22 24 3.0 2.5 VCC = 3.1V VCC = 3.3V VCC = 3.5V 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 0 2 G088 Figure 34. 18 4 6 8 10 12 14 16 18 20 RXBB Gain Setting (SPI-3, REG2<15,11>) 22 24 G089 Figure 35. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER TYPICAL CHARACTERISTICS fin= 280 MHz, SAW_EN = 0, LNA_ATT = 0, baseband gain setting = 0, 3-dB pad enabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RXBBI GAIN vs RX AGC VOLTAGE RXBBI GAIN vs RX AGC VOLTAGE 90 90 TJ = 0°C TJ = 65°C TJ = 125°C 80 70 RXBBI Gain (dB) RXBBI Gain (dB) 70 60 50 40 30 50 40 30 20 10 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) 0 200 400 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) G074 Figure 36. Figure 37. RXBBI INPUT IP3 vs RX GAIN RXBBI INPUT IP3 vs RX GAIN 20 G075 20 TJ = 0°C TJ = 65°C TJ = 125°C 0 VCC = 3.1V VCC = 3.3V VCC = 3.5V 10 RXBBI Input IP3 (dBm) 10 RXBBI Input IP3 (dBm) 60 20 0 −10 −20 −30 −40 −50 −60 0 −10 −20 −30 −40 −50 −60 −70 −70 −80 −80 0 10 20 30 40 50 60 70 80 RX Gain (dB) 0 90 10 20 30 40 50 60 70 80 90 RX Gain (dB) G076 G077 Figure 38. Figure 39. RXBBI NOISE FIGURE vs RX GAIN RXBBI NOISE FIGURE vs RX GAIN 50 50 TJ = 0°C TJ = 65°C TJ = 125°C 40 VCC = 3.1V VCC = 3.3V VCC = 3.5V 45 RXBBI Noise Figure (dB) 45 RXBBI Noise Figure (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V 80 35 30 25 20 15 10 5 40 35 30 25 20 15 10 5 0 0 0 10 20 30 40 50 RX Gain (dB) 60 70 80 90 0 G078 Figure 40. 10 20 30 40 50 60 70 80 RX Gain (dB) 90 G079 Figure 41. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 19 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER TYPICAL CHARACTERISTICS fin= 280 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 9, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RXBBI GAIN vs RX AGC VOLTAGE RXBBI GAIN vs RX AGC VOLTAGE 90 90 TJ = 0°C TJ = 65°C TJ = 125°C 80 70 RXBBI Gain (dB) RXBBI Gain (dB) 70 60 50 40 30 50 40 30 20 10 10 0 0 200 400 600 0 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) 200 600 800 1000 1200 1400 1600 1800 RX AGC Voltage (mV) G080 Figure 43. RXBBI INPUT IP3 vs RX GAIN RXBBI INPUT IP3 vs RX GAIN G081 20 TJ = 0°C TJ = 65°C TJ = 125°C 0 VCC = 3.1V VCC = 3.3V VCC = 3.5V 10 RXBBI Input IP3 (dBm) 10 −10 −20 −30 −40 −50 −60 −70 0 −10 −20 −30 −40 −50 −60 −70 −80 −80 0 10 20 30 40 50 60 70 80 RX Gain (dB) 90 0 10 20 30 40 50 60 70 80 90 RX Gain (dB) G082 G083 Figure 44. Figure 45. RXBBI NOISE FIGURE vs RX GAIN RXBBI NOISE FIGURE vs RX GAIN 50 50 TJ = 0°C TJ = 65°C TJ = 125°C 40 VCC = 3.1V VCC = 3.3V VCC = 3.5V 45 RXBBI Noise Figure (dB) 45 35 30 25 20 15 10 5 40 35 30 25 20 15 10 5 0 0 0 10 20 30 40 50 RX Gain (dB) 60 70 80 90 0 G084 Figure 46. 20 400 Figure 42. 20 RXBBI Input IP3 (dBm) 60 20 0 RXBBI Noise Figure (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V 80 10 20 30 40 50 RX Gain (dB) 60 70 80 90 G085 Figure 47. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) 0 −20 −40 BW = 1.8MHz −60 −80 −100 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 1 0.1 1 Frequency (MHz) RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) BW = 2.3MHz TJ = 0°C TJ = 65°C TJ = 125°C 0.1 1 G056 −20 −40 BW = 2.3MHz −60 VCC = 3.1V VCC = 3.3V VCC = 3.5V −80 0.1 1 Frequency (MHz) G057 Figure 51. RX LOW-PASS FILTER REJECTION vs FREQUENCY RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) −60 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 1 Frequency (MHz) 10 10 G058 Figure 50. BW = 3.5MHz 10 0 −100 0.01 10 −20 −100 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V −80 RX LOW-PASS FILTER REJECTION vs FREQUENCY 0 −80 −60 RX LOW-PASS FILTER REJECTION vs FREQUENCY Frequency (MHz) −40 BW = 1.8MHz Figure 49. −60 −100 0.01 −40 G055 −20 −80 −20 Figure 48. 0 −40 0 −100 0.01 10 Frequency (MHz) RX Low-Pass Filter Rejection (dB) RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) RX LOW-PASS FILTER REJECTION vs FREQUENCY 0 −20 −40 BW = 3.5MHz −60 −80 −100 0.01 G059 Figure 52. VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 1 Frequency (MHz) 10 G060 Figure 53. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 21 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS (continued) (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) 0 −20 −40 BW = 4.5MHz −60 −80 −100 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 1 0.1 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 1 0 −20 −40 BW = 8.5MHz −60 VCC = 3.1V VCC = 3.3V VCC = 3.5V −80 −100 0.01 10 0.1 1 Frequency (MHz) G063 RX LOW-PASS FILTER REJECTION vs FREQUENCY RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) −60 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 1 10 10 G064 Figure 57. BW = 9MHz 10 G062 Figure 56. Frequency (MHz) 0 −20 −40 BW = 9MHz −60 −80 −100 0.01 G065 Figure 58. 22 1 Frequency (MHz) RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) BW = 8.5MHz −20 −100 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V −80 RX LOW-PASS FILTER REJECTION vs FREQUENCY 0 −80 −60 RX LOW-PASS FILTER REJECTION vs FREQUENCY Frequency (MHz) −40 BW = 4.5MHz Figure 55. −60 −100 0.01 −40 G061 −20 −80 −20 Figure 54. 0 −40 0 −100 0.01 10 Frequency (MHz) RX Low-Pass Filter Rejection (dB) RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) RX LOW-PASS FILTER REJECTION vs FREQUENCY VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 1 Frequency (MHz) 10 G066 Figure 59. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS (continued) (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX LOW-PASS FILTER REJECTION vs FREQUENCY RX LOW-PASS FILTER REJECTION vs FREQUENCY 0.5 RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) 0.5 0.0 −0.5 −1.0 BW = 3.5MHz −1.5 −2.0 −2.5 −3.0 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 1 Frequency (MHz) 10 0.0 −0.5 −1.0 BW = 3.5MHz −1.5 −2.0 −2.5 −3.0 0.01 G092 Figure 60. VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 1 Frequency (MHz) 10 G093 Figure 61. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 23 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TRANSMITTER TYPICAL CHARACTERISTICS Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX OUTPUT POWER vs TX ATTENUATION SETTING TX OUTPUT POWER vs TX ATTENUATION SETTING 10 10 TJ = 0°C TJ = 65°C TJ = 125°C 0 −5 −10 −15 −20 −25 −30 0 5 10 −10 −15 −20 −25 fOUT = 340MHz −35 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 35 0 5 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) G041 Figure 63. TX GAIN vs TX ATTENUATION SETTING TX GAIN vs TX ATTENUATION SETTING 35 G042 25 TJ = 0°C TJ = 65°C TJ = 125°C 20 15 VCC = 3.1V VCC = 3.3V VCC = 3.5V 20 15 TX Gain (dB) 10 5 0 −5 −10 10 5 0 −5 −10 −15 −15 fOUT = 340MHz −20 0 5 10 20 25 30 35 0 G043 20 25 TX 0.5-dB GAIN STEP vs TX ATTENUATION SETTING TX 0.5-dB GAIN STEP vs TX ATTENUATION SETTING TX 0.5-dB Gain Step (dB) 0.7 0.6 0.5 0.4 TJ = 0°C TJ = 65°C TJ = 125°C 5 15 Figure 65. 0.7 0 10 Figure 64. 0.8 0.2 5 10 fOUT = 340MHz 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 35 G044 0.6 0.5 0.4 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.3 0.2 35 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 0.8 0.3 fOUT = 340MHz −20 15 TX Attenuation Setting (SPI-3, REG1<12,6>) 0 G047 Figure 66. 24 10 Figure 62. 25 TX Gain (dB) 0 −5 −30 fOUT = 340MHz −35 TX 0.5-dB Gain Step (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V 5 TX Output Power (dBm) TX Output Power (dBm) 5 5 10 fOUT = 340MHz 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 35 G048 Figure 67. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 TRANSMITTER TYPICAL CHARACTERISTICS (continued) Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX 1-dB GAIN STEP vs TX ATTENUATION SETTING TX 1-dB GAIN STEP vs TX ATTENUATION SETTING 1.5 1.5 TJ = 0°C TJ = 65°C TJ = 125°C 1.3 fOUT = 340MHz 1.2 1.1 1.0 0.9 0.8 0.7 0.6 1.2 1.1 1.0 0.9 0.8 0.7 0.5 0 5 10 15 20 25 30 35 TX Attenuation Setting (SPI-3, REG1<12,6>) 0 5 10 15 20 25 30 35 TX Attenuation Setting (SPI-3, REG1<12,6>) G049 Figure 68. Figure 69. TX CUMULATIVE GAIN ERROR vs TX ATTENUATION SETTING TX CUMULATIVE GAIN ERROR vs TX ATTENUATION SETTING 0.5 G050 0.5 TJ = 0°C TJ = 65°C TJ = 125°C 0.4 0.3 fOUT = 340MHz TX Cumulative Gain Error (dB) TX Cumulative Gain Error (dB) 1.3 fOUT = 340MHz 0.6 0.5 0.2 0.1 0.0 −0.1 −0.2 −0.3 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.4 0.3 fOUT = 340MHz 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.4 −0.5 −0.5 5 10 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 10 15 20 25 30 35 G090 G091 Figure 71. UNCALIBRATED TX SIDEBAND SUPPRESSION vs TX ATTENUATION SETTING UNCALIBRATED TX SIDEBAND SUPPRESSION vs TX ATTENUATION SETTING TJ = 0°C TJ = 65°C TJ = 125°C fOUT = 340MHz 50 45 40 35 30 0 5 TX Attenuation Setting (SPI-3, REG1<12,6>) Figure 70. 60 55 0 35 5 10 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 35 Uncalibrated TX Sideband Suppression (dB) 0 Uncalibrated TX Sideband Suppression (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V 1.4 TX 1-dB Gain Step (dB) TX 1-dB Gain Step (dB) 1.4 60 VCC = 3.1V VCC = 3.3V VCC = 3.5V 55 fOUT = 340MHz 50 45 40 35 30 0 G051 Figure 72. 5 10 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 35 G052 Figure 73. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 25 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TRANSMITTER TYPICAL CHARACTERISTICS (continued) Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX CARRIER LEAKAGE vs TX ATTENUATION SETTING TX CARRIER LEAKAGE vs TX ATTENUATION SETTING −40 TJ = 0°C TJ = 65°C TJ = 125°C −50 TX Carrier Leakage (dBm) TX Carrier Leakage (dBm) −40 −60 −70 −80 −90 fOUT = 340MHz −100 0 5 10 20 25 30 −70 −80 −90 35 fOUT = 340MHz 0 5 15 20 25 30 G094 Figure 74. Figure 75. TX OUTPUT IP3 vs TX ATTENUATION SETTING TX OUTPUT IP3 vs TX ATTENUATION SETTING 35 G095 35 TJ = 0°C TJ = 65°C TJ = 125°C 30 VCC = 3.1V VCC = 3.3V VCC = 3.5V 30 TX Output IP3 (dBm) 25 20 15 10 5 25 20 15 10 5 fOUT = 340MHz 0 0 5 10 fOUT = 340MHz 0 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 35 0 5 10 15 20 25 G053 Figure 77. TX IM3 vs TX ATTENUATION SETTING TX IM3 vs TX ATTENUATION SETTING 80 75 75 70 70 65 65 TX IM3 (dBc) 80 60 55 30 TX Attenuation Setting (SPI-3, REG1<12,6>) Figure 76. 50 35 G054 60 55 50 TJ = 0°C TJ = 65°C TJ = 125°C 45 40 0 5 10 VCC = 3.1V VCC = 3.3V VCC = 3.5V 45 fOUT = 340MHz 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 40 35 0 G072 Figure 78. 26 10 TX Attenuation Setting (SPI-3, REG1<12,6>) 35 TX Output IP3 (dBm) −60 −100 15 TX Attenuation Setting (SPI-3, REG1<12,6>) TX IM3 (dBc) VCC = 3.1V VCC = 3.3V VCC = 3.5V −50 5 10 fOUT = 340MHz 15 20 25 30 TX Attenuation Setting (SPI-3, REG1<12,6>) 35 G073 Figure 79. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 TRANSMITTER TYPICAL CHARACTERISTICS (continued) Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX PROGRAMMABLE POWER-SHUTDOWN vs TIME TX PROGRAMMABLE POWER-SHUTDOWN vs TIME 10 10 TJ = 0°C TJ = 65°C TJ = 125°C −10 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0 TX Output Power (dBm) TX Output Power (dBm) 0 −20 −30 −40 −50 −60 −70 −10 −20 −30 −40 −50 −60 −70 SPI-3 REG3<10,9>=<10> SPI-3 REG3<10,9>=<10> −80 −80 0 10 20 30 40 50 60 70 80 90 Time (µs) 100 0 10 20 30 40 50 60 70 80 90 Time (µs) G067 Figure 80. 100 G068 Figure 81. TX OUTPUT NOISE vs TX ATTENUATION SETTING −120 VCC = 3.1V VCC = 3.3V VCC = 3.5V TX Output Noise (dBm/Hz) −125 −130 −135 −140 −145 −150 −155 −160 −165 Note: No Input Signal −170 0 5 10 15 20 25 TX Attenuation Setting (SPI-3, REG1<12,6>) 30 G069 Figure 82. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 27 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com PLL TYPICAL CHARACTERISTICS Measured at TXLOTEST pin (6) and RXLOTEST pin (53). Charge-pump current = 1 mA, PFD frequency = 20 MHz, loop filter optimized (see Application Schematic section). (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX VCO PHASE NOISE TX VCO PHASE NOISE −90 −90 TJ = 0°C TJ = 65°C TJ = 125°C −110 −120 BW = 2720MHz −130 −140 −150 −160 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V −100 Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) −100 −110 −120 BW = 2720MHz −130 −140 −150 0.1 1 10 −160 0.01 100 Frequency Offset (MHz) 0.1 1 G096 Figure 83. RX VCO PHASE NOISE RX VCO PHASE NOISE TJ = 0°C TJ = 65°C TJ = 125°C Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) VCC = 3.1V VCC = 3.3V VCC = 3.5V −100 −110 BW = 2240MHz −130 −140 −150 −110 −120 BW = 2240MHz −130 −140 −150 0.1 1 Frequency Offset (MHz) 10 100 −160 0.01 G098 Figure 85. 28 G097 −90 −100 −160 0.01 100 Figure 84. −90 −120 10 Frequency Offset (MHz) 0.1 1 Frequency Offset (MHz) 10 100 G099 Figure 86. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 XPIC RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, XPIC baseband gain setting = 2 (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) XPIC RX GAIN vs XPIC AGC VOLTAGE XPIC RX GAIN vs XPIC AGC VOLTAGE 30 30 TJ = 0°C TJ = 65°C TJ = 125°C 20 15 10 5 15 10 0 0 100 200 300 400 500 600 700 XPIC AGC Voltage (mV) 0 100 200 300 400 500 600 700 XPIC AGC Voltage (mV) G025 Figure 87. Figure 88. XPIC RX INPUT IP3 vs XPIC RX GAIN XPIC RX INPUT IP3 vs XPIC RX GAIN G026 14 14 TJ = 0°C TJ = 65°C TJ = 125°C 10 VCC = 3.1V VCC = 3.3V VCC = 3.5V 12 XPIC RX Input IP3 (dBm) 12 XPIC RX Input IP3 (dBm) 20 5 0 8 6 4 2 0 −2 10 8 6 4 2 0 −2 −4 −4 0 5 10 15 20 25 XPIC RX Gain (dB) 30 0 5 10 15 20 25 XPIC RX Gain (dB) G027 Figure 89. Figure 90. XPIC RX NOISE FIGURE vs XPIC RX GAIN XPIC RX NOISE FIGURE vs XPIC RX GAIN 50 30 G028 50 TJ = 0°C TJ = 65°C TJ = 125°C 40 VCC = 3.1V VCC = 3.3V VCC = 3.5V 45 XPIC RX Noise Figure (dB) 45 XPIC RX Noise Figure (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V 25 XPIC RX Gain (dB) XPIC RX Gain (dB) 25 35 30 25 20 15 40 35 30 25 20 15 10 10 0 5 10 15 20 XPIC RX Gain (dB) 25 30 0 G029 Figure 91. 5 10 15 20 25 XPIC RX Gain (dB) 30 G030 Figure 92. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 29 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com INSERTION LOSSES TYPICAL CHARACTERISTICS Measured after transformers (see Application Schematic section). (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) INPUT RETURN LOSS XPICIN OUTPUT RETURN LOSS XPICOUT −10 VCC = 3.1V VCC = 3.3V VCC = 3.5V −15 Output Return Loss XPICOUT (dB) Input Return Loss XPICIN (dB) −10 −20 −25 −30 −35 VCC = 3.1V VCC = 3.3V VCC = 3.5V −15 −20 −25 −30 −35 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) G031 Figure 93. INPUT RETURN LOSS IFIN OUTPUT RETURN LOSS IFOUT −10 VCC = 3.1V VCC = 3.3V VCC = 3.5V Output Return Loss IFOUT (dB) Input Return Loss IFIN (dB) −10 −15 −20 −25 −30 −35 VCC = 3.1V VCC = 3.3V VCC = 3.5V −15 −20 −25 −30 −35 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) G033 Figure 95. OUTPUT RETURN LOSS TXOUT 0 −10 LNA_ATTN = 6 LAN_ATTN = 9 Output Return Loss TXOUT (dB) LNA_ATTN = 0 LAN_ATTN = 3 Input Return Loss RXIN (dB) G034 Figure 96. INPUT RETURN LOSS RXIN vs LNA_ATT −15 −20 −25 −30 −35 LNA_ATTN = 12 LAN_ATTN = 15 LNA_ATTN = 18 −40 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) VCC = 3.1V VCC = 3.3V VCC = 3.5V −5 −10 −15 −20 −25 −30 −35 300 G035 Figure 97. 30 G032 Figure 94. 310 320 330 340 350 Frequency (MHz) 360 370 380 G036 Figure 98. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 SPI REGISTERS The TRF2443 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift register. There are a total of three signals that must be applied: the clock (CLKSPI), the serial data (DATASPI) and the latch enable (LESPI). The TRF2443 has an additional pin (RDBKSPI) for readback functionality. This pin is a digital pin and can be used to read back values of different internal registers. The DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of the CLOCK. The latch enable is asynchronous to the CLOCK, and at its rising edge the data in the shift register is loaded onto the selected internal register. The 5 LSBs of the data field are the address bits to select the available internal registers (see Figure 99). The SPI can operate reliably at clock speeds up to 20 MHz (clock period <50 ns). In theory, two 32-bit registers could be programmed within 3.3 µs (64 clock cycles at 50 ns per clock cycle plus setup times). However, the user must exercise care when writing consecutive registers to ensure that subsequent register writes do not disrupt a previously requested operation such as a calibration. Calibration times are functions of the external reference frequency used as well as internally programmable clock dividers set by the user. The application section of this data sheet describes how to determine these calibration times. The user should allow for such calibration times when writing registers to the serial interface that contain settings related to the calibration or settings related to the circuits which are being calibrated. t su1 CLOCK REGISTER WRITE th t(CLK) t (CL) 1stWrite clock pulse DB0 (LSB) Address Bit0 32nd Write clock pulse t (CH) DB1 Address Bit1 DB2 Address Bit2 DB3 Address Bit3 DB29 DB30 DB31(MSB) DATA tsu2 tsu3 tw “End of Write Cycle” pulse LATCH ENABLE Figure 99. SPI Timing Diagram Table 1. SPI Timing – Writing Phase SYMBOL PARAMETER MIN TYP MAX UNITS th Hold time, data to clock 20 ns tSU1 Setup time, data to clock 20 ns t(CL) Clock low duration 20 ns t(CH) Clock high duration 20 ns tSU2 Setup time, clock to enable 20 ns tW Enable Time 50 ns t(CLK) Clock period 50 ns tSU3 Setup time, latch to data 70 ns TRF2443 Addressing Scheme The TRF2443 has a separate set of register banks for the EEPROM (SPI-0), TX PLL (SPI-1), RX PLL (SPI-2), and TX/RX functionality (SPI-3). Each of the register banks has unique address bits to identify it, and within each register bank there are several registers which require an additional 3 bits of addressing. Each register is 32 bits long; the bits can be described by B<31,0>. The 5 LSBs of each register, (B<4,0>), are the address bits, with B<4,3> corresponding to the address of the register bank and B<2,0> corresponding to the address of the individual register within each bank (see Table 2). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 31 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com Table 2. SPI Register Bank Addresses REGISTER BANK ADDRESS NUMBER OF REGISTERS EEPROM 00 3 TX PLL 01 6 RX PLL 10 6 TX/RX 11 8 Table 3. SPI Register Addresses NAME POWER-ON VALUE SUGGESTED VALUE DESCRIPTION B0 ADDR <0> X X Register address: B<2,0> B1 ADDR <1> X X For PLLs (SPI-1 and SPI-2): B2 ADDR <2> X X Reg 0(000), Reg 1(001), Reg 2 (010), Reg 3 (011), Reg 4 (100), Reg 5 (101) For TX_RX (SPI-3): Address bits Data field 32 Reg 0 (000), Reg 1(001), Reg 2 (010), Reg 3 (011), Reg 4 (100), Reg 5 (101), Reg 6(110), Reg 7(111) (Note: In TX_RX (SPI-3), Reg 0 has special functionality as described in the TX and RX SPI Registers section.) B3 ADDR <3> X X Register bank: B<4,3> B4 ADDR <4> X X TX PLL (01); RX PLL (10); TX_RX (11) B5 Data bit (LSB) X X B6 Data bit X X B7 Data bit X X B8 Data bit X X B9 Data bit X X B10 Data bit X X B11 Data bit X X B12 Data bit X X B13 Data bit X X B14 Data bit X X B15 Data bit X X B16 Data bit X X B17 Data bit X X B19 Data bit X X B20 Data bit X X B21 Data bit X X B22 Data bit X X B23 Data bit X X B24 Data bit X X B25 Data bit X X B26 Data bit X X B27 Data bit X X B28 Data bit X X B29 Data bit X X B30 Data bit X X B31 Data bit (MSB) X X Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 TX Synthesizer SPI registers SPI1 Register 1 Register address Bit0 Bit1 Bit2 SPI address Bit3 Bit4 TX reference divider REF INV Bit19 Bit16 Bit17 Bit18 REGISTER 1 NAME VCO NEG Bit20 Bit5 Bit6 Bit7 Bit8 TX reference divider Bit9 Bit10 Bit11 TX charge-pump current Bit21 Bit22 Bit23 POWER-ON VALUE SUGGESTED VALUE Bit24 Bit25 TX CP DOUBLE Bit26 Bit12 RSV RSB Bit27 Bit28 Bit13 Bit14 Bit15 CP OFF CP UP CP DN Bit29 Bit30 Bit31 DESCRIPTION Bit0 ADDR_0 1 1 Bit1 ADDR_1 0 0 Register address bits Bit2 ADDR_2 0 0 Bit3 ADDR_3 1 1 Bit4 ADDR_4 0 0 Bit5 TXRDIV_0 0 App. specific Bit6 TXRDIV_1 0 App. specific Bit7 TXRDIV_2 0 App. specific Bit8 TXRDIV_3 0 App. specific Bit9 TXRDIV_4 0 App. specific Bit10 TXRDIV_5 0 App. specific Bit11 TXRDIV_6 0 App. specific Bit12 TXRDIV_7 0 App. specific Bit13 TXRDIV_8 0 App. specific Bit14 TXRDIV_9 0 App. specific Bit15 TXRDIV_10 0 App. specific Bit16 TXRDIV_11 0 App. specific Bit17 TXRDIV_12 0 App. specific Bit18 TXRDIV_13 0 App. specific Bit19 TXREF_INV 0 0 Invert reference-clock polarity; 1 = use falling edge Bit20 TXNEG_VCO 1 1 VCO polarity control; 1 = negative slope (negative Kv) Bit21 TXICP_0 0 0 Bit22 TXICP_1 1 1 Bit23 TXICP_2 0 0 Program charge-pump dc current, ICP, from 0.5 mA (1 1111) to 2 mA (0 0000); default value 1 mA (0 1010) Bit24 TXICP_3 1 1 Bit25 TXICP_4 0 0 Bit26 TXICPDOUBLE 0 0 1 = set ICP to double the current Bit27 RSV 0 0 Reserved Bit28 RSV 0 0 Reserved Bit29 TXCP_OVERRIDE 0 0 1 = disable charge pump Bit30 TXCP_UP 0 0 1 = enable the charge-pump source current in disable mode Bit31 TXCP_DN 0 0 1 = enable the charge-pump sink current in disable mode SPI address bits 14-bit reference divider value (minimum value Rmin = 1; maximum value Rmax = 16,383) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 33 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com SPI1 Register 2 Register address Bit0 Bit1 Bit2 Bit16 TX N-divider value Bit17 Bit18 Bit19 REGISTER 2 34 SPI address Bit3 Bit4 NAME Bit20 Bit5 Bit6 Bit7 Bit8 Bit9 Bit21 Bit22 RSV Bit23 Bit24 Bit25 POWER-ON VALUE SUGGESTED VALUE Bit0 ADDR_0 0 0 Bit1 ADDR_1 1 1 Bit2 ADDR_2 0 0 Bit3 ADDR_3 1 1 Bit4 ADDR_4 0 0 Bit5 TX_NINT_0 0 App. specific Bit6 TX_NINT_1 0 App. specific Bit7 TX_NINT_2 1 App. specific Bit8 TX_NINT_3 0 App. specific TX N-divider value Bit10 Bit11 DIV 8–16 Bit26 Bit12 Bit13 CAL clock divider Bit27 Bit28 Bit29 Bit14 Bit15 CAL SEL Bit30 EN CAL Bit31 DESCRIPTION Register address bits SPI address bits TX PLL N-divider division setting Power-On value = 68 (<0000 0000 0100 0100) → fVCO = 2720 MHz (with fPFD = 20 MHz) fout = 340 MHz (minimum value Nmin = 56; maximum value Nmax = 65,535) Bit9 TX_NINT_4 0 App. specific Bit10 TX_NINT_5 0 App. specific Bit11 TX_NINT_6 1 App. specific Bit12 TX_NINT_7 0 App. specific Bit13 TX_NINT_8 0 App. specific Bit14 TX_NINT_9 0 App. specific Bit15 TX_NINT_10 0 App. specific Bit16 TX_NINT_11 0 App. specific Bit17 TX_NINT_12 0 App. specific Bit18 TX_NINT_13 0 App. specific Bit19 TX_NINT_14 0 App. specific Bit20 TX_NINT_15 0 App. specific Bit21 RSV 0 0 Reserved Bit22 RSV 0 0 Reserved Bit23 RSV 0 0 Reserved Bit24 RSV 0 0 Reserved Bit25 RSV 1 1 Reserved Bit26 TXDIV_SEL 1 1 TX VCO divider selection (1 = divide by 8; 0 = divide by 16) Bit27 TXCAL_CLK_0 1 1 Bit28 TXCAL_CLK_1 0 0 Set the clock speed used in the TX VCO frequency autocalibration. The clock is derived from the reference clock through a frequency divider. Bit29 TXCAL_CLK_2 1 1 Bit30 TXCAL_SEL 0 1 Select the TX VCO frequency calibration mode (1 = autocalibration; 0 = manual) Bit31 EN_TXCAL 0 1 Enable TX VCO frequency autocalibration (1 → start) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 TXCAL_CLK<2,0>: Set the frequency divider value used to derive the TX VCO calibration clock from the reference clock (See Table 4) Table 4. TX VCO Calibration Clock Divider vs TXCAL_CLK<2,0> TXCAL_CLK FREQUENCY DIVIDER 000 1 001 8 010 16 011 128 100 256 101 1024 110 2048 111 16,684 SPI1 Register 4 Register address Bit0 Bit1 Bit2 RSV Bit16 Bit17 RSV Bit5 RSV Bit6 RSV Bit7 RSV Bit8 RSV Bit9 RSV Bit10 Power down TX PLL blocks Bit11 Bit12 Bit13 Bit14 RSV Bit15 Power down TX PLL blocks Bit18 Bit19 Bit20 Bit21 Bit22 RSV Bit23 RSV Bit24 RSV Bit25 Bit26 Bit27 TXVCO trim Bit28 Bit29 Bit31 REGISTER 4 SPI address Bit3 Bit4 NAME POWER-ON VALUE SUGGESTED VALUE Bit30 DESCRIPTION Bit0 ADDR_0 0 0 Register address bits Bit1 ADDR_1 0 0 Bit2 ADDR_2 1 1 Bit3 ADDR_3 1 1 Bit4 ADDR_4 0 0 Bit5 RSV 0 0 Reserved Bit6 RSV 0 0 Reserved Bit7 RSV 0 0 Reserved Bit8 RSV 0 0 Reserved Bit9 RSV 1 1 Reserved Bit10 RSV 1 1 Reserved Bit11 PWD_TXCP 0 0 When 1, TX charge pump is off Bit12 PWD_TXVCO 0 0 When 1, TX VCO is off Bit13 PWD_TXBUF1 0 0 Power down VCO buffer 1 (1 = off) Bit14 PWD_TXBUF2 0 0 Power down VCO buffer 2 (1 = off) Bit15 RSV 1 1 Reserved Bit16 PWD_TX_TESTBUF 0 1 Power down TXVCO output buffer, pin TXLOTEST (1 = off) Bit17 PWD_TXDIV2 0 0 Power down VCO divider (1 = off) Bit18 PWD_TXPRESC 0 0 Power down prescaler buffer (1 = off) Bit19 PWD_TXRESYNC 0 0 Power down re-synch D flip-flop (1 = off) Bit20 PWD_TXPLL 0 0 Power down whole TX PLL (1 = off) Bit21 PWD_TXDIV 0 0 Power down LO divider (1 = off) Bit22 PWD_TXDET 0 0 Power down VCO detector (1 = off; used for VCO calibration) Bit23 RSV 0 0 Reserved Bit24 RSV 0 0 Reserved Bit25 RSV 0 0 Reserved SPI address bits Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 35 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com REGISTER 4 NAME POWER-ON VALUE SUGGESTED VALUE Bit26 TXVCO_TRIM_0 0 0 Bit27 TXVCO_TRIM_1 0 0 Bit28 TXVCO_TRIM_2 0 0 Bit29 TXVCO_TRIM_3 0 0 Bit30 TXVCO_TRIM_4 0 0 Bit31 TXVCO_TRIM_5 0 0 DESCRIPTION VCO coarse-frequency tuning control (manual mode) SPI1 Register 5 Register address Bit0 Bit1 Bit2 BUF2 bias Bit16 OUTBUF bias Bit17 Bit18 REGISTER 5 36 SPI address Bit3 Bit4 Bit19 NAME Bit5 TXPLL bias Bit6 Bit7 PRESC bias Bit20 Bit21 BIAS SEL Bit22 RSV Bit8 RSV Bit9 VCO CAL REF Bit23 POWER-ON VALUE SUGGESTED VALUE Bit24 Bit25 Bit10 TXVCO bias Bit11 Bit12 Bit13 BUF1 bias Bit14 Bit15 RSV RSV RSV RSV RSV RSV Bit26 Bit27 Bit28 Bit29 Bit30 Bit31 DESCRIPTION Bit0 ADDR_0 1 1 Bit1 ADDR_1 0 0 Register address bits Bit2 ADDR_2 1 1 Bit3 ADDR_3 1 1 Bit4 ADDR_4 0 0 Bit5 TXPLL_BIAS_0 0 0 Bit6 TXPLL_BIAS_1 0 0 Bit7 TXPLL_BIAS_2 1 1 Bit8 RSV 0 0 Reserved Bit9 RSV 0 0 Reserved Bit10 TXVCO_BIAS_0 0 0 Bit11 TXVCO_BIAS_1 0 0 TX VCO bias control bits. VCO current can be changed from 10 mA (0000) to 25 mA (1111), 1-mA step. Suggested value is 18 mA (1000). Bit12 TXVCO_BIAS_2 0 0 Bit13 TXVCO_BIAS_3 1 1 Bit14 TXBUF1_BIAS_0 0 0 Bit15 TXBUF1_BIAS_1 1 1 Bit16 TXBUF2_BIAS_0 0 0 Bit17 TXBUF2_BIAS_1 1 1 Bit18 TXBUFOUT_BIAS_0 0 0 Bit19 TXBUFOUT_BIAS_1 1 1 Bit20 TXPRES_BIAS_0 1 0 Bit21 TXPRES_BIAS_1 1 1 Bit22 TXVCO_CAL_IB 0 1 Select bias current type for VCO calibration circuitry 1 = PTAT; 0 = constant over temperature Bit23 TXVCO_CAL_REF_0 0 1 TX VCO calibration reference-voltage trimming. Bit24 TXVCO_CAL_REF_1 0 1 000 → 1.175 V Bit25 TXVCO_CAL_REF_2 0 0 111 → 2.05 V. Suggested value is 1.55 V (011). Bit26 RSV 0 0 Reserved Bit27 RSV 0 0 Reserved Bit28 RSV 0 0 Reserved Bit29 RSV 0 0 Reserved Bit30 RSV 0 0 Reserved Bit31 RSV 0 0 Reserved SPI address bits TX PLL reference-current control bits. Adjust reference current from 40 µA to 60 µA. Suggested value is 52 µA (100). It sets the PLL buffer-1 bias from 0.8 mA (00) to 2 mA (11), 0.4-mA step. Suggested value is 1.6 mA (10). It sets the PLL buffer-2 bias from 0.8 mA (00) to 2 mA (11), 0.4-mA step. Suggested value is 1.6 mA (10). TXPLL output-buffer reference bias current. 200 µA (00) to 500 µA (11). Suggested value is 400 µA (10). TXPLL prescaler reference bias current. 200 µA (00) to 500 µA (11). Suggested value is 400 µA (10). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RX Synthesizer SPI registers SPI2 Register 1 Register address Bit0 Bit1 Bit2 — Bit16 Bit17 Bit18 REGISTER 1 SPI address Bit3 Bit4 REF INV Bit19 NAME VCO NEG Bit20 Bit5 Bit6 Bit7 Bit8 RX reference divider Bit9 Bit10 Bit11 RX charge-pump current Bit21 Bit22 Bit23 POWER-ON VALUE SUGGESTED VALUE Bit24 Bit25 RX CP DOUBLE Bit26 Bit12 Bit13 Bit14 Bit15 RSV RSV Bit27 Bit28 CP OFF Bit29 CP UP Bit30 CP DN Bit31 DESCRIPTION Bit0 ADDR_0 1 1 Bit1 ADDR_1 0 0 Register address bits Bit2 ADDR_2 0 0 Bit3 ADDR_3 0 0 Bit4 ADDR_4 1 1 Bit5 RXRDIV_0 0 App. specific Bit6 RXRDIV_1 0 App. specific Bit7 RXRDIV_2 0 App. specific Bit8 RXRDIV_3 0 App. specific Bit9 RXRDIV_4 0 App. specific Bit10 RXRDIV_5 0 App. specific Bit11 RXRDIV_6 0 App. specific Bit12 RXRDIV_7 0 App. specific Bit13 RXRDIV_8 0 App. specific Bit14 RXRDIV_9 0 App. specific Bit15 RXRDIV_10 0 App. specific Bit16 RXRDIV_11 0 App. specific Bit17 RXRDIV_12 0 App. specific Bit18 RXRDIV_13 0 App. specific Bit19 RXREF_INV 0 0 Invert reference-clock polarity; 1 = use falling edge Bit20 RXNEG_VCO 1 1 VCO polarity control; 1 = negative slope (negative Kv) Bit21 RXICP_0 0 0 Bit22 RXICP_1 1 1 Program charge-pump dc current, ICP from 0.5 mA (1 1111) to 2 mA (0 0000); default value 1 mA (0 1010) Bit23 RXICP_2 0 0 Bit24 RXICP_3 1 1 Bit25 RXICP_4 0 0 Bit26 RXICPDOUBLE 0 0 1 = set ICP to double the current Bit27 RSV 0 0 Reserved Bit28 RSV 0 0 Reserved Bit29 RXCP_OVERRIDE 0 0 1 = disable charge pump Bit30 RXCP_UP 0 0 1 = enable the charge-pump source current in disable mode Bit31 RXCP_DN 0 0 1 = enable the charge-pump sink current in disable mode SPI address bits 14-bit reference-divider value (minimum value Rmin = 1; maximum value Rmax = 16,383) SPI2 REGISTER 2 Register address Bit0 Bit1 Bit2 SPI address Bit3 Bit4 Bit5 Bit6 RX N-divider value Bit16 Bit17 Bit18 Bit19 Bit7 Bit8 RX N-divider value Bit9 Bit10 Bit11 Bit24 DIV 8–16 Bit26 RSV Bit20 Bit21 Bit22 Bit23 Bit25 Bit12 Bit13 CAL clock divider Bit27 Bit28 Bit29 Bit14 Bit15 CAL SEL Bit30 EN CAL Bit31 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 37 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com REGISTER 2 NAME POWER-ON VALUE SUGGESTED VALUE DESCRIPTION Bit0 ADDR_0 0 0 Bit1 ADDR_1 1 1 Register address bits Bit2 ADDR_2 0 0 Bit3 ADDR_3 0 0 Bit4 ADDR_4 1 1 Bit5 RX_NINT_0 0 App. specific Bit6 RX_NINT_1 0 App. specific Bit7 RX_NINT_2 0 App. specific Bit8 RX_NINT_3 0 App. specific Bit9 RX_NINT_4 1 App. specific Bit10 RX_NINT_5 1 App. specific Bit11 RX_NINT_6 1 App. specific Bit12 RX_NINT_7 0 App. specific Bit13 RX_NINT_8 0 App. specific Bit14 RX_NINT_9 0 App. specific Bit15 RX_NINT_10 0 App. specific Bit16 RX_NINT_11 0 App. specific Bit17 RX_NINT_12 0 App. specific Bit18 RX_NINT_13 0 App. specific Bit19 RX_NINT_14 0 App. specific Bit20 RX_NINT_15 0 App. specific Bit21 RSV 0 0 Reserved Bit22 RSV 0 0 Reserved Bit23 RSV 0 0 Reserved Bit24 RSV 0 0 Reserved Bit25 RSV 1 1 Reserved Bit26 RXDIV_SEL 0 0 RX VCO divider selection (1 = divide by 8; 0 = divide by 16) Bit27 RXCAL_CLK_0 1 1 Bit28 RXCAL_CLK_1 0 0 Set the clock speed used in the RX VCO frequency autocalibration. The clock is derived from the reference clock through a frequency divider. Bit29 RXCAL_CLK_2 1 1 Bit30 RXCAL_SEL 0 1 Select the RX VCO frequency calibration mode (1 = autocalibration; 0 = manual) Bit31 EN_RXCAL 0 1 Enable RX VCO frequency autocalibration (1 → start) SPI address bits RX PLL N-divider division setting Power-On value = 112 (<00 000 000 0111 0000>) → fVCO = 2240 MHz (with fPFD = 20 MHz) fout = 140 MHz (minimum value Nmin = 56; maximum value Nmax = 65,535) RXCAL_CLK<2,0>: Set the frequency divider value used to derive the TX VCO calibration clock from the reference clock (See Table 5). Table 5. RX VCO Calibration Clock Divider vs. RXCAL_CLK<2,0> 38 RXCAL_CLK FREQUENCY DIVIDER 000 1 001 8 010 16 011 128 100 256 101 1024 110 2048 111 16,684 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 SPI2 Register 4 Register address Bit0 Bit1 Bit2 RSV Bit16 Bit17 RSV Bit5 RSV Bit6 RSV Bit7 RSV Bit8 RSV Bit9 RSV Bit10 Power down RX PLL blocks Bit11 Bit12 Bit13 Bit14 Power down RX PLL blocks Bit18 Bit19 Bit20 Bit21 Bit22 RSV Bit23 RSV Bit24 Bit25 Bit26 Bit27 REGISTER 4 SPI address Bit3 Bit4 NAME POWER-ON VALUE SUGGESTED VALUE RXVCO trim Bit28 Bit29 Bit30 RSV Bit15 Bit31 DESCRIPTION Bit0 ADDR_0 0 0 Bit1 ADDR_1 0 0 Register address bits Bit2 ADDR_2 1 1 Bit3 ADDR_3 0 0 Bit4 ADDR_4 1 1 Bit5 RSV 0 0 Reserved Bit6 RSV 0 0 Reserved Bit7 RSV 0 0 Reserved Bit8 RSV 0 0 Reserved SPI address bits Bit9 RSV 1 1 Reserved Bit10 RSV 1 1 Reserved Bit11 PWD_RXCP 0 0 When 1, RX charge pump is off Bit12 PWD_RXVCO 0 0 When 1, RX VCO is off Bit13 PWD_RXBUF1 0 0 Power down VCO buffer 1 (1 = off) Bit14 PWD_RXBUF2 0 0 Power down VCO buffer 2 (1 = off) Bit15 RSV 1 1 Reserved Bit16 PWD_RX_TESTBUF 0 1 Power down RXVCO output buffer, pin RXLOTEST (1 = off) Bit17 PWD_RXDIV2 0 0 Power down VCO divider (1 = off) Bit18 PWD_RXPRESC 0 0 Power down prescaler buffer (1 = off) Bit19 PWD_RXRESYNC 0 0 Power down re-synch D flip-flop (1 = off) Bit20 PWD_RXPLL 0 0 Power down whole RX PLL (1 = off) Bit21 PWD_RXDIV 0 0 Power down LO divider (1 = off) Bit22 PWD_RXDET 0 0 Power down VCO detector (1 = off; used for VCO calibration) Bit23 RSV 0 0 Reserved Bit24 RSV 0 0 Reserved Bit25 RXVCO_TRIM_0 0 0 VCO coarse frequency tuning control (manual mode) Bit26 RXVCO_TRIM_1 0 0 Bit27 RXVCO_TRIM_2 0 0 Bit28 RXVCO_TRIM_3 0 0 Bit29 RXVCO_TRIM_4 0 0 Bit30 RXVCO_TRIM_5 0 0 Bit31 RXVCO_TRIM_6 0 0 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 39 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com SPI2 Register 5 Register address Bit0 Bit1 Bit2 BUF2 BIAS Bit16 Bit17 OUTBUF BIAS Bit18 Bit19 REGISTER 5 40 SPI address Bit3 Bit4 Bit5 RXPLL BIAS Bit6 PRESC BIAS Bit20 Bit21 NAME BIAS SEL Bit22 RSV Bit9 Bit10 RXVCO BIAS Bit11 Bit12 Bit13 BUF1 BIAS Bit14 Bit15 VCO CAL REF Bit23 Bit24 Bit25 RSV Bit26 RSV Bit27 RSV Bit29 RSV Bit30 Bit7 POWER-ON VALUE SUGGESTED VALUE RSV Bit8 RSV Bit28 RSV Bit31 DESCRIPTION Bit0 ADDR_0 1 1 Bit1 ADDR_1 0 0 Register address bits Bit2 ADDR_2 1 1 Bit3 ADDR_3 0 0 Bit4 ADDR_4 1 1 Bit5 RXPLL_BIAS_0 0 0 Bit6 RXPLL_BIAS_1 0 0 Bit7 RXPLL_BIAS_2 1 1 Bit8 RSV 0 0 Reserved SPI address bits RX PLL reference-current control bits. Adjust reference current from 40 µA to 60 µA. Bit9 RSV 0 0 Reserved Bit10 RXVCO_BIAS_0 0 1 Bit11 RXVCO_BIAS_1 0 1 RX VCO bias-control bits. VCO current can be changed from 10 mA (0000) to 25 mA (1111), 1-mA steps. Bit12 RXVCO_BIAS_2 0 1 Bit13 RXVCO_BIAS_3 1 1 Bit14 RXBUF1_BIAS_0 0 0 Bit15 RXBUF1_BIAS_1 1 1 Bit16 RXBUF2_BIAS_0 0 0 Bit17 RXBUF2_BIAS_1 1 1 Bit18 RXBUFOUT_BIAS_0 0 0 Bit19 RXBUFOUT_BIAS_1 1 1 Bit20 RXPRES_BIAS_0 1 0 Bit21 RXPRES_BIAS_1 1 1 Bit22 RXVCO_CAL_IB 0 1 Select bias-current type for VCO calibration circuitry; 1 = PTAT; 0 = constant over temperature Bit23 RXVCO_CAL_REF_0 0 1 Bit24 RXVCO_CAL_REF_1 0 1 RX VCO calibration reference voltage trimming. 000 → 1.175 V 111 → 2.05 V. Suggested value is 1.55 V (011). Bit25 RXVCO_CAL_REF_2 0 0 Bit26 RSV 0 0 Reserved Bit27 RSV 0 0 Reserved Bit28 RSV 0 0 Reserved Bit29 RSV 0 0 Reserved Bit30 RSV 0 0 Reserved Bit31 RSV 0 0 Reserved It sets the PLL buffer 1 bias from 0.8 mA (00) to 2 mA (11), 0.4-mA steps. It sets the PLL buffer 2 bias from 0.8 mA (00) to 2 mA (11), 0.4-mA steps. RXPLL output-buffer reference bias current. 200 µA (00) to 500 µA (11) RXPLL prescaler reference bias current. 200 µA (00) to 500 µA (11) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 TX and RX SPI Registers SPI3 Register 0 This is a read-only register, no write is possible. It contains the internal ADC 8-bit output. Bit0 Bit1 Bit2 Bit3 Bit4 CONV DONE Bit5 RSV Bit16 RSV Bit17 RSV Bit18 RSV Bit19 RSV Bit20 RSV Bit21 Register address REGISTER 0 SPI address NAME OUT RANGE Bit6 Bit22 RSV RSV RSV RSV RSV RSV RSV RSV RSV Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15 Bit23 Bit24 TEMPOUT <7,0> Bit25 Bit26 Bit27 Bit28 Bit29 RSV Bit30 RSV Bit31 POWER-ON VALUE SUGGESTED VALUE DESCRIPTION Bit0 ADDR_0 0 0 Bit1 ADDR_1 0 0 Register address bits Bit2 ADDR_2 0 0 Bit3 ADDR_3 1 1 Bit4 ADDR_4 1 1 Bit5 CONVDONE 0 N/A When 1, ADC conversion done Bit6 OUTRANGE 0 N/A When 1, the analog input voltage to the ADC falls outside the ADC input range of 0.125 V–1.125 V. Bit7 RSV 0 N/A Reserved Bit8 RSV 0 N/A Reserved SPI address bits Bit9 RSV 0 N/A Reserved Bit10 RSV 0 N/A Reserved Bit11 RSV 0 N/A Reserved Bit12 RSV 0 N/A Reserved Bit13 RSV 0 N/A Reserved Bit14 RSV 0 N/A Reserved Bit15 RSV 0 N/A Reserved Bit16 RSV 0 N/A Reserved Bit17 RSV 0 N/A Reserved Bit18 RSV 0 N/A Reserved Bit19 RSV 0 N/A Reserved Bit20 RSV 0 N/A Reserved Bit21 RSV 0 N/A Reserved Bit22 TEMPOUT_0 0 N/A Bit23 TEMPOUT_1 0 N/A ADC 8-bit output Input range 0.125 V to 1.125 V Bit24 TEMPOUT_2 0 N/A Bit25 TEMPOUT_3 0 N/A Bit26 TEMPOUT_4 0 N/A Bit27 TEMPOUT_5 0 N/A Bit28 TEMPOUT_6 0 N/A Bit29 TEMPOUT_7 0 N/A Bit30 RSV 0 N/A Reserved Bit31 RSV 0 N/A Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 41 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com SPI3 Register 1 Register address Bit0 Bit1 SPI address Bit2 TX I and ... correction Bit16 Bit17 Enable loopback Bit18 REGISTER 1 Bit3 Bit4 TX PWD Bit5 Bit6 Loopback Detect PD ref attenuator reset Bit19 Bit20 Bit21 NAME Bit12 TX I and Q phase unbalance correction Bit13 Bit14 Bit15 Bit28 Bit29 TX VGA attenuation control Bit7 Bit8 Bit9 Bit10 Bit11 RSV Bit22 Bit23 POWER-ON VALUE SUGGESTED VALUE Bit24 Bit25 Bit26 Bit27 Bit30 Bit31 DESCRIPTION Bit0 ADDR_0 1 1 Bit1 ADDR_1 0 0 Register address bits Bit2 ADDR_2 0 0 Bit3 ADDR_3 1 1 Bit4 ADDR_4 1 1 Bit5 PWD_TX 1 0 Bit6 TX_ATT_0 0 App. specific Bit7 TX_ATT_1 0 App. specific Bit8 TX_ATT_2 0 App. specific Bit9 TX_ATT_3 1 App. specific Bit10 TX_ATT_4 0 App. specific Bit11 TX_ATT_5 0 App. specific Bit12 TX_ATT_6 0 App. specific Bit13 TXIQ_PHASE_0 0 0 Bit14 TXIQ_PHASE_1 0 0 Bit15 TXIQ_PHASE_2 0 0 Bit16 TXIQ_PHASE_3 0 1 Bit17 TXIQ_PHASE_4 1 0 Bit18 EN_LB 0 0 Enable loopback switch (1 = enable) Bit19 EN_LB_ATT 0 0 Enable 20-dB attenuator in loopback (1 = enable) Bit20 DET_RESET 0 0 Software reset of power-detect alarm output Bit21 PD_REF_BUF 0 0 Power down reference-frequency input buffer (1 = disable) Bit22 RSV 0 0 Reserved Bit23 RSV 0 0 Reserved Bit24 RSV 0 0 Reserved Bit25 RSV 0 0 Reserved Bit26 RSV 0 0 Reserved Bit27 RSV 0 0 Reserved Bit28 RSV 0 0 Reserved Bit29 RSV 0 0 Reserved Bit30 RSV 0 0 Reserved Bit31 RSV 0 0 Reserved SPI address bits TX chain power down (1 = TX chain is off) TX chain variable-attenuator control; 000 0000 = minimum attenuation; 100 0111 = maximum attenuation (35.5 dB); attenuation step = 0.5 dB; TX LO I and Q phase-error correction bits. Suggested value is (0 1000). PWD_TX (bit 5): When 1, the entire TX chain is off. TX_ATT<6,0>: TX chain variable-attenuator control bits, 000 0000 corresponds to minimum attenuation (maximum gain), and 100 0111 sets the attenuator to maximum (minimum gain). The typical attenuation step is 0.5 dB. TXIQ_PHASE<4,0>: TX I-Q phase unbalance correction bits. These bits allow correcting ±2 degrees of phase unbalance between the I and Q paths. Suggested value to program = 0 1000. 42 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 EN_LB (bit 18): When 1, the loopback switch, connecting the TX mixer output to the RX IFVGA3 input, is on. Also, when the switch is enabled, the TX amplifier, RX LNA, IFVGA1, and IFVGA2 are turned off (see the Application Information section). EN_LB_ATT (bit 19): When 1, a 20-dB attenuator in the loopback path is enabled (see the Application Information section). DET_RESET (bit 20): Set this bit to 1 to reset the power-alarm output after it has gone low for a power-alarm alert (see the Application Information section). SPI3 Register 2 Register address Bit0 Bit1 SPI address Bit2 Bit3 Bit4 Bit5 Bit6 Bit17 REGISTER 2 Bit18 Bit19 NAME Bit20 Bit21 Bit7 Filter bypass RX baseband-filter corner frequency Bit16 Bit9 Enable ext SAW Bit10 PWD RX PWD XPIC Bit25 Bit26 RX LNA gain control Bit22 Bit23 Bit8 Baseband 3-dB attenuation Bit24 POWER-ON VALUE SUGGESTED VALUE RX baseband gain Bit11 Bit12 Bit13 Bit14 Bit15 XPIC baseband gain Bit27 Bit28 Bit29 Bit30 Bit31 DESCRIPTION Bit0 ADDR_0 0 0 Bit1 ADDR_1 1 1 Register address bits Bit2 ADDR_2 0 0 Bit3 ADDR_3 1 1 Bit4 ADDR_4 1 1 Bit5 LNA_ATT_0 0 App. specific Bit6 LNA_ATT_1 0 App. specific Bit7 LNA_ATT_2 0 App. specific Bit8 LNA_ATT_3 0 App. specific Bit9 LNA_ATT_4 0 App. specific Bit10 EN_SAW 0 App. specific 1 = signal path through external SAW filter enabled Bit11 RXBB_GAIN_0 0 App. specific Bit12 RXBB_GAIN_1 0 App. specific Bit13 RXBB_GAIN_2 0 App. specific Bit14 RXBB_GAIN_3 0 App. specific RX baseband amplifier gain setting <1 1000> = maximum gain (33 dB); gain step is 1 dB. RXBB_GAIN<4,0> = wanted gain – 9 Example: wanted gain = 22 dB → New gain setting = 22 – 9 = 13 = <0 1101> Bit15 RXBB_GAIN_4 1 App. specific Bit16 RXBB_FREQ_0 0 App. specific Bit17 RXBB_FREQ_1 1 App. specific Bit18 RXBB_FREQ_2 1 App. specific Bit19 RXBB_FREQ_3 1 App. specific Bit20 RXBB_FREQ_4 1 App. specific Bit21 RXBB_FREQ_5 0 App. specific Bit22 RXBB_FREQ_6 1 App. specific Bit23 RXBB_FLT_BYP 0 App. specific RX baseband filter bypass Bit24 RXBB_3dBATT 1 App. specific Enable 3-dB attenuator in the RX BB output buffer (1 = on) Bit25 PWD_RX 0 0 Power down receiver chain Bit26 PWD_XPIC 0 0 Power down XPIC Bit27 XPICBB_GAIN_0 0 App. specific Bit28 XPICBB_GAIN_1 1 App. specific Bit29 XPICBB_GAIN_2 1 App. specific Bit30 XPICBB_GAIN_3 0 App. specific Bit31 XPICBB_GAIN_4 0 App. specific SPI address bits RX LNA attenuation control bits <0 0000> corresponds to 0-dB attenuation (maximum gain). <1 0011> corresponds to 19-dB attenuation (minimum gain). Gain step is 1 dB. RX baseband-filter cutoff-frequency setting Setting of <111 1111> corresponds to minimum cutoff frequency. See the Baseband-Filter Cutoff-Frequency Calibration section. XPIC baseband-amplifier gain setting. <xxx> = maximum gain (xx dB); gain step is 1 dB. XPICBB_GAIN<4,0> = wanted gain – 9 Example: wanted gain = 12 dB → New gain setting = 12 – 9 = 3 = <0 0011> Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 43 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com LNA_ATT<4,0>: RX LNA attenuation setting. The LNA has 19 dB of gain range in 1-dB steps, as shown in Table 6. Table 6. LNA Attenuation and Gain vs LNA_ATT<4,0> LNA_ATT<4,0> LNA ATTENUATION (dB) LNA GAIN (dB) <0 0000> 0 17 <00001> 1 16 <0 0010> 2 15 <0 0011> 3 14 <0 0100> 4 13 <0 0101> 5 12 <0 0110> 6 11 <0 0111> 7 10 <0 1000> 8 9 <0 1001> 9 8 <0 1010> 10 7 <0 1011> 11 6 <0 1100> 12 5 <0 1101> 13 4 <0 1110> 14 3 <0 1111> 15 2 <1 0000> 16 1 <1 0001> 17 0 <1 0010> 18 –1 <1 0011> 19 –2 EN_SAW (bit 10): It enables the external IF path (through the SAW filter) for the signal. When it is 1, the IFVGA1 output buffer (pins 2 and 3) and IFVGA2 input buffer (pins 62 and 63) are on, and the internal connection between the two VGAs is off (see Figure 101). RXBB_GAIN<4,0>: RX baseband-amplifier gain setting. There are 25 gain settings (0 to 24) in 1-dB increments. <1 1000> = maximum gain (33 dB). To set a new gain, the following formula can be used: gain_setting = wanted_gain – 9. Example: Wanted gain = 22 dB → New gain setting = 22 – 9 = 13 = <0 1101> RXBB_FREQ<6,0>: RX baseband-filter cutoff-frequency control. All 1s sets the filter to its minimum pass band; whereas all 0s sets the filter to its maximum cutoff frequency. PWD_RX (bit 25): When it is 1, the entire RX chain is off. PWD_XPIC (bit 26): When it is 1, XPIC (RX chain and output amplifier) is off. XPICBB_GAIN<4,0>: XPIC baseband-amplifier gain setting. There are 13 gain settings (0 to 12) in 1-dB increments; <0 0000> = minimum gain (9 dB) and <0 1100> = maximum gain (21 dB). To set a new gain, the following formula can be used: gain_setting = wanted_gain – 9. Example: Wanted gain = 12 dB → New gain setting = 12 – 9 = 3 = <0 0011> 44 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 SPI3 Register 3 Register address Bit0 TXLO IQ FLIP Bit16 Bit1 SPI address Bit2 TX mixer bias control Bit17 Bit18 REGISTER 3 Bit3 Bit4 Reserved Bit5 Bit6 Bit7 Bit8 TX shut-down Time const Bit9 Bit10 TX input dc-offset control: Q channel Bit19 NAME Bit20 Bit21 Bit22 Bit23 POWER-ON VALUE SUGGESTED VALUE RSV TXBIAS Bit11 Bit12 TX VATT bias control Bit13 Bit14 Bit15 Bit30 EN TXBB bias Bit31 TX input dc-offset control: I channel Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 DESCRIPTION Bit0 ADDR_0 1 1 Bit1 ADDR_1 1 1 Register address bits Bit2 ADDR_2 0 0 Bit3 ADDR_3 1 1 Bit4 ADDR_4 1 1 Bit5 RSV 0 0 Reserved Bit6 RSV 0 0 Reserved Bit7 RSV 0 0 Reserved Bit8 RSV 0 0 Reserved Bit9 PS_TC_0 0 App. specific Bit10 PS_TC_1 0 App. specific Bit11 RSV 1 1 Reserved Bit12 TXBETABIAS 0 0 TXAMP bias control (0 = low; 1 = high) Bit13 TXATTBIAS_0 0 0 TX variable attenuator bias current control Bit14 TXATTBIAS_1 0 0 Bit15 TXATTBIAS_2 1 1 Bit16 TX_IQ_SEL 0 0 Flip TX I with Q side Bit17 TXMIXBIAS_0 0 0 TX mixer bias control Bit18 TXMIXBIAS_1 1 1 Bit19 TXBBQ_0 0 0 Bit20 TXBBQ_1 0 0 Bit21 TXBBQ_2 0 0 Bit22 TXBBQ_3 0 0 Bit23 TXBBQ_4 0 0 Bit24 TXBBQ_5 1 1 Bit25 TXBBI_0 0 0 Bit26 TXBBI_1 0 0 Bit27 TXBBI_2 0 0 Bit28 TXBBI_3 0 0 Bit29 TXBBI_4 0 0 Bit30 TXBBI_5 1 1 Bit31 EN_TXCM 0 0 SPI address bits TX power-shutdown time constant: 00 = 28 µs; 01 = 42 µs; 10 = 57 µs; 11 = 75 µs TX input baseband dc offset control: Q channel See the application note (SLWU064) for optimum dc-offset control setting. TX input baseband dc-offset control: I channel See the application note (SLWU064) for optimum dc-offset control setting. Enable external TX baseband common-mode generation (0 = internal common-mode voltage generation; 1 = external common-mode voltage generation) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 45 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com PS_TC<1,0>: TX power-shutdown time constant. It controls how fast the TX output power is ramped down after TXPWD (pin 17) is set high. The typical shutdown time (output level attenuated by 30 dB) is shown in Table 7. Table 7. TX Power Shutdown Time vs PS_TC<1,0> PS_TC POWER DOWN 00 28 µs 01 42 µs 10 57 µs 11 75 µs TXBBQ<4,0> and TXBBI<4,0>: TX input baseband dc-offset control bits. Suggested value is <1 0000>, that corresponds to 0-V applied offset. EN_TXCM: When 1, the TX baseband input common mode is generated internally. SPI3 Register 4 Register address Bit0 Bit1 .. Bit2 Bit3 Bit4 PWD TX chain blocks Bit16 Bit17 REGISTER 4 46 EN TEMP XPIC AMP ADC cal bias sel Bit5 Bit6 SPI address Bit18 Bit19 Bit20 NAME PWD T_ADC Bit21 PWD T_SENS Bit22 XPIC AMP bias control Bit7 Bit8 XPIC AMP gain control Bit9 Bit10 Bit11 RX VGA bias control .. Bit12 Bit13 Bit14 PWD RX and XPIC blocks Bit23 POWER-ON VALUE SUGGESTED VALUE Bit24 Bit25 Bit26 Bit27 Bit28 Bit15 RSV Bit29 Bit30 Bit31 DESCRIPTION Bit0 ADDR_0 0 0 Register address bits Bit1 ADDR_1 0 0 Bit2 ADDR_2 1 1 Bit3 ADDR_3 1 1 Bit4 ADDR_4 1 1 Bit5 EN_TADC_CAL 0 0 Enable temperature-sensor ADC calibration Bit6 XPICAMPBIAS_SEL 0 0 Select bias type (1 = PTAT; 0 = CONST) Bit7 XPICAMPBIAS_0 0 0 XPIC output-amplifier bias control Bit8 XPICAMPBIAS_1 1 1 Bit9 XPICAMPGAIN_0 0 0 Bit10 XPICAMPGAIN_1 0 1 Bit11 XPICAMPGAIN_2 1 0 Bit12 RXVGABIAS_0 1 1 Bit13 RXVGABIAS_1 0 1 Bit14 RXVGABIAS_2 0 1 Bit15 RXVGABIAS_3 1 0 Bit16 RXVGABIAS_4 0 0 Bit17 PWD_TXMIX 0 0 Power down TX modulator (1 = disable) Bit18 PWD_TXATT 0 0 Power down TX variable attenuator (1 = disable) Bit19 PWD_TXPREAMP 0 0 Power down TX amplifier driver (1 = disable) Bit20 PWD_TXAMP 0 0 Power down TX output amplifier (1 = disable) Bit21 PWD_TEMPADC 1 1 Power down TEMP sensor ADC (1 = disable) Bit22 PWD_TEMPSENS 1 1 Power down TEMP sensor (1 = disable) Bit23 PWD_DCOFF 0 0 Power down RX dc offset loop (1 = disable) Bit24 PWD_XPICAMP 0 0 Power down XPIC output amplifier (1 = disable) Bit25 PWD_LNA 0 0 Power down RX LNA (1 = disable) Bit26 PWD_IFVGA1 0 0 Power down RX IFVGA1 (1 = disable) Bit27 PWD_IFVGA2 0 0 Power down RX IFVGA2 (1 = disable) SPI address bits XPIC output-amplifier gain adjustment RX VGAs bias control Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 REGISTER 4 NAME POWER-ON VALUE SUGGESTED VALUE DESCRIPTION Bit28 PWD_IFVGA3 0 0 Power down RX IFVGA3 (1 = disable) Bit29 PWD_RXMIX 0 0 Power down RX demodulator (1 = disable) Bit30 PWD_RXBB 0 0 Power down RX baseband (1 = disable) Bit31 RSV 0 0 Reserved EN_TADC_CAL (bit 5): When 1, TEMP sensor ADC autocalibration starts. XPICAMPBIAS_SEL (bit 6): It selects the XPIC output amplifier biasing type. When 1, a PTAT (proportional to temperature) dc current is selected. If it is 0, then a constant current over temperature is chosen. SPI3 Register 5 Register address Bit0 Bit1 ... RSV Bit16 Bit17 SPI address Bit2 Bit3 ENXPIC CAL Bit18 REGISTER 5 Bit4 ENBB AUTOCAL Bit5 XPIC MIX BIAS Bit19 Bit20 NAME RXMIX BIAS Bit6 Bit7 XPIC IMIX VCM Bit21 Bit22 RX IMIX VCM Bit8 XPIC QMIX VCM Bit23 Bit24 POWER-ON VALUE SUGGESTED VALUE Bit9 RXQMIX VCM Bit10 XPIC dc offset resolution Bit25 Bit26 Bit11 DC offset resolution Bit12 Bit13 XPIC dc offset CLK Bit27 Bit28 Bit29 DC offset CLK Bit14 RSV Bit30 Bit15 PWD dc OFF Bit31 DESCRIPTION Bit0 ADDR_0 1 1 Bit1 ADDR_1 0 0 Register address bits Bit2 ADDR_2 1 1 Bit3 ADDR_3 1 1 Bit4 ADDR_4 1 1 Bit5 EN_BB_AUTOCAL 0 0 Enable RX baseband dc-offset autocalibration Bit6 RXMIX_BIAS_0 1 1 RX demodulator dc current control Bit7 RXMIX_BIAS_1 0 0 Bit8 RXIMIX_VCM_0 0 0 SPI address bits RX I mixer bias control Bit9 RXIMIX_VCM_1 1 1 Bit10 RXQMIX_VCM_0 0 0 Bit11 RXQMIX_VCM_1 1 1 Bit12 DCOFF_BIAS_0 1 1 Bit13 DCOFF_BIAS_1 1 1 Bit14 DCOFF_CLK_0 0 0 Bit15 DCOFF_CLK_1 0 0 Bit16 DCOFF_CLK_2 1 1 Bit17 RSV 0 0 Reserved Bit18 EN_XPIC_AUTOCAL 0 0 Enable XPIC baseband dc-offset autocalibration Bit19 XMIX_BIAS_0 1 0 XPIC demodulator dc-current control Bit20 XMIX_BIAS_1 0 1 Bit21 XIMIX_VCM_0 0 0 Bit22 XIMIX_VCM_1 1 1 Bit23 XQMIX_VCM_0 0 0 Bit24 XQMIX_VCM_1 1 1 Bit25 XPICDCOFF_BIAS_0 1 1 Bit26 XPICDCOFF_BIAS_1 1 1 Bit27 XDCOFF_CLK_0 0 0 Bit28 XDCOFF_CLK_1 0 0 Bit29 XDCOFF_CLK_2 1 1 Bit30 RSV 1 1 RX Q mixer bias control Set RX dc-offset calibration-loop resolution RX dc offset-loop clock-speed control XPIC I mixer bias control XPIC Q mixer bias control Set XPIC dc-offset calibration-loop resolution XPIC dc offset-loop clock-speed control Reserved Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 47 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com REGISTER 5 Bit31 NAME POWER-ON VALUE SUGGESTED VALUE 0 0 PWD_XPICDCOFF DESCRIPTION Power down XPIC dc-offset loop (1 = disable) EN_BB_AUTOCAL (bit5): When 1, the RX baseband dc-offset automatic calibration starts. At the end of the calibration, the bit is reset to 0. DCOFF_BIAS<2,0>: These bits control the maximum output dc voltage of the dc-offset correction DAC used in the RX chain. DCOFF_CLK<2,0>: It sets the frequency-divider ratio that creates the RX dc-offset correction-loop clock from the clock divider. EN_BB_CAL (bit17): When 1, the RX baseband dc-offset loop is enabled. EN_XPIC_AUTOCAL (bit18): When 1, the XPIC baseband dc-offset automatic calibration starts. At the end of the calibration, the bit is reset to 0. XPICDCOFF_BIAS<2,0>: These bits control the maximum output dc voltage of the dc-offset correction DAC used in the XPIC chain. XDCOFF_CLK<2,0>: It sets the frequency-divider ratio that creates the XPIC dc-offset correction-loop clock from the clock divider. SPI3 Register 6 Register address Bit0 Bit1 SPI address Bit2 IFVGA2 gain-range control Bit16 Bit17 Bit18 REGISTER 6 48 Bit3 IFVGA3 gain-range control Bit4 Bit5 Bit6 Bit7 IFVGA2 min. gain Bit19 NAME Bit20 Bit21 Bit8 IFVGA3 min. gain Bit9 Bit10 Bit11 Bit12 IFVGA1 gain-range control Bit22 Bit23 POWER-ON VALUE SUGGESTED VALUE Bit0 ADDR_0 0 0 Bit1 ADDR_1 1 1 Bit2 ADDR_2 1 1 Bit3 ADDR_3 1 1 Bit4 ADDR_4 1 1 Bit5 IFVGA3_RANGE_0 0 0 Bit6 IFVGA3_RANGE_1 0 1 Bit7 IFVGA3_RANGE_2 1 0 Bit8 IFVGA3_RANGE_3 1 1 Bit9 IFVGA3_RANGE_4 1 0 Bit10 IFVGA3_ MINGAIN_0 0 0 Bit11 IFVGA3_MINGAIN_1 1 1 Bit12 IFVGA3_MINGAIN_2 0 0 Bit13 IFVGA3_MINGAIN_3 0 0 Bit14 IFVGA2_RANGE_0 0 1 Bit15 IFVGA2_RANGE_1 0 0 Bit16 IFVGA2_RANGE_2 1 0 Bit17 IFVGA2_RANGE_3 1 1 Bit18 IFVGA2_RANGE_4 1 0 Bit19 IFVGA2_ MINGAIN_0 0 0 Bit20 IFVGA2_MINGAIN_1 1 1 Bit21 IFVGA2_MINGAIN_2 0 0 Bit22 IFVGA2_MINGAIN_3 0 0 Bit24 Bit25 Bit26 Bit13 IFVGA2 gainrange control Bit14 Bit15 IFVGA1 min. gain Bit27 Bit28 Bit29 Bit30 Bit31 DESCRIPTION Register address bits SPI address bits IFVGA3 gain-range control IFVGA3 minimum-gain control IFVGA2 gain-range control IFVGA2 minimum-gain control Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 REGISTER 6 NAME POWER-ON VALUE SUGGESTED VALUE Bit23 IFVGA1_RANGE_0 0 0 Bit24 IFVGA1_RANGE_1 0 0 Bit25 IFVGA1_RANGE_2 1 1 Bit26 IFVGA1_RANGE_3 1 1 Bit27 IFVGA1_RANGE_4 1 1 Bit28 IFVGA1_ MINGAIN_0 0 0 Bit29 IFVGA1_MINGAIN_1 1 0 Bit30 IFVGA1_MINGAIN_2 0 1 Bit31 IFVGA1_MINGAIN_3 0 0 DESCRIPTION IFVGA1 gain-range control IFVGA1 minimum-gain control Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 49 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com SPI3 Register 7 Register address Bit0 Bit1 Bit2 SPI address Bit3 Bit4 RX BB Q dc offset DAC Bit16 Bit17 Bit18 REGISTER 7 Bit19 NAME Bit20 RX BB I dc offset DAC Bit7 Bit8 Bit9 Bit10 Bit5 Bit6 CAL SEL Bit21 PWD DET DELAY Bit22 Bit23 POWER-ON VALUE SUGGESTED VALUE PWR DETECTOR THRESHOLD Bit24 Bit25 Bit26 RX BB Q dc offset DAC Bit13 Bit14 Bit15 Bit11 Bit12 RSV RSV RSV RSV RSV Bit27 Bit28 Bit29 Bit30 Bit31 DESCRIPTION Bit0 ADDR_0 1 1 Register address bits Bit1 ADDR_1 1 1 Bit2 ADDR_2 1 1 Bit3 ADDR_3 1 1 Bit4 ADDR_4 1 1 Bit5 RXBBI_DCOFF_0 0 0 Bit6 RXBBI_DCOFF_1 0 0 Bit7 RXBBI_DCOFF_2 0 0 Bit8 RXBBI_DCOFF_3 0 0 Bit9 RXBBI_DCOFF_4 0 0 Bit10 RXBBI_DCOFF_5 0 0 Bit11 RXBBI_DCOFF_6 0 0 Bit12 RXBBI_DCOFF_7 1 1 Bit13 RXBBQ_DCOFF_0 0 0 Bit14 RXBBQ_DCOFF_1 0 0 Bit15 RXBBQ_DCOFF_2 0 0 Bit16 RXBBQ_DCOFF_3 0 0 Bit17 RXBBQ_DCOFF_4 0 0 Bit18 RXBBQ_DCOFF_5 0 0 Bit19 RXBBQ_DCOFF_6 0 0 Bit20 RXBBQ_DCOFF_7 1 1 Bit21 RXBB_CALSELECT 1 1 Bit22 PWRDET_DEL_0 1 App. Specific Bit23 PWRDET_DEL_1 0 App. Specific Bit25 PWRDET_0 0 0 Bit25 PWRDET_1 0 1 Bit26 PWRDET_2 0 0 Bit27 RSV 0 0 Reserved Bit28 RSV 0 0 Reserved Bit29 RSV 0 0 Reserved Bit30 RSV 0 0 Reserved Bit31 RSV 0 0 Reserved SPI address bits RX baseband I-side dc-offset control DAC RX baseband Q-side dc-offset control DAC RX baseband dc-offset calibration select (1 = automatic; 0 = manual) Power-detector-response delay control TX power-detector threshold setting RXBBI_DCOFF<7,0> and RXBBI_DCOFF<7,0>: TRF2443 internal auxiliary DAC bits to be set during the manual RX-chain baseband dc-offset calibration (see the Application Information section). RXBB_CALSELECT (bit 21): Selects the dc-offset calibration mode; when 0, the manual mode is selected. PWRDET_DEL<1,0>: TX power-detector response-time delay (see Table 8). 50 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Table 8. TX Power-Detector Response-Time Delay vs PWRDET_DEL<1,0> PWRDET_DEL DET DELAY 00 5 µs 01 10 µs 10 20 µs 11 40 µs PWRDET<2,0>: TX power-detector threshold-level control READBACK MODE The TRF2443 implements the capability to read back the content of the serial programming-interface registers. Each readback is composed of two phases: 1. Writing a request to read back data 2. Reading the actual data of the internal registers (see timing diagram in Figure 100). During the writing phase, a command is sent to the TRF2443 to set it in readback mode and to specify which register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred to the RDBKSPI pin and can be read at the following falling edge (LSB first). The first clock after the LE goes high (end of writing cycle) is idle, and the following 32 clock pulses transfer the internal register content to the RDBKSPI pin. REGISTER WRITE tsu1 CLOCK t(CLK) t(CL) t(CH) 32nd Writes clock pulse DB0 (LSB) Address Bit0 DATA DB1 Address Bit1 DB2 Address Bit2 DB3 Address Bit3 DB29 DB31 (MSB) DB30 tsu3 tsu2 tw LATCH ENABLE CLOCK READBACK th 1st Write clock pulse LATCH ENABLE 32nd Write clock pulse tsu2 1st Read clock pulse 2nd Read clock pulse 33rd Read clock pulse 32nd Read clock pulse tw “End of Write Cycle” pulse td ReadBack Data Bit0 READBACK DATA Read Back Data Bit1 Read Back Data Bit29 ReadBack Data Bit30 ReadBack Data Bit31 Figure 100. SPI Readback Timing Diagram Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 51 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com Table 9. SPI Readback Timing PARAMETER MIN TYP MAX UNITS th Hold time, data to clock 20 ns tSU1 Setup time, data to clock 20 ns t(CL) Clock low duration 20 ns t(CH) Clock high duration 20 ns tSU2 Setup time, clock to enable 20 ns tW Enable time 50 ns t(CLK) Clock period 50 ns tSU3 Setup time, latch to data 70 ns td Delay time, clock to readback-data output 10 ns COMMENTS Equals clock period Readback From the Internal Register Banks The TX PLL (SPI-1) and RX PLL (SPI-2) register banks each contain six registers: register 0 (000) through register 5 (101). Register 0 (000) is used only for the readback operation, whereas registers 1 through 5 are the actual PLL control registers. In the case of the TX PLL (SPI-1) and RX PLL (SPI-2) register banks, register 0 contains no information. Therefore, it is not possible to read back register 0 from these register banks. The TX-RX (SPI-3) register bank contains eight registers: register 0 (000) through register 7 (111). Register 0 (000) is used only for the readback operation, whereas registers 1 through 7 are the actual TX and RX control registers. In the case of the TX-RX register bank (SPI-3), register 0 is used to store some TRF2443 internal data. Therefore, it is possible to read back register 0 from this register bank, as it contains this data. To read back a register from any of these register banks, register 0 of the register bank which contains the register to be read must be programmed with a specific command that sets the TRF2443 in the readback mode and specifies the register to be read: • Set B<31> to 1 to put the TRF2443 in readback mode. • Set B<30,28> equal to the address of the register to be read (001 to 101 in the case of TX PLL/RX PLL; 000 to 111 in the case of TX-RX SPI). 52 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Table 10. SPI Register Banks Readback Setup BITS Address bits Data field NAME SUGGESTED VALUE B0 ADDR <0> 0 B1 ADDR <1> 0 B2 ADDR <2> 0 B3 ADDR <3> X B4 ADDR <4> X B5 N/C 0 B6 N/C 0 B7 N/C 0 B8 N/C 0 B9 N/C 0 B10 N/C 0 B11 N/C 0 B12 N/C 0 B13 N/C 0 B14 N/C 0 B15 N/C 0 B16 N/C 0 B17 N/C 0 B19 N/C 0 B20 N/C 0 B21 N/C 0 B22 N/C 0 B23 N/C 0 B24 N/C 0 B25 N/C 0 B26 N/C 0 B27 N/C 0 B28 RB_REG<0> X B29 RB_REG<1> X B30 RB_REG<2> X B31 RB_Enable 1 DESCRIPTION Register 0 to be programmed to set TRF2443 in readback mode Register bank: B<4,3> from which a particular register is to be read back TX PLL (01); RX PLL (10); TX-RX SPI (11) Address of the register within the bank that is being read back; Reg 1(001) to Reg 5(101) in TX PLL/RX PLL; Reg 0(000) to Reg 7(111) in TX-RX SPI 1 → Put the device in readback mode Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 53 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TRF2443 DESCRIPTION RECEIVER DESCRIPTION IF SAW RX_AGC IF_OUT IF_IN BB AMP/FLT AGC CNTL RX VGA RX_BBI LNA 0/90 RX_IN IFVGA1 IFVGA2 IFVGA3 RX _BBQ From SPI from RXPLL From SPI Figure 101. Receiver Chain Block Diagram The TRF2443 features a highly linear low-noise receiver chain with over 60 dB of analog-controlled gain range and more than 40 dB of gain range programmable via the serial programming interface (SPI) in 1-dB steps. Moreover, the TRF2443 gives the flexibility to add an external IF filter to further remove unwanted signals. Such an external filter can be bypassed using an internal path that can be enabled via SPI. LNA The first block of the receiver chain is a low-noise, highly linear IF amplifier (LNA). Its input is differential and internally matched to 50 Ω. To drive the TRF2443 RX input via a single0-ended source, a 1:1 balun is required at the LNA input (see Application Schematic section). The TRF2443 LNA attenuation is programmable via the serial programming interface (SPI) from 0 dB to –19 dB, corresponding to an LNA gain of 17 dB to –2 dB (1-dB steps). LNA_ATT<4,0> in SPI-3, register 2, B<9,5> are the LNA attenuation controlling bits. To program the amplifier to the maximum gain, set the attenuation bits to 0 (LNA_ATT<4,0> = <0 0000>); whereas minimum gain corresponds to LNA_ATT<4,0> = <1 0011>. VGA The LNA is followed by three analog-controlled VGAs that provide more than 60 dB of gain range. The IFVGA1 output and IFVGA2 input can be connected externally (pins IFOUT and IFIN) through an external IF filter. The IFVGA1 output buffer requires two pullup inductors to be connected from the IFOUTP/N pins to Vcc (see Application Schematic section). The IFVGA2 input (pins IFINN/P) is high-impedance. A 50-Ω external resistor is required across the IFINN and IFINP pins to provide a matching load to the IF filter output. An internal switch gives the flexibility to bypass the external filter. The internal bypass switch is controlled via the serial programming interface through bit EN_SAW (SPI-3, register 2, B<10>). By programming EN_SAW to 1, the external path is selected, whereas a 0 engages the internal bypass switch. The VGA gain is controlled by the dc voltage applied to the RXAGC pin. By varying the input dc voltage from 0 V to 2 V, the VGA total gain goes from minimum to maximum. The gain control is linear in dB, with a typical slope around 51 dB/V. The RXAGC input provides a high input impedance, equivalent to a 100-kΩ resistance in series with a 4-pF capacitance. Demodulator The IFVGA3 drives the demodulator, which downconverts the IF input signal directly to baseband in phase and quadrature. The demodulator block includes the local oscillator in-phase and quadrature-generation circuitry, followed by the LO buffer. The LO chain also includes a frequency divider that can be programmed to divide by 8 or 16. The frequency divider generates the RX LO from the RX VCO. By selecting a division ratio of 16, the RX LO can be set to 140 MHz (see the Programming the TRF2443 Synthesizers section). 54 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Baseband Section The TRF2443 baseband section integrates a programmable gain amplifier (PGA) and programmable low-pass filter. The baseband PGA minimum gain is 9 dB, and the maximum gain is 33 dB. The PGA can be programmed in 25 gain settings (0 to 24) in 1-dB increments. Its gain can be changed by the RX_BBGAIN<4,0> bits (SPI-3, register 2, B<15,11> according to the following formula: gain_setting = wanted_gain – 9. Example: Wanted gain = 22 dB → New gain setting = 22 – 9 = 13 = <0 1101> The TRF2443 baseband low-pass filter cutoff frequency can be programmed from 2 MHz to 11 MHz by setting appropriately the cutoff-frequency control bits RXBB_FREQ<6,0> (SPI-3, register 2, B<22,16>). RXBB_FREQ<6,0> = <111 1111> corresponds to the minimum corner frequency. The baseband output buffers (ADC drivers) are designed to drive directly an analog-to-digital converter (ADC), either dc- or ac-coupled. The output common mode of the ADC drivers is set externally via the RXBBCM pin (pin 40). When the TRF2443 is dc-connected to the ADC, the same dc common mode for both the ADC and the TRF2443 baseband output can be used. TRANSMITTER DESCRIPTION VCC From SPI TX_OUT From TX PLL To feedback switch TXI_IN 6 0/90 TXAMP VCC ATT Level Detect TXQ_IN TX_PWD Figure 102. Transmitter Chain Block Diagram The transmitter chain integrates an IQ modulator followed by a variable attenuator and the final transmitter amplification stage. The last two blocks provide over 35 dB of gain range. A power-alarm circuit monitors the level at the modulator output, and its digital output goes low if the signal level falls below the user-specified threshold level relative to the expected level. TX IQ Modulator The first block of the transmitter chain is the IQ modulator, which upconverts the incoming in-phase and quadrature signals to the TX IF frequency. The TRF2443 can be either ac- or dc-coupled to the digital-to-analog converter (DAC). If a dc-coupled configuration is selected, then the modulator-input dc-common mode must be set externally to the appropriate level of 1.4 V and the common-mode bias generation must be set to external mode via the SPI by setting EN_TXCM (SPI-3, register 3, B<31>) to 1. If an ac-coupled configuration is selected, then internal common-mode generation mode must be enabled via the SPI by setting EN_TXCM (SPI-3, register 3, B<31>) to 0. When internal biasing is enabled, it is possible to apply a dc offset to either the I or Q side of the IQ modulator using the integrated dc DAC, accessible via the SPI (TXBBI<5,0>, SPI-3, register 3, B<30,25>; TXBBQ<5,0>, SPI-3, register 3, B<24,19>). An external 100 Ω differential resistor is required between the TX baseband input pins (TXBBIP and TXBBIN, pins 22 and 21, and TXBBQP and TXBBQN, pins 20 and 19) if utilizing the dc DAC. The optimum value of the dc DAC, which minimizes carrier leakage, can be read from the EEPROM within the TRF2443. See the application note (SLWU064) on how to access EEPROM information. The mixers of the IQ modulator use an external load. The collectors of the output transistors are connected to the pins MIXINDN and MIXINDP (pins 2 and 3). On the board, a pullup inductor to Vcc must be connected to each of those pins, as well as a shunt resistor between the pins (see the Application Schematic section). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 55 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TX Variable Attenuator and Output Amplifier The IQ modulator drives a variable attenuator. This block provides 5.5 dB of total attenuation range in 0.5-dB steps. The output amplifier integrates five attenuation steps of 6 dB each for total of 30 dB. The output amplifier in combination with the variable attenuator provides over 35.5 dB of monotonic output power control (0.5-dB steps). The TRF2443 TX gain can be controlled via SPI TX_ATT<6,0> (SPI-3, register 1, B<12,6>). TX_ATT<6,0> sets the amount of attenuation in the variable attenuator and output amplifier. • TX_ATT<6,0> = 000 0000 → 0 dB attenuation (maximum gain) • TX_ATT<6,0> = 100 0111 → maximum attenuation (minimum gain) The TX output amplifier uses an output open-collector arrangement. Therefore, each of the two output pins (TXOUTP and TXOUTN, pins 77 and 78) requires a pullup inductor connected to the power supply (see the Application Schematic section). The TRF2443 TX output impedance is set typically to 200 Ω differential. A 4:1 impedance-ratio balun is needed to transform the impedance to 50 Ω single-ended. SYNTHESIZERS DESCRIPTION RXPLL_CP REF_CLK TXVCO Tune RXVCO Tune CP RXVCO PFD R1 R2 1/N1 PFD CP TXVCO 1/N2 From SPI RXIFLO_I RXIFLO_Q Div-8/ 16 Div-8/ 16 TXIFLO_I TXIFLO_Q Figure 103. RX and TX PLL Block Diagram The TRF2443 integrates two complete integer synthesizers for the receiver and transmitter chains. The RXVCO operates at 16 times the typical RX input frequency, and the TXVCO operates at 8 times the typical TX output frequency. Each synthesizer is composed of: • High-frequency VCO (around 2720 MHz for the TX VCO and 2240 MHz for the RX VCO) • N-divider (driven by the high-frequency VCO) done by an 8/9 prescaler followed by an A-B counter that drives the phase-frequency detector • Phase-frequency detector (PFD) (driven by the N-divider) that compares the VCO divided by N to the reference clock divided by R signals • Charge pump (driven by the PFD), which creates up and down current pulses based on the incoming signals from the PFD. Its output is filtered and transformed to voltage by the external loop filter and applied to the VCO input control voltage. • An external reference clock must be applied to REFIN (pin 16). The incoming signal is buffered and goes through a programmable divider (R-divider). The VCO output is then routed through a programmable divider by 8 or 16 to create the TX and RX LO signals. The TRF2443 features a lock-detect output pin (LOCKDET, pin 5). This is a digital output that is high when both RX and TX synthesizers are locked, and it is low if one or both synthesizers are unlocked (or lose lock). Programming the TRF2443 Synthesizers Both TRF2443 synthesizers are integer PLLs. The VCO output frequency is defined by: fVCO = k × N / R × fRef 56 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 where: N: division ratio of the N-divider R: division ratio of the R-divider K: multiplier factor; k = 1 for RX synthesizer; k = 2 for the TX synthesizer. Knowing the fRef, it is possible to calculate the required N and R values to synthesize any output frequency within the VCO frequency range. Example Suppose we want to synthesize the TX LO to be 340 MHz and the input reference frequency is 20 MHz. LOTX = 340 MHz fRef = 20 MHz fVCO-TX = 2720 MHz (8 × LOTX) Because fVCO-TX is an integer multiple of fRef, we can set the R divider to 1. R=1 N = fVCO-TX / (k × fRef) × R = 68 Then the TRF2443 SPI can be programmed as follows: R = 1 → TXRDIV<13,0> = <00 0000 0000 0001> (SPI-1, register 1, B<18,5>) N = 68 → TX_NINT<15,0> = <0000 0000 0100 0100> (SPI-1, register 2, B<20,5>) LO divider set to 8 → TXDIV_SEL = 1 (SPI-1, register 2, B<26>). Calibrating TRF2443 TX and RX VCO Both TRF2443 VCOs are based on a cross-coupled LC tank architecture. The tank is composed of a high-Q integrated spiral inductor, a varactor, and an array of capacitors which is digitally controlled. To tune the VCO to a certain frequency, the correct configuration for the array of capacitors is required. The capacitor array can be configured automatically or manually. The calibration mode is controlled by TXCAL_SEL (SPI-1, register 2, B<30>) for the TX VCO and by RXCAL_SEL (SPI-2, register 2, B<30>) for the RX VCO. Setting these two bits to 1 selects the automatic calibration mode. The calibration starts when EN_TXCAL (SPI-1, register 2, B<31>) and/or EN_RXCAL (SPI-2, register 2, B<31>) are toggled to 1. The calibration speed is controlled by a clock derived from the reference clock through a frequency divider, whose division ratio can be programmed with TXCAL_CLK<2,0> (SPI-1, register 2, B<29,27>) and RXCAL_CLK<2,0> (SPI-2, register 2, B<29,27>). The suggested value of TXCAL_CLK<2,0> and RXCAL_CLK<2,0> = <101>, which corresponds to a divider value of 1024 and a clock speed of 20 MHz. The manual-mode calibration, used mainly for debugging purposes, is activated by setting TXCAL_SEL (SPI-1, register 2, B<30>) and or RXCAL_SEL (SPI-2, register 2, B<30>) to 0. In this mode, the capacitor array setting is controlled by TXVCO_TRIM<5,0> (SPI-1, register 4, B<31,26>) for the TX VCO and RXVCO_TRIM<6,0> (SPI-2, register 4, B<31,26>) for the RX VCO. Synthesizer Lock-Detector Indicator The TRF2443 integrates a PLL lock-detector circuit. When both the TX and RX synthesizers are locked, LOCKDET (pin 5) goes high. The settling time of the lock-detector circuitry can be set externally by sizing the capacitor placed between LDCAP (pin 38) and ground. The size of capacitor on this pin sets the time constant Tld of the lock detect circuit. If either the TX PLL or the RX PLL lock-detect circuit indicates a loss of lock, the LOCKDET pin goes low immediately. If the lock-detect circuits of the TX and the RX PLLs have not indicated a loss of lock for a time > Tld, the LOCKDET pin goes high. For a 20-MHz PFD frequency, a 1-nF capacitor is suggested, corresponding to a 10-µs deglitch time. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 57 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com XPIC DESCRIPTION XPIC AGC Demodulator XPIC_IN BB AMP XPIC_BBI 0/90 VGA XPIC_BBQ VCC from RXPLL From demodulator input XPIC_AMP XPIC OUT VCC Figure 104. XPIC Block Diagram XPIC Output Amplifier The XPIC output amplifier transmits the signal taken at the receiver demodulator input. The XPIC output amplifier uses an output open-collector arrangement. Therefore, each of the output pins (XPICOUTN and XPICOUTP, pins 54 and 55) requires a pullup inductor to the power supply (see the Application Schematic section). The TRF2443 XPIC output impedance is set to 75 Ω differential with an internal resistor. A 1:1 impedance-ratio balun is needed to transform the impedance to 75 Ω single-ended. XPIC Receiver Chain The XPIC receiver section downconverts the input signal to baseband I and Q. It includes an IF VGA followed by a demodulator and a baseband amplifier. The XPIC receiver input is differential, but it can be converted to a single-ended 75-Ω input through an external 1:1 balun. The XPIC input impedance is set to 75 Ω with an internal resistor. 58 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 APPLICATION INFORMATION POWER SUPPLY RAMP-UP PROCEDURE In order to assure the correct functionality of the TRF2443 internal registers, it is important to ramp up the VCCREF power supply at the same time as or before VCCSPI. If VCCREF is powered before VCCSPI, the EEPROM contents could potentially be erased. TRF2443 SPI INITIALIZATION SEQUENCE In order to ensure proper operation of the TRF2443, it is important to program the IC through the SPI in a particular manner. How to do this is the scope of this section. The chip initialization can be broken down into four parts: • Acquire information from EEPROM needed for subsequent initializations • Initialize receiver PLL (SPI-2) • Initialize transmitter PLL (SPI-1) • Initialize receiver and transmitter (SPI-3) EEPROM There is information stored in the EEPROM that is available to the user to program the TRF2443 into an optimal state. If desired, the user must first read this information from the EEPROM and make it available for subsequent SPI programming. See the application note (SLWU064) on how to access EEPROM information. Initialize RX PLL (SPI-2) Write registers 4, 5, 1, and 2 of SPI-2 in this order. Register 2 is the last register to be written because register 2 starts the RX VCO calibration and PLL lock. The time required for this calibration to complete is 12 cycles of the calibration frequency. The calibration frequency is the external reference frequency divided by the RX_CAL CLK<2,0> (SPI-2, register 2, B<29,27>) setting. With a 20-MHz external reference and RX_CAL CLK<2,0> = <111> corresponding to a divider ratio of 16,684, this calibration frequency is 1.2 kHz. Therefore, the calibration requires 10 ms. The user should set the external reference frequency and the RX_CAL CLK<2,0> setting to ensure that the calibration frequency does not exceed 800 kHz. Subsequent register writes to SPI-1 and SPI-3 do not affect the RX VCO calibration and can begin immediately on the next SPI clock cycle. Initialize TX PLL (SPI-1) Write registers 4, 5, 1, and 2 of SPI-1 in this order. Register 2 is the last register to be written because register 2 starts the TX VCO calibration and PLL lock. The time required for this calibration to complete is 11 cycles of the calibration frequency. The calibration frequency is the external reference frequency divided by the TX_CAL CLK<2,0> (SPI-1, register 2, B<29,27>) setting. With a 20-MHz external reference and TX_CAL CLK<2,0> = <111>, corresponding to a divider ratio of 16,684, this calibration frequency is 1.2 kHz. Therefore, this calibration requires 9.2 ms. The user should set the external reference frequency and the TX_CAL CLK<2,0> setting to ensure that the calibration frequency does not exceed 800 kHz. Subsequent register writes to SPI-3 do not affect the TX VCO calibration and can begin immediately on the next SPI clock cycle. Initialize RX and TX Write registers 6, 3, 7, 4, 2, 5, 1, and 1 again of SPI-3 in this order. Register 5 starts the RX dc offset calibration. Register 1 follows register 5 and can be written immediately on the next SPI clock cycle, because its content does not affect the RX dc-offset calibration. Register 1 is written last because it contains the PWD_TX bit (SPI-3, register 1, B<5>). This ensures that all the other parameters of the TX are set up correctly before the transmitter is enabled. However, the power alarm circuitry (See the Power Alarm Detector section) is reset from register 1 by DET_RESET (SPI-3, register 1, B<20>). Because the TX is enabled at the same time the power alarm circuitry is reset, there exists a race condition which could cause the power alarm to be in either state. To ensure that the power alarm is properly armed, the DET_RESET (SPI-3, register 1, B<20>) bit should be resent after the transmitter has been enabled. To do this, register 1 is written a second time. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 59 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com POWER ALARM DETECTOR The TRF2443 integrates power-alarm indicator circuitry that allows monitoring of the TX output power and issuing an alarm (PWRDET pin LOW) if the output power goes below a threshold level. The power-alarm indicator includes a peak detector, a comparator with a programmable threshold level, and power-alarm logic (see Figure 105). TX I / Q Modulator TX Attn + Amp BBI TX OUT BBQ V1 TX LO Peak Detector Programmable Threshold Power Alarm Logic TX Power Alarm Software Reset Figure 105. Block Diagram of the TX Power-Alarm Implementation The peak detector measures the signal power level at the modulator output and provides a dc level proportional to the measured level. The peak-detector output is compared to a programmable reference threshold and the comparator output (V1) goes HIGH if the measured level is below the threshold level (see Figure 106). Comparator Output VCC 0 Poutnorm –X dB Poutnorm TX Mixer Output Figure 106. Expected Output of the Comparator 60 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 The power-alarm logic includes a time counter which is used to measure how long the IQ modulator output power stays below the user-specified threshold level. The counter is enabled when the comparator output (V1) is HIGH and the PWRDET pin is HIGH, but it is reset to 0 when the comparator output is LOW. If the time counter reaches the target count and V1 is still HIGH (that is, the IQ modulator output power is still low), then the logic goes in power-alert mode and PWRDET pin goes LOW. The power-alarm logic stays in the power-alert mode until a software reset is programmed. The device recognizes a software reset as a transition from 0 to 1 of the controlling bit DET_RESET (SPI-3, register 1, B<20>). Figure 107 illustrates how the power-alarm logic works from power up of the IC. Power UP POWER ALERT STATE PWRDET = LOW V1 = X SW_RESET = 0 1 V1 = HIGH V1 = ? V1 = LOW NORMAL MODE TIME COUNTER >= td V1 = HIGH PWRDET = HIGH V1 = LOW V1 = HIGH PRE-ALARM MODE PWRDET = HIGH TIME COUNTER STARTS TIME COUNTER < td V1 = LOW COUNTER ? V1 ? Figure 107. TX Power-Alarm Flow Chart Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 61 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TX OUTPUT POWER RAMP-DOWN To avoid unwanted spurious emissions during power down of the transmitter, the power-down circuitry is designed to ramp down the output power gradually. The ramp-down time constant is programmable. PS_TC<1,0> (SPI-3, register 3, B<10,9>) allows selection of four different time constants. PS_TC POWER DOWN 00 28 µs 01 42 µs 10 57 µs 11 75 µs The values shown in the preceding table are the typical times required for the output level to be attenuated by 30 dB. LOOPBACK The TRF2443 integrates a loopback switch between the TX and the RX chains. The switch connects the TX modulator output to the RX IFVGA3 input. This path can be used for three different functions: • Loopback path for the transmitted signal • RX baseband low-pass-filter corner-frequency calibration • TX modulator LO leakage calibration The loopback mode is enabled by setting EN_LB (SPI-3, register 1, B<18>) to 1. When the switch is activated, the TX amplifier, RX LNA, RX IFVGA1, and RX IFVGA2 are all turned off automatically. The loopback path can be programmed with two different insertion losses: • 20-dB insertion loss for the loopback path of the transmitted signal • Minimum insertion loss for calibration mode The attenuation mode is selected via EN_LB_ATT (SPI-3, register 1, B<19>). EN_LB_ATT = 1 → 20-dB attenuation EN_LB_ATT = 0 → minimum insertion loss TX Signal Loopback The TRF2443 internal feedback path can be used to loop back the TX signal (1), which enables the RX chain to be used to monitor the transmitted signal. This mode is controlled via the serial programming interface (SPI) according the following possible steps: 1. Enable loopback switch with 20-dB attenuation a. EN_LB_ATT = 1 (SPI-3, register 1, B<19>) b. EN_LB = 1 (SPI-3, register 1, B<18>) 2. Program TXLO to 165 MHz (TXLO to 2640 MHz and TX divider to 16) a. TXRDIV<13,0> = <00 0000 0000 0001> (SPI-1, register 1, B<18,5>) [R = 1] b. TX_NINT<15,0> = <0000 0000 0100 0010> (SPI-1, register 2, B<20,5>) [N = 66] c. TXDIV_SEL = 0 (SPI-1, register 2, B<26>) [LO divider set to 16] 3. Program RXLO to 165 MHz (RXLO to 2640 MHz and RX divider to 16) a. RXRDIV<13,0> = <00 0000 0000 0001> (SPI-2, register 1, B<18,5>) [R = 1] b. RX_NINT<15,0> = <0000 0000 1000 0100> (SPI-2, register 2, B<20,5>) [N = 132] c. RXDIV_SEL = 0 (SPI-2, register 2, B<26>) [LO divider set to 16] 4. Set receiver baseband gain to 10 dB a. RXBB_GAIN<4,0> = <00001> (SPI-3, register 2, B<15,11>) 5. Program the receiver baseband-filter cutoff frequency to the appropriate value (depending on the TX signal bandwidth). (1) 62 For a TX loopback frequency of 165 MHz, the PLLs are locked to a 20-MHz PFD frequency. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Baseband-Filter Cutoff-Frequency Calibration The TRF2443 internal feedback path can be used to set up an automatic calibration of the RX baseband-filter cutoff frequency. The procedure to calibrate the corner frequency to 3 MHz is described as follows. 1. Enable loopback switch with minimum insertion loss. a. EN_LB_ATT = 0 (SPI-3, register 1, B<19>) b. EN_LB = 1 (SPI-3, register 1, B<18>) 2. Program RXLO to 165 MHz (RXLO to 2640 MHz and RX divider to 16). a. RXRDIV<13,0> = <00 0000 0000 0001> (SPI-2, register 1, B<18,5>) [R = 1] b. RX_NINT<15,0> = <0000 0000 1000 0100> (SPI-2, register 2, B<20,5>) [N = 132] c. RXDIV_SEL = 0 (SPI-2, register 2, B<26>) [LO divider set to 16] 3. Set TXVCO divider to 16. a. TXDIV_SEL = 0 (SPI-1, register 2, B<26>) [LO divider set to 16] 4. Set the TXPLL PFD frequency to 4 MHz (R divider = 5). a. TXRDIV<13,0> = <00 0000 0000 0101> (SPI-1, register 1, B<18,5>) [R = 5] 5. Apply a dc offset at the TRF2443 TX baseband inputs (to increase the TXLO leakage at the modulator output). 6. Set the RX baseband amplifier gain to 22 dB. a. RXBB_GAIN<4,0> = <01101> (SPI-3, register 2, B<15,11>) 7. Set the RX baseband cutoff-frequency bit controls RXBB_FREQ<6,0> = 011 1000 (typical value for fC = 3 MHz) 8. Program the TXLO frequency to 166 MHz (TXVCO = 2656 MHz). a. TX_NINT<15,0> = <0000 0001 0100 1100> (SPI-1, register 2, B<20,5>) [N = 332] 9. Measure the RX baseband output-power level (at I or Q output): Pout1. 10. Program the TXLO frequency to 168 MHz (TXVCO = 2688 MHz). a. TX_NINT<15,0> = <0000 0001 0101 0000> (SPI-1, register 2, B<20,5>) [N = 336] 11. Measure the RX baseband output power level (Pout2) and calculate attenuation: Att = Pout1 – Pout2. 12. If Att < 3 dB, then increase RXBB_FREQ and go back to 11); else if Att > 3 dB, then reduce RXBB_FREQ and go back to 11). This is repeated until two sequential iterations result in the calculated attenuation being above and below 3 dB. When this is observed, save the RXBB_FREQ value which results in an attenuation value closer to 3 dB. The TRF2443 baseband low-pass filter cutoff frequency can be programmed to any of 128 cutoff frequencies. The cutoff frequency control consists of 7 bits, RXBB_FREQ<6,0>, which are located in SPI-3, register 2, B<22,16>. RXBB_FREQ<6,0> = <111 1111> corresponds to the minimum corner frequency. Figure 108 shows the 3-dB bandwidth of the filter versus all possible SPI codes for a typical unit. Figure 109 shows the inverse of the 3-dB bandwidth versus all possible SPI codes for a typical unit. 16 0.7 14 0.6 RXBB Filter 1/BW RXBB Filter BW 12 10 8 RXBB I 6 4 0.4 0.3 RXBB I 0.2 0.1 RXBB Q 2 RXBB Q 0.5 0 0.0 0 10 20 30 40 50 60 70 80 90 100 110 120 LPF BW Adj (dec) 0 10 20 30 40 50 60 70 80 90 100 110 120 LPF BW Adj (dec) G070 Figure 108. BW vs SPI Code (RXBB_FREQ<6,0> G071 Figure 109. 1/BW vs SPI Code (RXBB_FREQ<6,0> Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 63 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com Because the corner frequency is dependent on the on-chip capacitance, it is possible to observe variations from unit to unit in the SPI code that yields a fixed corner frequency. Variations in capacitance from unit to unit result in a unique 1/BW curve for each unit. If the same DUT is to be used at multiple corner frequencies, the user should calibrate the DUT as described above to determine, at a minimum, 2 points on the 1/BW curve. From these calibrated points, any other corner frequency can be extrapolated using linear regression. TX LO Leakage Calibration The TRF2443 internal feedback path can be used to set up an automatic calibration of the TX LO leakage according the following potential procedure: 1. Enable loopback switch with minimum insertion loss. a. EN_LB_ATT = 0 (SPI-3, register 1, B<19>) b. EN_LB = 1 (SPI-3, register 1, B<18>) 2. Set RXLO = 330 MHz (RXVCO to 2640 MHz and RX divider to 8) a. RXRDIV<13,0> = <00 0000 0000 0001> (SPI-2, register 1, B<18,5>) [R = 1] b. RX_NINT<15,0> = <0000 0000 1000 0100> (SPI-2, register 2, B<20,5>) [N = 132] c. RXDIV_SEL = 1 (SPI-2, register 2, B<26>) [LO divider set to 8] 3. Set RX baseband in filter bypass mode and gain = 22 dB a. RXBB_GAIN<4,0> = <01101> (SPI-3, register 2, B<15,11>) [gain = 22 dB] b. RXBB_FLT_BYP = 1 (SPI-3, register 2, B<23>) [bypass filter] 4. Program TX LO in normal mode (TXLO = 340 MHz). a. TXRDIV<13,0> = <00 0000 0000 0001> (SPI-1, register 1, B<18,5>) [R = 1] b. TX_NINT<15,0> = <0000 0000 0100 0100> (SPI-1, register 2, B<20,5>) [N = 68] c. TXDIV_SEL = 1 (SPI-1, register 2, B<26>) [LO divider set to 8] 5. Measure power level at RXBB output at 10 MHz = P1. 6. Change TX input dc offset until minimum P1 is achieved. The TRF2443 TX baseband inputs can be ac- or dc-coupled to the external digital-to-analog converter (DAC). In case of direct coupling, the DAC must provide the appropriate dc offset of step 6 to null the LO leakage. If an ac-coupled approach is selected, then the internal bias must be enabled by setting EN_TXCM = 1 (SPI-3, register 3, B<31>). In this case, the integrated dc DAC controls the baseband dc offset. The internal DAC is programmed via the SPI. TXBBI<5,0> (SPI-3, register 3, B<30,25>) and TXBBQ<5,0> (SPI-3, register 3, B<24,19>) control the internal DAC settings. TXBBI<5,0> = TXBBQ<5,0> = <10 0000> corresponds to midrange, that is, no offset applied. RX IMAGE REJECTION The TRF2443 has been designed to provide optimal image rejection. Using symmetry in the design of the I and Q paths of the receiver ensures that mismatch between the I and Q paths is minimized. Image rejection is a function of the amplitude (A) mismatch and the phase error (Φ) from 90 degrees of the I and Q RX baseband signals. Image rejection is calculated in the following manner: é A 2 - 2Acosf + 1ù Rejection(dB) = 10log ê 2 ú ëê A + 2Acosf + 1ûú DC-OFFSET CALIBRATION The TRF2443 provides an automatic calibration procedure for adjusting the dc offset in the receiver and XPIC baseband I/Q paths. The internal calibration requires a clock in order to function. This clock is derived internally from the reference clock with a frequency divider, whose divider ratio is programmable. DCOFF_CLK<2,0> (SPI-3, register 5, B<16,14>) and XDCOFF_CLK<2,0> (SPI-3, register 5, B<29,27>) set the division ratio for the dc-offset correction-loop clock for the receiver and XPIC chains, respectively. The output full-scale range of the internal dc-offset-correction DAC is programmable using bits DCOFF_BIAS<1,0> (SPI-3, register 5, B<13,12>) for the receiver chain and XPICDCOFF_BIAS<1,0> (SPI-3, register 5, B<26,25>) for the XPIC chain. The range is shown in Table 11. 64 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Table 11. DC Offset Correction DAC Programmable Range DCOFF_BIAS _B1 XPICDCOFF_BIAS _B1 DCOFF_BIAS _B0 XPICDCOFF_BIAS _B0 FULL SCALE 0 0 10 mV 0 1 20 mV 1 0 30 mV 1 1 40 mV The I- and Q-channel output maximum dc-offset correction range can be calculated by multiplying the values in Table 11 by the baseband PGA gain. The LSB of the digital correction is dependent on the programmed maximum correction range. The dc offset correction DAC output is affected by a change in the PGA gain, but if the initial calibration yields optimum results, then the adjustment of the PGA gain during normal operation does not significantly impair the dc offset balance. The dc offset correction DACs are programmed from the internal registers when the RXBB_CALSELECT bit (SPI-3, register 7, B<21>) is set to 1 (default value at power on). At start-up, the internal registers are loaded at half-scale, corresponding to a decimal value of 128. The autocalibration for the receiver chain is initiated by setting the EN_BB_AUTOCAL bit (SPI-3, register 5, B<5>) to 1. When the calibration is over, this bit is automatically reset to 0. Similarly for the XPIC, by programming EN_XPIC_AUTOCAL (SPI-3, register 5, B<18>) to 1, the baseband dc-offset calibration starts. During calibration, the RX local oscillator must be on. At each clock cycle during an autocalibration sequence, the internal circuitry senses the output dc offset and calculates the new dc current for the DAC. After the 13th clock cycle, the calibration is complete and the EN_BB_AUTOCAL (or EN_XPIC_AUTOCAL) bit is reset to 0. The dc-offset DAC state is stored in the internal registers and maintained as long as the power supply is kept on or until a new calibration is started. The required clock speed for the optimum calibration is determined by the internal detector behavior (integration bandwidth, gain, sensitivity). The speed of the clock can be slowed down by selecting a clock divider ratio DCOFF_CLK<2,0> (SPI-3, register 5, B<16,14>) and/or XDCOFF_CLK<2.0> (SPI-3, register 5, B<29,27>). The detector has more averaging time the slower the clock; hence, it can be desirable to slow down the clock speed for a given condition to achieve optimum results. The internal registers controlling the internal dc current DAC for the receiver chain are accessible through the SPI (SPI-3, register 7, B<20,5>), providing a user-programmable method for implementing the dc-offset calibration. To employ this option, the RXBB_CALSELECT (SPI-3, register 7, B<21>) bit must be set to 0. During this calibration, an external instrument monitors the output dc offset between the I/Q differential outputs and programs the internal registers RXBBI_DCOFF<7,0> (SPI-3, register 7, B<12,5) and RXBBQ_DCOFF<7,0>, (SPI-3, register 7, B<20,13) to cancel the dc offset. TEMPERATURE SENSOR The TRF2443 integrates a temperature sensor that can be used to monitor the die junction temperature. To enable it, PWD_TEMPSENS (SPI-3, register 4, B<22>) must be set to 0. The temperature sensor generates a dc voltage proportional to the measured temperature. This voltage is output at the TEMPOUT pin (pin 37). The output voltage goes typically from 500 mV at –40°C to 970 mV at 150°C. The temperature sensor output can also be read through the SPI. An internal ADC converts the analog information to digital bits. The internal data-converter is enabled by setting PWD_TEMPADC (SPI-3, register 4, B<21>) to 0. The conversion starts when ADC_START (SPI-3, register 4, B<5>) is set to 1. The internal ADC uses a clock (ADC clock) generated from the external reference clock with a divide-by-16 frequency divider. At the end of conversion, ADC_START is reset to 0 and the 8-bit word ADC output is transferred into SPI-3, register 0, B<29,22>, where it can be read through the readback mode (See the READBACK MODE section). When the data conversion from analog to digital is complete, the CONVDONE bit (SPI-3, register 0, B<5>) is set to 1. If the ADC input signal is outside its input voltage range, the OUTRANGE bit (SPI-3, register 0, B<6>) is 1. The ADC input voltage range is 1 V, from 0.125 V to 1.125 V. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 65 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com APPLICATION SCHEMATIC +3.3V 0.1uF 15pF 82nH 220pF IF Saw Filter 50 OHM 220pF XPICOUT 220pF 15pF 82nH 75 OHM DIFF 41 42 44 RXBBQP 43 RXBBIP RXBBIN 46 45 GNDDIGRX 47 VCCPLLRX GNDPLLRX VCCDIGRX 49 48 50 VTUNERX CPOUTRX 52 51 VCCVCORX RXLOTEST GNDVCORX 54 53 55 XPICOUTN RXBBQN TEMPOUT 37 GND 36 35 GND XPICINP VCCRX XPICINN 34 68 RXINP VCCXPIC2 33 69 RXINN GND 32 70 GNDRX 71 TRF2443 QFP XPICBBIP 28 DATASPI XPICBBIN 27 75 VCCSPI XPICBBQP 26 76 VCCTX XPICBBQN 25 77 TXOUTP XPICBBCM 24 78 TXOUTN GNDXPIC 23 79 GNDTX TXBBIP 22 80 GNDTX2 TXBBIN 21 TXBBQP TEMPOUT 1nF XPICAGC 20 REFIN GND 19 18 17 16 15 14 12 13 10 11 +3.3V TXBBQN CLKSPI 74 GNDREF 73 VCCREF 29 GNDDIGTX VCCXPIC VCCDIGTX LESPI VCCPLLTX 72 GNDPLLTX 30 CPOUTTX XPICAGC VTUNETX 31 GNDRX GNDVCOTX GND 1 39nH F=2240MHZ LBW=100KHZ 40 67 9 50 ohm RXBBCM 66 8 100pF VCCIFIN RXAGC VCCVCOTX 200 OHM DIFF XPICOUTP RDBKSPI 65 TXLOTEST 100pF 57 64 7 100pF TXOUT (340MHz) IFINP 38 6 39nH 59 39 LDCAP LOCKDET +3.3V 58 GND IFOUTP 220pF 0.1uF IFINN 60 PWRPAD IFOUTN 63 PWRDET 50 OHM DIFF 22pF 680pF 4K ohm 62 4 220pF 220pF 47pF GNDRX3 MIXINDP 50 OHM RXIN 1K ohm 61 3 RXAGC GNDIFIN 81 50 OHM DIFF GNDIFIN2 15pF MIXINDN 15pF +3.3V TXPWD 82nH 2 82nH +3.3V 56 220pF 0.1uF 5 220pF 50 OHM DIFF +3.3V 0.1uF 1000pF +3.3V REFIN 68nH 2 1 590 ohm 1000pF 1.25K ohm 68nH TX MIXER LOAD (340MHz) 56pF 560pF 56pF 5K ohm F=2720MHz LBW=100kHz Figure 110. TRF2443 Application Schematic Table 12. Pin Termination Requirements/Limitations NAME PIN IFOUTN/IFOUTP 62, 63 IFVGA1 open-collector output terminals. A pullup inductor from each pin to the power supply is required. 18 Ground pin shorted to package thermal pad. To be connected to the same ground plane as GNDREFIN (pin 17). GND IFINP/IFINN 57, 58 DESCRIPTION IFVGA2 differential input pins internally matched to 50 Ω. LDCAP 38 Lock-detector capacitor pin. The size of capacitor on this pin sets the time constant of the lock-detect circuit. Suggested value for 20-MHz PFD frequency: connect a 1-nF capacitor to ground on this pin (10-µs deglitch time). MIXINDN/ MIXINDP 2, 3 TX IQ modulator open-collector load terminals. A pullup inductor from each pin to the power supply is required. A shunt load resistor is required. PWRDET, LOCKDET, RDBKSPI 4, 5, 64 REFIN 66 16 TRF2443 digital output pins can sink/source up to 8 mA of current. PLL reference clock input. External ac-coupling capacitor required, as pin is internally dc-coupled. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Table 12. Pin Termination Requirements/Limitations (continued) NAME RXAGC RXINP/ RXINN PIN 65 68, 69 DESCRIPTION Receiver-chain VGA gain-control dc-voltage input. Equivalent input impedance: 100 kΩ in series with 4 pF. RX input differential terminals. Input impedance is 50 Ω differential. A 1:1 balun is required to drive it single-ended. RXLOTEST 53 RX VCO output pin: test output to check internal RX local oscillator. If it is not used, the pin can be grounded. TEMPOUT 37 Temperature-sensor output. If temperature sensor is not used (disabled), this pin should be terminated with a 100-kΩ resistor to ground. If it used, the TEMPOUT buffer can drive impedances of R > 10 kΩ and C < 100 pF. TXLOTEST 6 TX VCO output pin: test output to check internal TX local oscillator. If it is not used, the pin can be grounded. TXBBIP/ TXBBIN 22, 21 TX baseband I-channel differential inputs. If EN_TXCM (SPI-3, register 3, B<31>) = 0, external AC coupling caps and 100-Ω differential resistor is required. TXBBQP/ TXBBQN 20, 19 TX baseband Q-channel differential inputs. If EN_TXCM (SPI-3, register 3, B<31>) = 0, external AC coupling caps and 100-Ω differential resistor is required. TXOUTP/ TXOUTN 77, 78 TX amplifier open-collector output terminals. A pullup inductor from each pin to power supply is required. Output impedance is set typically to 200 Ω differential. A 4:1 impedance-ratio balun is needed to transform to 50 Ω single-ended. TXPWD 1 TX power down; digital input VCCRX 67 RX-chain power supply. The decoupling capacitor on this power supply should be connected to the same ground plane to which the GNDRX pins, 70 and 71, are connected. 30 XPIC chain VGA gain-control dc-voltage input. Equivalent input impedance: 100 kΩ in series with 4 pF. XPICAGC XPICOUTN/ XPICOUTP 54, 55 XPIC output-amplifier open-collector output terminals. Output impedance is set typically to 75 Ω differential with an internal resistor so that no external load is required. A pullup inductor from each pin to the power supply is required. A 1:1 impedance ratio balun is needed to transform to 75 Ω single-ended. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 67 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com EVM BOARD LAYOUT ASSEMBLY TOP COMPONENT SIDE (S01) TRF2443 REV C J29 RXLOTEST J31 IFIN J33 XPICOUT J15 RXBBI J24 RXBBQ J30 IFOUT J32 XPICIN J16 XPICBBI J7 RXIN J6 TXOUT J25 XPICBBQ J1 VCC J5 USB J2 GND J28 TXLOTEST J3 REFIN J23 TXBBQN J20 TXBBQP J17 TXBBIN J12 TXBBIP Figure 111. TRF2443 EVM Top Layer 68 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 PACKAGE OPTION ADDENDUM www.ti.com 23-Sep-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TRF2443IPFP ACTIVE HTQFP PFP 80 TRF2443IPFPR ACTIVE HTQFP PFP 80 96 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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