19-3148; Rev 4; 12/04 KIT ATION EVALU LE B A IL A AV 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface The MAX5732–MAX5735 are 32-channel, 16-bit, voltageoutput, digital-to-analog converters (DACs). All devices accept a 3V external reference input. The devices include an internal offset DAC that allows all the outputs to be offset and a ground-sensing function, allowing output voltages to be referenced to a remote ground. A 33MHz SPI™-/QSPI™-/MICROWIRE™- and digital signal processor (DSP)-compatible serial interface controls the MAX5732–MAX5735. Each DAC has a doublebuffered input structure that helps minimize the digital noise feedthrough from the digital inputs to the outputs, and allows for synchronous or asynchronous updating of the outputs. The MAX5732–MAX5735 also provide a DOUT that allows for read-back or daisy chaining multiple devices. The devices provide separate power inputs for the analog and digital sections and provide separate power inputs for the output buffer amplifiers. The MAX5732–MAX5735 include proprietary deglitch circuits to prevent output glitches at power-up and eliminate the need for power sequencing. The devices provide a software-shutdown mode to allow efficient power management. The MAX5732–MAX5735 consume 50µA of supply current in shutdown. Features ♦ Guaranteed Monotonic to 16 Bits ♦ 32 Individual DACs in an 8mm x 8mm, 56-Pin, Thin QFN Package ♦ Four Output Voltage Ranges 0 to +5V 0 to +10V -2.5V to +7.5V -5V to +5V ♦ Buffered Voltage Outputs Capable of Driving 10kΩ || 100pF ♦ Glitch-Free Power-Up ♦ SPI-/QSPI-/MICROWIRE-/DSP-Compatible 33MHz Serial Interface Ordering Information PART TEMP RANGE PIN-PACKAGE MAX5732ACTN* 0°C to +70°C 56 Thin QFN-EP** MAX5732BCTN 0°C to +70°C 56 Thin QFN-EP** MAX5732CCTN 0°C to +70°C 56 Thin QFN-EP** MAX5732AETN* -40°C to +85°C 56 Thin QFN-EP** MAX5732BETN -40°C to +85°C 56 Thin QFN-EP** MAX5732CETN -40°C to +85°C 56 Thin QFN-EP** MAX5733ACTN* 0°C to +70°C 56 Thin QFN-EP** MAX5733BCTN 0°C to +70°C 56 Thin QFN-EP** MAX5733CCTN 0°C to +70°C 56 Thin QFN-EP** MAX5733AETN* -40°C to +85°C 56 Thin QFN-EP** MAX5733BETN -40°C to +85°C 56 Thin QFN-EP** MAX5733CETN -40°C to +85°C 56 Thin QFN-EP** MAX5734ACTN* 0°C to +70°C 56 Thin QFN-EP** Automatic Test Systems MAX5734BCTN 0°C to +70°C 56 Thin QFN-EP** Optical Router Controls MAX5734CCTN 0°C to +70°C 56 Thin QFN-EP** Industrial Process Controls MAX5734AETN* -40°C to +85°C 56 Thin QFN-EP** MAX5734BETN -40°C to +85°C 56 Thin QFN-EP** MAX5734CETN -40°C to +85°C 56 Thin QFN-EP** MAX5735ACTN* 0°C to +70°C 56 Thin QFN-EP** MAX5735BCTN 0°C to +70°C 56 Thin QFN-EP** MAX5735CCTN 0°C to +70°C 56 Thin QFN-EP** MAX5735AETN* -40°C to +85°C 56 Thin QFN-EP** SPI/QSPI are trademarks of Motorola, Inc. MAX5735BETN -40°C to +85°C 56 Thin QFN-EP** MICROWIRE is a trademark of National Semiconductor Corp. MAX5735CETN -40°C to +85°C 56 Thin QFN-EP** The MAX5732–MAX5735 provide buffered outputs that can drive 10kΩ in parallel with 100pF. The MAX5732 has a 0 to +5V output range; the MAX5733 has a 0 to +10V range; the MAX5734 has a -2.5V to +7.5V range; the MAX5735 has a -5V to +5V range. The MAX5732– MAX5735 are available in a 56-pin, 8mm x 8mm, thin QFN package in both the commercial (0°C to +70°C) and extended (-40°C to +85°C) temperature ranges. Applications Arbitrary Function Generators Avionics Equipment Digital Offset/Gain Adjustment Pin Configuration and Selector Guide appear at end of data sheet. *Future product—contact factory for availability. Specifications are preliminary. **EP = Exposed paddle (internally connected to VSS). ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5732–MAX5735 General Description MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface ABSOLUTE MAXIMUM RATINGS AVCC to VSS, AGND, DGND, REFGND ..................-0.3V to +12V VSS to AGND, DGND................................................-6V to +0.3V AVDD, DVDD to AGND, DGND, REFGND.................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V REF to AGND, DGND, REFGND...............-0.3V to the lower of (AVDD + 0.3V) and +6V REFGND to AGND.................................................-0.3V to +0.3V Digital Inputs to AGND, DGND, REFGND..............-0.3V to the lower of (DVDD + 0.3V) and +6V DOUT to DGND.......-0.3V to the lower of (DVDD + 0.3V) and +6V OUT_ to VSS .........-0.3V to the lower of (AVCC + 0.3V) and +12V GS to AGND ................................................................-1V to +1V Maximum Current into REF...............................................±10mA Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) Thin QFN (derate 31.3mW/°C above +70°C)...................2.5W Operating Temperature Ranges MAX573__CTN....................................................0°C to +70°C MAX573__ETN .................................................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX5732 (0 to +5V Output Voltage Range) (AVCC = +5.25V to +5.5V (Note 1), AVDD = +5V ±5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.0V, RL = ∞, CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS Resolution N Integral Nonlinearity (Note 2) INL Differential Nonlinearity Zero-Scale Error DNL VOS Full-Scale Error 16 MAX5732B ±8 ±16 MAX5732C ±32 ±64 Guaranteed monotonic (Note 3) ±1 LSB LSB VSS = -0.5V, AVCC = +5.25V (Note 4) ±8 ±40 mV (Note 4) ±8 ±50 mV ±0.1 ±0.5 %FSR 20 40 ppm FSR/°C VSS = -0.5V, AVCC = +5V (Note 5) 50 250 µV Full-scale change to ±0.5 LSB 20 µs 1 V/µs Gain Error Gain Temperature Coefficient DC Crosstalk Bits DYNAMIC CHARACTERISTICS Output-Voltage Settling Time Voltage-Output Slew Rate Digital Feedthrough (Note 6) 5 nV-s Digital Crosstalk (Note 7) 5 nV-s Digital-to-Analog Glitch Impulse Major carry transition 120 nV-s DAC-to-DAC Crosstalk (Note 8) 15 nV-s Output Noise Spectral Density at 1kHz Full-scale code 250 nV/√Hz ANALOG OUTPUTS (OUT0 to OUT31) Output Voltage Range Resistive Load to Ground 2 VSS = -0.5V, AVCC = +5V 0 10 5 50 _______________________________________________________________________________________ V kΩ 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface (AVCC = +5.25V to +5.5V (Note 1), AVDD = +5V ±5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.0V, RL = ∞, CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN Capacitive Load to Ground DC Output Impedance TYP MAX UNITS 50 100 pF Ω 0.1 Sourcing, full-scale code, output connected to AGND 5 Sinking, zero-scale code, output connected to AVCC -5 Short-Circuit Current mA GROUND-SENSE ANALOG INPUT (GS) Input Voltage Range VGS GS Gain AGS Relative to AGND -0.5 0.995 -0.5V ≤ VGS ≤ +0.5V, VSS = -0.5V Input Resistance 1.000 +0.5 V 1.005 V/V 35 kΩ REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range 1 VREF Referred to REFGND 2.900 MΩ 3.000 3.100 V DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP) Input-Voltage High VIH Input-Voltage Low VIL Input Capacitance CIN Input Current IIN DVDD = +2.7V to +3.6V DVDD = +4.75V to +5.25V 0.7 × DVDD V 2.4 0.8 10 Digital inputs = 0 or DVDD V pF ±1 µA POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) Output-Amplifier Positive Supply Voltage AVCC 4.75 5.50 V Output-Amplifier Negative Supply Voltage VSS -0.5 0 V 5.75 V V Output-Amplifier Supply Voltage Difference AVCC - VSS Analog Supply Voltage AVDD 4.75 5.25 Digital Supply Voltage DVDD 2.70 5.25 V 15 mA Analog Supply Current AIDD Digital Supply Current DIDD Output-Amplifier Positive Supply Current AICC Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio ISS PSRR VOUT0 through VOUT31 = 0 10 Software shutdown 10 VIH = DVDD, VIL = 0, fSCLK = 20MHz 2.5 3.5 5 6.5 VOUT0 through VOUT31 = 0 4 10 mA Software shutdown 20 -10 mA VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz VSS = -0.5V VOUT0 through VOUT31 = 0 Software shutdown -4 µA mA µA -20 µA -95 dB _______________________________________________________________________________________ 3 MAX5732–MAX5735 ELECTRICAL CHARACTERISTICS—MAX5732 (0 to +5V Output Voltage Range) (continued) MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX5733 (0 to +10V Output Voltage Range) (AVCC = +10.5V to +11V, AVDD = 5V ±5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.0V, RL = ∞, CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX MAX5733B ±8 ±16 MAX5733C ±32 ±64 UNITS DC CHARACTERISTICS Resolution N 16 Bits Integral Nonlinearity (Note 2) INL Differential Nonlinearity DNL Guaranteed monotonic (Note 3) ±1 LSB Zero-Scale Error VOS VSS = -0.5V, AVCC = +10V (Note 4) ±8 ±40 mV (Note 4) ±8 ±50 mV ±0.1 ±0.5 % FSR Full-Scale Error Gain Error Gain Temperature Coefficient ppm FSR/°C 20 DC Crosstalk LSB VSS = -0.5V, AVCC = +10V (Note 5) 50 250 µV Full-scale change to ±0.5 LSB 20 1 V/µs Digital Feedthrough (Note 6) 5 nV-s Digital Crosstalk (Note 7) 5 nV-s Digital-to-Analog Glitch Impulse Major carry transition 120 nV-s DAC-to-DAC Crosstalk (Note 8) 15 nV-s Output Noise Spectral Density at 1kHz Full-scale code 250 nV/√Hz DYNAMIC CHARACTERISTICS Output-Voltage Settling Time Voltage-Output Slew Rate µs ANALOG OUTPUTS (OUT0 to OUT31) Output Voltage Range VSS = -0.5V, AVCC = +10.5V Resistive Load to Ground 0 10 Capacitive Load to Ground 10 50 50 DC Output Impedance 100 5 Sinking, zero scale, output connected to AVCC -5 pF Ω 0.1 Sourcing, full scale, output connected to AGND V kΩ Short-Circuit Current mA GROUND-SENSE ANALOG INPUT (GS) Input Voltage Range VGS GS Gain AGS Relative to AGND -0.5V ≤ VGS ≤ +0.5V, VSS = -0.5V Input Resistance -0.5 0.995 1.000 +0.5 V 1.005 V/V 70 kΩ REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range 4 1 VREF Referred to REFGND 2.900 MΩ 3.000 _______________________________________________________________________________________ 3.100 V 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface (AVCC = +10.5V to +11V, AVDD = 5V ±5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.0V, RL = ∞, CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP) Input-Voltage High VIH DVDD = +2.7V to +3.6V DVDD = +4.75V to +5.25V Input-Voltage Low VIL Input Capacitance CIN Input Current IIN 0.7 × DVDD V 2.4 0.8 10 Digital inputs = 0 or DVDD V pF ±1 µA POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) Output-Amplifier Positive Supply Voltage AVCC 10 11 V Output-Amplifier Negative Supply Voltage VSS -0.5 0 V 11 V V Output-Amplifier Supply Voltage Difference AVCC - VSS Analog Supply Voltage AVDD 4.75 5.25 Digital Supply Voltage DVDD 2.70 5.25 V 15 mA Analog Supply Current AIDD Digital Supply Current DIDD Output-Amplifier Positive Supply Current AICC Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio ISS PSRR VOUT0 through VOUT31 = 0 10 Software shutdown 10 VIH = DVDD, VIL = 0, fSCLK = 20MHz 2.5 3.5 5 6.5 VOUT0 through VOUT31 = 0 4 10 mA Software shutdown 20 -10 mA VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz VSS = -0.5V µA mA µA VOUT0 through VOUT31 = 0 -4 Software shutdown -20 µA -95 dB _______________________________________________________________________________________ 5 MAX5732–MAX5735 ELECTRICAL CHARACTERISTICS—MAX5733 (0 to +10V Output Voltage Range) (continued) MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX5734 (-2.5V to +7.5V Output Voltage Range) (AVCC = +7.75V to +8.25V, AVDD = +5V ±5%, DVDD = +2.7V to AVDD, VSS = -2.75V to -3.25V, AGND = DGND = REFGND = GS = 0, program the offset DAC to 4000hex. VREF = +3.0V, RL = ∞, CL= 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MAX5734B ±8 ±16 MAX5734C ±32 ±64 ±1 LSB ±8 ±40 mV DC CHARACTERISTICS Resolution N 16 Integral Nonlinearity (Note 2) INL Differential Nonlinearity Zero-Scale Error DNL Guaranteed monotonic (Note 3) VOS VSS = -3.25V, AVCC = +7.75V (Note 4) Full-Scale Error (Note 4) Gain Error Gain Temperature Coefficient Bits ±8 ±50 mV ±0.1 ±0.5 %FSR ppm FSR/°C 20 DC Crosstalk LSB VSS = -3.25V, AVCC = +7.75V (Note 4) 50 250 µV Full-scale change to ±0.5 LSB 20 µs 1 V/µs 5 nV-s 5 nV-s DYNAMIC CHARACTERISTICS Output-Voltage Settling Time Voltage-Output Slew Rate Digital Feedthrough (Note 6) Digital Crosstalk (Note 7) Digital-to-Analog Glitch Impulse Major carry transition 120 nV-s DAC-to-DAC Crosstalk (Note 8) 15 nV-s Output Noise Spectral Density at 1kHz Full-scale code 250 nV/√Hz ANALOG OUTPUTS (OUT0 to OUT31) Output Voltage Range VSS = -2.75V, AVCC = +7.75V Resistive Load to Ground -2.5 10 +7.5 50 Capacitive Load to Ground 50 DC Output Impedance 0.1 Sourcing, full scale, output connected to AGND V kΩ 100 pF Ω 5 Short-Circuit Current mA Sinking, zero scale, output connected to AVCC -5 GROUND-SENSE ANALOG INPUT (GS) Input Voltage Range VGS GS Gain AGS Relative to AGND -0.5V ≤ VGS ≤ +0.5V, VSS = -0.5V Input Resistance -0.5 0.995 1.000 +0.5 V 1.005 V/V 70 kΩ 1 MΩ REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range 6 VREF Referred to REFGND 2.900 3.000 _______________________________________________________________________________________ 3.100 V 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface (AVCC = +7.75V to +8.25V, AVDD = +5V ±5%, DVDD = +2.7V to AVDD, VSS = -2.75V to -3.25V, AGND = DGND = REFGND = GS = 0, program the offset DAC to 4000hex. VREF = +3.0V, RL = ∞, CL= 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP) Input-Voltage High VIH Input-Voltage Low VIL Input Capacitance CIN Input Current IIN DVDD = +2.7V to +3.6V DVDD = +4.75V to +5.25V 0.7 × DVDD V 2.4 0.8 10 Digital inputs = 0 or DVDD V pF ±1 µA POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) Output-Amplifier Positive Supply Voltage AVCC 7.50 8.25 V Output-Amplifier Negative Supply Voltage VSS -3.25 -2.50 V 11 V 5.25 V Output-Amplifier Supply Voltage Difference AVCC - VSS Analog Supply Voltage AVDD Digital Supply Voltage DVDD Analog Supply Current AIDD Digital Supply Current DIDD Output-Amplifier Positive Supply Current AICC Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio ISS PSRR 4.75 2.70 5.25 V 15 mA VOUT0 through VOUT31 = 0 10 Software shutdown 10 VIH = DVDD, VIL = 0, fSCLK = 20MHz 2.5 3.5 5 6.5 VOUT0 through VOUT31 = 0 4 10 mA Software shutdown 20 -10 mA VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz VSS = -2.75V µA mA µA VOUT0 through VOUT31 = 0 -4 Software shutdown -20 µA -95 dB _______________________________________________________________________________________ 7 MAX5732–MAX5735 ELECTRICAL CHARACTERISTICS—MAX5734 (-2.5V to +7.5V Output Voltage Range) (continued) MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX5735 (-5V to +5V Output Voltage Range) (AVCC = +5.25V to +5.5V, AVDD = +5V ±5%, DVDD = +2.7V to AVDD, VSS = -5.25V to -5.5V, AGND = DGND = REFGND = GS = 0, program the offset DAC to 8000hex. VREF = +3.0V, RL = ∞, CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS Resolution N 16 Bits MAX5735B ±8 ±16 MAX5735C ±32 ±64 Integral Nonlinearity (Note 2) INL Differential Nonlinearity DNL Guaranteed monotonic (Note 3) Zero-Scale Error VOS VSS = -5.25V, AVCC = +5.25V (Note 4) ±8 ±40 mV (Note 4) ±8 ±50 mV ±0.1 ±0.5 %FSR Full-Scale Error ±1 Gain Error Gain Temperature Coefficient LSB ppm FSR/°C 20 DC Crosstalk LSB VSS = -5.75V, AVCC = +5.25V (Note 5) 50 250 µV Full-scale change to ±0.5 LSB 20 1 V/µs Digital Feedthrough (Note 6) 5 nV-s Digital Crosstalk (Note 7) 5 nV-s Digital-to-Analog Glitch Impulse Major carry transition DYNAMIC CHARACTERISTICS Output-Voltage Settling Time Voltage-Output Slew Rate DAC-to-DAC Crosstalk (Note 8) Output Noise Spectral Density at Full-scale code 1kHz ANALOG OUTPUTS (OUT0 through OUT31) Output Voltage Range VSS = -5.25V, AVCC = +5.25V Resistive Load to Ground 120 nV-s 15 nV-s 250 nV/√Hz -5 10 µs +5 50 Capacitive Load to Ground 50 DC Output Impedance 0.1 Sourcing, full scale, output connected to AGND 5 Sinking, zero scale, output connected to AVCC -5 V kΩ 100 pF Ω Short-Circuit Current mA GROUND-SENSE ANALOG INPUT (GS) Input Voltage Range VGS GS Gain AGS Relative to AGND 0.995 -0.5V ≤ VGS ≤ +0.5V, VSS = -0.5V Input Resistance -0.5 1.000 +0.5 V 1.005 V/V 70 kΩ REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range 8 1 VREF Referred to REFGND 2.900 MΩ 3.000 _______________________________________________________________________________________ 3.100 V 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface (AVCC = +5.25V to +5.5V, AVDD = +5V ±5%, DVDD = +2.7V to AVDD, VSS = -5.25V to -5.5V, AGND = DGND = REFGND = GS = 0, program the offset DAC to 8000hex. VREF = +3.0V, RL = ∞, CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP) Input-Voltage High VIH Input-Voltage Low VIL Input Capacitance CIN Input Current IIN DVDD = +2.7V to +3.6V 0.7 × DVDD DVDD = +4.75V to 5.25V 2.4 V 0.8 10 Digital inputs = 0 or DVDD V pF ±1 µA POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) Output-Amplifier Positive Supply Voltage AVCC 4.75 5.50 V Output-Amplifier Negative Supply Voltage VSS -5.50 -4.75 V 11 V Output-Amplifier Supply Voltage Difference AVCC - VSS Analog Supply Voltage AVDD 4.75 5.25 V Digital Supply Voltage DVDD 2.70 5.25 V Analog Supply Current AIDD 15 mA Digital Supply Current DIDD Output-Amplifier Positive Supply Current AICC Output-Amplifier Negative Supply Current ISS Power-Supply Rejection Ratio PSRR VOUT0 through VOUT31 = 0 10 Software shutdown 10 VIH = DVDD, VIL = 0, fSCLK = 20MHz 2.5 3.5 5 6.5 VOUT0 through VOUT31 = 0 4 10 Software shutdown 20 VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz VSS = -0.5V µA mA mA µA VOUT0 through VOUT31 = 0 -4 Software shutdown -20 µA -95 dB -10 mA Note 1: AVCC should be at least 0.25V higher than the maximum output voltage required from the DAC. Full-scale output is 5V for the MAX5732. Note 2: Linearity guaranteed from code 2047 to full scale and from (VSS + 0.3V) to (AVCC - 0.3V). Note 3: DNL guaranteed over all codes for (VSS + 0.3V) to (AVCC - 0.3V). Note 4: Zero-scale error is measured at code 0. Full-scale error is measured at code FFFFhex. Note 5: DC crosstalk is the change in the output level of one DAC at midscale in response to the full-scale output change of all other DACs. Note 6: Digital feedthrough is a measure of the impulse injected into the analog outputs from the digital control inputs when the device is not being written to. It is measured with a worst-case change on the digital inputs. Note 7: Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale while a full-scale code change is written into another DAC. Note 8: DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter. _______________________________________________________________________________________ 9 MAX5732–MAX5735 ELECTRICAL CHARACTERISTICS—MAX5735 (-5V to +5V Output Voltage Range) (continued) MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface TIMING CHARACTERISTICS—DVDD = +4.75V to +5.25V (Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +4.75V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 33 MHz Serial Clock Frequency fSCLK 0 SCLK Pulse-Width High tCH 10 SCLK Pulse-Width Low tCL 10 ns SCLK Fall to CS Fall Setup Time tSCS 6 ns CS Fall to SCLK Fall Setup Time tCSS CS Rise to SCLK Fall tCS1 SCLK Fall to CS Rise Setup Time ns 5 ns 15 ns tCS2 0 ns DIN to SCLK Fall Setup Time tDS 10 ns DIN to SCLK Fall Hold Time tDH 2 ns SCLK Fall to DOUT Fall tSCL Load capacitance = 20pF tSDH Load capacitance = 20pF SCLK Fall to DOUT Rise At end of cycle in SPI mode only 20 20 ns ns CS Pulse-Width High tCSPWH 50 ns CS Pulse-Width Low tCSPWL 20 ns tLDAC 20 ns tCLR 20 ns LDAC Pulse-Width Low CLR Pulse-Width Low TIMING CHARACTERISTICS—DVDD = +2.7V to +5.25V (Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 25 MHz Serial Clock Frequency fSCLK 0 SCLK Pulse-Width High tCH 10 ns SCLK Pulse-Width Low tCL 10 ns SCLK Fall to CS Fall Setup Time tSCS 10 ns CS Fall to SCLK Fall Setup Time tCSS 10 ns CS Rise to SCLK Fall tCS1 18 ns SCLK Fall to CS Rise Setup Time tCS2 0 ns DIN to SCLK Fall Setup Time tDS 10 ns DIN to SCLK Fall Hold Time tDH 2 ns At end of cycle in SPI mode only SCLK Fall to DOUT Fall tSCL Load capacitance = 20pF 25 SCLK Fall to DOUT Rise tSDH Load capacitance = 20pF 25 ns ns CS Pulse-Width High tCSPWH 50 ns CS Pulse-Width Low tCSPWL 20 ns tLDAC 20 ns tCLR 20 ns LDAC Pulse-Width Low CLR Pulse-Width Low 10 ______________________________________________________________________________________ 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface DIFFERENTIAL NONLINEARITY vs. INPUT CODE 4 0.3 2.0 INL (LSB) 2 0.1 0 1.0 0 -0.1 0.5 0 -0.2 0 10k 20k 30k 40k 50k 60k 70k 0 10k 20k 30k 40k 50k 60k -40 70k -15 10 35 INPUT CODE INPUT CODE TEMPERATURE (°C) WORST-CASE DNL vs. TEMPERATURE ZERO-SCALE ERROR vs. TEMPERATURE FULL-SCALE ERROR vs. TEMPERATURE 0.15 0.10 0.05 4 3 2 -15 10 35 60 85 85 MAX5732 toc06 3.0 2.5 2.0 1.5 0 -40 -15 10 35 60 85 -40 -15 10 35 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) ANALOG SUPPLY CURRENT vs. TEMPERATURE DIGITAL SUPPLY CURRENT vs. TEMPERATURE DIGITAL SUPPLY CURRENT vs. TEMPERATURE 8.8 59 58 8.7 111 110 109 DVDD (µA) 8.5 8.4 56 55 54 8.3 53 8.2 52 8.1 51 8.0 50 -15 10 35 TEMPERATURE (°C) 60 85 108 DVDD (µA) 57 8.6 MAX5732 toc09 8.9 MAX5732 toc08 60 MAX5732 toc07 9.0 -40 60 3.5 0.5 VSS = -0.5V 0 -40 4.0 1.0 1 0 85 4.5 FULL-SCALE ERROR (mV) 5 ZERO-SCALE ERROR (mV) 0.20 60 5.0 MAX5732 toc05 6 MAX5732 toc04 0.25 AVDD (mA) 1.5 1 -1 DNL (LSB) 2.5 0.2 DNL (LSB) INL (LSB) 3 WORST-CASE INL vs. TEMPERATURE 3.0 MAX5732 toc02 0.4 MAX5732 toc01 5 MAX5732 toc03 INTEGRAL NONLINEARITY vs. INPUT CODE 107 106 105 104 103 ALL DIGITAL INPUTS AT ZERO OR DVDD -40 -15 10 102 DVDD = +3V 101 35 TEMPERATURE (°C) 60 85 ALL DIGITAL INPUTS AT ZERO OR DVDD -40 -15 10 DVDD = +5V 35 60 85 TEMPERATURE (°C) ______________________________________________________________________________________ 11 MAX5732–MAX5735 Typical Operating Characteristics (AVCC = +10.5V ±5%, AVDD = +5V ±5%, DVDD = +5V, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.000V, RL = ∞, CL = 50pF referenced to ground, output gain = 2.5, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C). 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732–MAX5735 Typical Operating Characteristics (continued) (AVCC = +10.5V ±5%, AVDD = +5V ±5%, DVDD = +5V, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.000V, RL = ∞, CL = 50pF referenced to ground, output gain = 2.5, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C). LARGE-SIGNAL STEP RESPONSE (LOW TO HIGH) DIGITAL FEEDTHROUGH LARGE-SIGNAL STEP RESPONSE (HIGH TO LOW) MAX5732 toc11 MAX5732 toc10 MAX5732 toc12 CS 5V/div CS 5V/div OUT_ 5V/div OUT_ 5V/div SCLK 5V/div OUT_ 10mV/div 2µs/div 2µs/div NOISE VOLTAGE DENSITY MAJOR CARRY TRANSITION (7FFFhex TO 8000hex) MAJOR CARRY TRANSITION (8000hex TO 7FFFhex) MAX5732 toc13 1000 NOISE (nV/√Hz) 400ns/div MAX5732 toc15 MAX5732 toc14 CS 5V/div CS 5V/div 100 10 OUT_ 20mV/div OUT_ 20mV/div 1 0 12 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) 1µs/div 1µs/div ______________________________________________________________________________________ 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface PIN NAME 1, 42, 48 AVCC Output-Amplifier Positive Supply Input. Bypass to VSS with a 0.1µF capacitor. FUNCTION 2 OUT9 DAC9 Buffered Analog Output Voltage 3 OUT8 DAC8 Buffered Analog Output Voltage 4 OUT7 DAC7 Buffered Analog Output Voltage 5 N.C. 6 OUT6 No Connection. Internally connected. Do not make any connections to N.C. DAC6 Buffered Analog Output Voltage 7 OUT5 DAC5 Buffered Analog Output Voltage DAC4 Buffered Analog Output Voltage 8 OUT4 9, 38 AGND Analog Ground 10 OUT3 DAC3 Buffered Analog Output Voltage 11, 28, 39 VSS Output-Amplifier Negative Supply Input 12 OUT2 DAC2 Buffered Analog Output Voltage 13 OUT1 DAC1 Buffered Analog Output Voltage 14 OUT0 15 DSP 16 CS 17 DOUT Digital Serial-Data Output. Use DOUT to daisy chain and read the contents of the DAC registers. 18 SCLK Digital Serial-Clock Input 19 DIN Digital Serial-Data Input DAC0 Buffered Analog Output Voltage Digital Serial-Interface-Select Input. Drive low for DSP-interface mode. Drive high for SPI-interface mode. Active-Low Digital Chip-Select Input 20 DVDD Digital Power-Supply Input. Bypass to DGND with a 0.1µF capacitor. 21 DGND Digital Ground 22 LDAC Active-Low Digital Load DAC Input. Drive this asynchronous input low to transfer the contents of the input register to their respective DAC registers and set all DAC outputs accordingly. 23 CLR Active-Low Digital Clear Input. Drive this asynchronous input low to clear the contents of the input and DAC registers and set all the DAC outputs to zero. 24 GS Ground-Sense Analog Input. Offsets the DAC amplifier outputs by ±0.5V to compensate for a remote system ground potential difference. 25, 49 REFGND 26 REF 27, 50 AVDD 29 OUT31 DAC31 Buffered Analog Output Voltage 30 OUT30 DAC30 Buffered Analog Output Voltage 31 OUT29 DAC29 Buffered Analog Output Voltage 32 OUT28 DAC28 Buffered Analog Output Voltage 33 OUT27 DAC27 Buffered Analog Output Voltage 34 OUT26 DAC26 Buffered Analog Output Voltage 35 OUT25 DAC25 Buffered Analog Output Voltage 36 OUT24 DAC24 Buffered Analog Output Voltage 37 OUT23 DAC23 Buffered Analog Output Voltage Reference Ground Analog Reference Voltage Input Analog Power-Supply Input. Bypass to AGND with a 0.1µF capacitor. ______________________________________________________________________________________ 13 MAX5732–MAX5735 Pin Description 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732–MAX5735 Pin Description (continued) PIN NAME 40 OUT22 DAC22 Buffered Analog Output Voltage 41 OUT21 DAC21 Buffered Analog Output Voltage 43 OUT20 DAC20 Buffered Analog Output Voltage 44 OUT19 DAC19 Buffered Analog Output Voltage 45 OUT18 DAC18 Buffered Analog Output Voltage 46 OUT17 DAC17 Buffered Analog Output Voltage 47 OUT16 DAC16 Buffered Analog Output Voltage 51 OUT15 DAC15 Buffered Analog Output Voltage 52 OUT14 DAC14 Buffered Analog Output Voltage 53 OUT13 DAC13 Buffered Analog Output Voltage 54 OUT12 DAC12 Buffered Analog Output Voltage 55 OUT11 DAC11 Buffered Analog Output Voltage 56 OUT10 — 14 EP FUNCTION DAC10 Buffered Analog Output Voltage Exposed Paddle. Internally connected to VSS. Connect externally to a metal pad for improved thermal dissipation. ______________________________________________________________________________________ 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732–MAX5735 AVCC INPUT REGISTER DAC0 REGISTER DAC0 OUT0 VSS AVCC INPUT REGISTER DAC1 REGISTER DAC1 OUT1 VSS AVCC INPUT REGISTER DAC_ REGISTER DAC_ OUT_ VSS AVCC INPUT REGISTER DAC30 REGISTER DAC30 OUT30 VSS AVCC INPUT REGISTER DAC31 REGISTER DAC31 OUT31 VSS AVCC OFFSET DAC REGISTER INPUT REGISTER OFFSET DAC VSS AGND POWER MANAGEMENT AVDD DVDD GS REF DOUT CLR LDAC DSP DIN SCLK CS DIGITAL CONTROL LOGIC MAX5732 MAX5733 MAX5734 MAX5735 DGND REFGND Figure 1. Functional Diagram ______________________________________________________________________________________ 15 MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface Detailed Description range; the MAX5734 has a -2.5V to +7.5V output range; and the MAX5735 has a -5V to +5V output range. The MAX5732–MAX5735 are 32-channel, 16-bit, voltage-output DACs (Figure 1). The devices accept a 3V external reference input at REF. An internal offset DAC allows all outputs to be offset (see Table 1). The devices provide a ground-sensing function that allows the output voltages to be referenced to a remote ground. A 33MHz SPI-/QSPI/-MICROWIRE- and DSP-compatible serial interface controls the MAX5732–MAX5735 (Figure 2). Each DAC includes a double-buffered input structure to minimize the digital noise feedthrough from the digital inputs to the outputs, and allows for synchronous or asynchronous updating of the outputs. The two buffers are organized as an input register followed by a DAC register that stores the contents of the output. Input registers update the DAC registers independently or simultaneously with a single software or hardware command. The MAX5732–MAX5735 also have a DOUT that allows for read-back or daisy chaining multiple devices. The MAX5732–MAX5735 are available in a 56-pin 8mm x 8mm thin QFN package and are specified over the extended -40°C to +85°C temperature range. External Reference Input (REF) The REF voltage sets the full-scale output voltage for all 32 DACs. REF accepts a +3V ±3% input. Reference voltages outside these limits can result in a degradation of device performance. REF is a buffered input. The typical input impedance is 10MΩ, and it does not vary with code. Use a highaccuracy, low-noise voltage reference such as the MAX6126AASA30 (3ppm/°C temp drift and 0.02% initial accuracy) to improve static accuracy. REF does not accept AC signals. Ground Sense (GS) The MAX5732–MAX5735 include a GS that allows the output voltages to be referenced to a remote ground. The GS input voltage range (VGS) is -0.5V to +0.5V. VGS is added to the output voltage with unity gain. The resulting output voltage must be within the valid outputvoltage range set by the power supplies. See the Output Amplifiers (OUT0–OUT31) section for the effect of the GS inputs on the DAC outputs. The MAX5732–MAX5735 analog and digital sections have separate power inputs. Separate power inputs are also provided for the output buffer amplifiers. Proprietary deglitch circuits prevent output glitches at power-up and eliminate the need for power sequencing. A software-shutdown mode allows efficient power management. The MAX5732–MAX5735 consume 50µA of supply current in shutdown. All DACs provide buffered outputs that can drive 10kΩ in parallel with 100pF. The MAX5732 has a 0 to +5V output range; the MAX5733 has a 0 to +10V output Offset DAC The MAX5732–MAX5735 feature an offset DAC that determines the output voltage range. While each part number has an output voltage range associated with it, tCL SCLK X X 1 2 tCH 3 32 X tDH DIN C2 tSCS C1 C0 D0 tCS1 tDS tCS2 tCSS CS (µC MODE) tCSPWH tCSPWL CS (DSP MODE) Figure 2. Serial-interface Timing 16 ______________________________________________________________________________________ 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface PART NUMBER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MAX5732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAX5733 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAX5734 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAX5735 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: For the MAX5732, the maximum code for the offset DAC is 16384. For the MAX5733/MAX5734/MAX5735, the maximum code for the offset DAC is 40000. it is the offset DAC that determines the end-point voltages of the range. Table 1 shows the offset DAC code required during power-up. Note: The offset DAC of every device can be programmed with any of the four output voltage ranges. However, the specifications in the Electrical Characteristics table are only guaranteed (production tested) for the offset code associated with each particular part number. For example, the MAX5734 specifications are only valid with the MAX5734 offset- DAC code shown in Table 1. The offset DAC is summed with GS (Figure 1). The offset DAC can also cancel the offset of the output buffers. Any change in the offset DAC affects all 32 DACs. The offset DAC is also configured identically to the other 32 DACs with an input and DAC register. Write to the offset DAC through the serial interface by using control bits C2, C1, and C0 = 001 followed by the data bits D15–D0. The CLR command affects the offset DAC as well as the other DACs. The data format for the offset DAC codes are: control bits C2, C1, and C0 = 011, address bits A5–A0 = 100000, 7 don’t-care bits, and 16 data bits as shown in Table 2. Output Amplifiers (OUT0–OUT31) All DAC outputs are internally buffered. The internal buffers provide gain, improved load regulation, and transition glitch suppression for the DAC outputs. The output buffers slew at 1V/µs and can drive 10kΩ in parallel with 100pF. The output buffers are powered by AVCC and Table 2. Serial Data Format CONTROL BITS ADDRESS BITS DON’TCARE BITS DATA BITS C2, C1, AND C0 A5–A0 — D15–D0 011 100000 XXXXXXX See table 1 VSS. AVCC and VSS determine the maximum output voltage range of the device. The input code, the voltage reference, the offset DAC output, the voltage on GS, and the gain of the output amplifier determine the output voltage. Calculate VOUT as follows: VOUT = GAIN × VREF × (DAC code − offset DAC code) 216 + VGS where GAIN = 5/3 for the MAX5732, or GAIN = 10/3 for the MAX5733/MAX5734/MAX5735. Load-DAC (LDAC) Input The MAX5732–MAX5735 feature an active-low LDAC logic input that allows the outputs OUT_ to update asynchronously. Keep LDAC high during normal operation (when the device is controlled only through the serial interface). Drive LDAC low to simultaneously update all DAC outputs with data from their respective input registers. Figure 3 shows the LDAC timing with respect to OUT_. tLDAC LDAC ±0.5 LSB tS OUT_ Figure 3. LDAC Timing ______________________________________________________________________________________ 17 MAX5732–MAX5735 Table 1. Offset DAC Codes MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface A software command can also activate the LDAC operation. To activate LDAC by software, set control bits C2, C1, and C0 = 010, address bits A5–A0 = 111111, and all data bits to don’t care. See Table 3 for the data format. This operation updates all DAC outputs. Note: The software load DAC does not affect the offset DAC. Clear (CLR) The MAX5732–MAX5735 feature an active-low CLR logic input that sets all channels including the offset DAC to 0V (code 0000hex). The offset DAC needs to be reprogrammed after CLR is asserted. Driving CLR low clears the contents of both the input and DAC registers. The serial interface can also issue a software clear command. Setting the control bits C2, C1, and C0 = 111 (Table 4) performs the same function as driving logicinput CLR low. Table 4 shows the clear-data format for the software-controlled clear command. This registerreset process cannot be interrupted. All serial input data is ignored until the entire reset process is complete. Serial Interface A 3-wire SPI-/QSPI-/MICROWIRE- and DSP-compatible serial interface controls the MAX5732–MAX5735. The interface requires a 32-bit command word to control the device. The command word consists of 3 control bits, 6 address bits, 7 don’t-care bits, and 16 data bits. Table 5 shows the general serial-data format. The control bits control various write and read commands as well as the load DAC and clear commands. Table 6 shows the control-bit functions. The address bits select the register(s) to be written. Table 7 shows the address functions. The data bits control the value of the DAC outputs. Table 6. Control-Bit Functions CONTROL BITS CONTROL-BIT DESCRIPTION C2 C1 C0 0 No operation (NOP); no internal registers change state. The NOP command can be passed to DOUT depending on the state of the configuration register. Address bits A5–A0 and data bits D15–D0 are ignored. 1 Loads D15–D0 into the input register(s) for the selected address. Depending on the address bits, this command could write to: The configuration register (A[5:0] = 100001) One of the input registers of the 32 DAC channels All 32 DAC input registers (A[5:0] = 111111) The offset DAC input register (A[5:0] = 100000) Table 3. Load-DAC Data Format 0 CONTROL BITS ADDRESS BITS DON’TCARE BITS DATA BITS C2, C1, AND C0 A5–A0 — D15–D0 010 111111 XXXXXXX XXXXXXXXXXXXXXXX 0 0 0 Table 4. Clear-Data Format CONTROL BITS ADDRESS BITS DON’TCARE BITS DATA BITS C2, C1, AND C0 A5–A0 — D15–D0 111 See table 7 XXXXXXX XXXXXXXXXXXXXXXX Table 5. Serial-Data Format CONTROL BITS ADDRESS BITS DON’TCARE BITS DATA BITS MSB C2, C1, and C0 18 0 1 0 Loads DAC register(s) from the input register(s). Depending on the address bits, this command can update one or all of the DAC registers from the stored input register value(s). Data bits D15–D0 are ignored. 0 1 1 Write-through; loads D15–D0 into the input and DAC registers, depending on the address bits. 1 0 0 Read command; depending on the address bits, one of the DAC-register values or the configuration-register value may be read back through DOUT. Data bits D15–D0 are ignored. 1 0 1 Reserved for internal testing; do not use. 1 1 0 Reserved for internal testing; do not use. 1 1 1 Clear register(s); depending on the address bits, one or all registers (except the offset-DAC registers) are cleared to zero. Data bits D15–D0 are ignored. LSB A5–A0 XXXXXXX D15–D0 ______________________________________________________________________________________ 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface ADDRESS BITS A5 A4 A3 A2 A1 A0 CONTROL FUNCTION ADDRESS BITS A5 A4 A3 A2 A1 A0 CONTROL FUNCTION 0 0 0 0 0 0 DAC0 1 0 0 0 1 0 Command reserved; do not use. 0 0 0 0 0 1 DAC1 1 0 0 0 1 1 Command reserved; do not use. 0 0 0 0 1 0 DAC2 1 0 0 1 0 0 Command reserved; do not use. 0 0 0 0 1 1 DAC3 1 0 0 1 0 1 Command reserved; do not use. 0 0 1 1 0 Command reserved; do not use. 0 0 0 1 0 0 DAC4 1 0 0 0 1 0 1 DAC5 1 0 0 1 1 1 Command reserved; do not use. 0 0 0 1 1 0 DAC6 1 0 1 0 0 0 Command reserved; do not use. 0 1 0 0 1 Command reserved; do not use. 0 0 0 1 1 1 DAC7 1 0 0 1 0 0 0 DAC8 1 0 1 0 1 0 Command reserved; do not use. 0 0 1 0 0 1 DAC9 1 0 1 0 1 1 Command reserved; do not use. 0 1 1 0 0 Command reserved; do not use. 0 0 1 0 1 0 DAC10 1 0 0 1 0 1 1 DAC11 1 0 1 1 0 1 Command reserved; do not use. 0 0 1 1 0 0 DAC12 1 0 1 1 1 0 Command reserved; do not use. 0 1 1 1 1 Command reserved; do not use. 0 0 1 1 0 1 DAC13 1 0 0 1 1 1 0 DAC14 1 1 0 0 0 0 Command reserved; do not use. 0 0 1 1 1 1 DAC15 1 1 0 0 0 1 Command reserved; do not use. 1 0 0 1 0 Command reserved; do not use. 0 1 0 0 0 0 DAC16 1 0 1 0 0 0 1 DAC17 1 1 0 0 1 1 Command reserved; do not use. 0 1 0 0 1 0 DAC18 1 1 0 1 0 0 Command reserved; do not use. 0 1 0 0 1 1 DAC19 1 1 0 1 0 1 Command reserved; do not use. 0 1 0 1 0 0 DAC20 1 1 0 1 1 0 Command reserved; do not use. 0 1 0 1 0 1 DAC21 1 1 0 1 1 1 Command reserved; do not use. 0 1 0 1 1 0 DAC22 1 1 1 0 0 0 Command reserved; do not use. 0 1 0 1 1 1 DAC23 1 1 1 0 0 1 Command reserved; do not use. 0 1 1 0 0 0 DAC24 1 1 1 0 1 0 Command reserved; do not use. 0 1 1 0 0 1 DAC25 1 1 1 0 1 1 Command reserved; do not use. 0 1 1 0 1 0 DAC26 1 1 1 1 0 0 Command reserved; do not use. 0 1 1 0 1 1 DAC27 1 1 1 1 0 1 Command reserved; do not use. 0 1 1 1 0 0 DAC28 1 1 1 1 1 0 Command reserved; do not use. 0 1 1 1 0 1 DAC29 0 1 1 1 1 0 DAC30 1 0 1 1 1 1 1 DAC31 1 0 0 0 0 0 Offset DAC All channels (DAC31–DAC0); used for write commands only. Read commands cannot be used with these address bits. 1 Configuration register; control bits C2, C1, and C0 = 010 and C2, C1, and C0 = 011 set the error flag in the configuration register. Do not use these control bits with these address bits. 1 0 0 0 0 1 1 1 1 1 ______________________________________________________________________________________ 19 MAX5732–MAX5735 Table 7. Address-Bit Functions MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface Table 8. Configuration-Register Data Format 16 DATA BITS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ERRF SING GLT DT SHDN X X X X X X X X X X X X = Don’t care. Table 9. Configuration-Register Commands DATA BIT D15 D14 D13 D12 NAME DESCRIPTION ERRF Error flag; ERRF goes logic-high when an invalid command is attempted. ERRF is cleared each time the configuration register is read back to DOUT. Clear-register commands C2, C1, and C0 = 111 resets ERRF. Conditions that trigger ERRF include: Attempted read of address bits A5–A0 = 111111 (all 32 DACs) Access to reserved addresses Access to the configuration register (address bits A5–A0 = 100001 when used with control bits C2, C1, and C0 = 010 and 011) Default is logic-low (no error flags); ERRF is read only. SING Single device; SING determines the manner in which data is output to DOUT. A logic-high sets the device to operate in stand-alone mode or in parallel; only the 16 data bits are output to DOUT. A logic-low sets the device to operate in a daisy chain of devices. In this case, the entire 32-bit command word is output to DOUT. Default is logic-low (daisy-chain mode); SING is read/write. GLT Glitch-suppression enable; the MAX5732–MAX5735 feature glitch-suppression circuitry on the analog outputs that minimizes the output glitch during a major carry transition. A logic-low disables the internal glitch-suppression circuitry, which improves settling time. A logic-high enables glitchsuppression, suppressing up to 120nV-s glitch impulse on the DAC outputs. Default is logic-low (glitch suppression disabled); GLT is read/write. DT D11 SHDN D10–D0 X Digital output enable; a logic-low enables DOUT. A logic-high disables DOUT. Disabling DOUT reduces power consumption and digital noise feedthrough to the DAC outputs from the DOUT output buffer. Default is logic-low (DOUT enabled); DT is read/write. Shutdown; a logic-high shuts down all 32 DACs. The logic interface remains active, and the data is retained in the input and DAC registers. Read/write operations can be performed while the device is disabled; however, no changes can occur at the device outputs. A logic-low powers up all 32 DACs if the device was previously in shutdown. Upon waking up, the DAC outputs return to the last stored value in the DAC registers. Default is logic-low (normal operation); SHDN is read/write. Don’t care. DSP Mode (DSP) The MAX5732–MAX5735 provide a hardware-selectable DSP-interface mode. DSP mode, when active, allows chip select (CS) to go high before the entire 32-bit command word is clocked in. The active-low DSP logic input selects microcontroller (µC)- or DSP-interface mode. Drive DSP low for DSP-interface mode. Drive DSP high for µC-interface mode. Figure 2 illustrates serial timing for both µC- and DSP-interface modes. 20 Configuration Register The configuration register controls the advanced features of the MAX5732–MAX5735. Write to the configuration register by setting the control bits C2, C1, and C0 = 001 and address bits A5–A0 = 100001. Table 8 shows the configuration-register data format for the D15–D0 data bits. Table 9 shows the commands controlled by the configuration register. ______________________________________________________________________________________ 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX573_ DIN(0) SCLK DOUT(0) CS CONTROLLER DEVICE 1 DSP MAX573_ DIN(1) SCLK DOUT(1) CS Daisy Chain Operation DSP Any number of the MAX5732–MAX5735 devices can be daisy chained by connecting the DOUT of one device to the DIN of another device in a chain. All devices must be in SING = 0 mode. Connecting the CS inputs of all devices together eliminates the need to issue NOP commands to devices early in the chain (see Figure 4). Data Readback The contents of the MAX5732–MAX5735 DAC and configuration registers can be read on DOUT by issuing a read-data command. Setting control bits C2, C1, and C0 = 100, puts the device in read-data mode. The address bits select the register to be read. The contents of the register (16 data bits) are clocked out at DOUT. The output-data format depends on the status of DSP and SING. Table 10 shows the manner in which MAX5732–MAX5735 SING When SING = 0 (default power-up mode), the device is in daisy-chain mode. DOUT follows DIN after 32 clock cycles. For the read command, DOUT provides the read data in the next cycle following CS rising edge. The 16 data bits of the previous command word are clocked out on the last 16 clock cycles of the current command word. When SING = 1, the device is in stand-alone mode. To reduce the time it takes to read data out, the read data is provided at DOUT as the 16 data bits of the current command are clocked in. The device acts on an incoming command word independent of the rising edge of CS. MAX573_ DIN(2) SCLK DOUT(2) CS DSP Figure 4. Daisy-Chain Configuration data is written to DOUT. Note that when the device is in DSP mode (DSP = 0), only the 16-bit data of the selected register is written to DOUT. Table 10. Read-Data Modes with SING and DSP Controls DSP SING CONFIGURATION DESCRIPTION 0 0 Stand alone DOUT provides the 16 data bits from the previous command word. Data appears at DOUT on the last 16 clock edges of the current command word. See Figure 7. 0 1 Stand alone DOUT provides the 16 data bits from the current command word. Data appears at DOUT on the last 16 clock edges of the current command word. See Figure 7. 1 0 Daisy chain Data on DOUT follows the current command word after 32 clock cycles. For read commands, the read data from the previous command word appears at DOUT on the last 16 clock edges of the current command word. See Figure 4. 1 1 READ DATA AT DOUT DOUT provides the 16 data bits from the current command word. Data appears Multiple DOUTs connected at DOUT on the last 16 clock edges of the current command word. For read in parallel (not daisy commands, the read data from the current command word appears at DOUT chained) on the last 16 clock edges of the current command word. See Figures 8 and 9. ______________________________________________________________________________________ 21 MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface DIN(0) W WD2 W WD1 W WD0 R XX R XX R XX X XX X XX X XX W WD2 W WD1 W WD0 R XX R XX R RD0 X XX X XX W WD2 W WD1 W WD0 R XX R RD1 R RD0 X XX R RD2 R RD1 R RD0 CS DOUT(0) DOUT(1) W WD2 DOUT(2) W WD1 W WD0 Figure 5. Example 1 of a Daisy-Chain Data Sequence W/WD0 = 32-bit word with a write command; WD0 writes data for device 0. The 0 refers to the position in the daisy chain (0 is closest to the bus master). Devices 1 and 2 are devices further down the chain. R/RD2 = 32-bit word with a read command; RD2 reads data from device 2. X = Don’t care (for X in the data or command position). DIN(0) W WD2 R XX W WD0 R XX W WD1 R XX X XX X XX X XX R XX W WD0 R XX W WD1 R RD0 X XX X XX W WD2 R RD1 W WD0 R XX W WD1 R RD0 X XX W WD2 R RD1 W WD0 R RD2 W WD1 R RD0 CS DOUT(0) DOUT(1) W WD2 DOUT(2) Figure 6. Example 2 of a Daisy-Chain Data Sequence W/WD0 = 32-bit word with a write command; WD0 writes data for device 0. The 0 refers to the position in the daisy chain (0 is closest to the bus master). Devices 1 and 2 are devices further down the chain. R/RD2 = 32-bit word with a read command; RD2 reads data from device 2. X = Don’t care (for X in the data or command position). 22 ______________________________________________________________________________________ 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface CONTROLLER DEVICE 1 OR 0 DSP Figure 7. Stand-Alone Configuration Shutdown Mode MAX573_ DIN SCLK DOUT CS CONTROLLER DEVICE 1 OR 0 DSP MAX573_ DIN SCLK DOUT CS 1 OR 0 DSP MAX573_ DIN SCLK DOUT CS 1 OR 0 The MAX5732–MAX5735 feature a software-controlled low-power shutdown mode. When bit 11 of the configuration register is a logic high, the analog section of the device is disabled, and the outputs go high impedance. In shutdown, supply current is reduced to 50µA. Data stored in the DAC and input registers is retained, and the device outputs return to their previous values when the device is brought out of shutdown. The serial interface remains active while the device is in shutdown. Power-Up State The MAX5732–MAX5735 monitor the four power supplies and maintain the output buffers in a known state until sufficient voltage is available to ensure that no output glitches occur. Once the minimum voltage threshold has been passed, the device outputs come up in the clear state (all outputs = 0). For proper power sequencing, VSS must be applied first. Power sequencing is not necessary if VSS is connected to AGND. DSP Figure 8. Example of a Parallel Configuration with Read-Back DIN(0) C2 C1 C0 A5 A4 A3 A2 A1 A0 Sp Sp Sp Sp Sp Sp Sp D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SCLK CS (µC) OR CS (DSP) DOUT(0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 9. Read Data Timing When Not Daisy Chained ______________________________________________________________________________________ 23 MAX5732–MAX5735 MAX573_ DIN SCLK DOUT CS Read-Data Format The MAX5732–MAX5735 support daisy-chain connections of multiple devices. The default (power-up) configuration for the MAX5732–MAX5735 assumes that the device may be part of a daisy chain of devices. DOUT follows DIN after 32 clock cycles. For a read command, DOUT provides read data (instead of the data value shifted in) in the next cycle following a CS rising edge. Figures 5 and 6 show examples of daisy-chain data sequences. MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface HVDRV0 DAC0 MAX5732 MAX5733 VOLTAGE REFERENCE DAC31 HVDRV31 14 TO 16 BITS CONTROL ALGORITHM DWDM PIPE DSP 14 TO 16 BITS ADC POSITION OR OPTICAL FEEDBACK VOLTAGE REFERENCE PGA OR FIXED GAIN AMPS MEMS MIRRORS WITH X AND Y CONTROL THIN-FILM FILTER OR PLANAR LIGHT WAVE SEPARATORS WITH OPTICAL LENSES MEMS MIRRORS WITH X AND Y CONTROL DWDM PIPE OPTICAL LENSES AND COLLIMATORS Figure 10. MEMS Mirror Control Applications Information MEMS Micromirror Control The MAX5732/MAX5733 are the highest resolution 32channel DACs available in the smallest footprint, making the devices ideal for optical MEMS mirror control (Figure 10). A high-resolution DAC forms the core analog block for controlling the X and Y position of the mirror. As the density of the optical cross-connects increases, the number of DAC channels also increases. By offering the highest resolution and the greatest density, the MAX5732/MAX5733 improve performance and reduce the board footprint. Automatic Test Equipment (ATE) Applications The MAX5734 includes many features suited for ATE applications. The device is the most compact level-setting solution available for high-density pin electronics boards. The MAX5734 provides a -2.5V to +7.5V output voltage range (required by most ATE applications). 24 The offset DAC simultaneously adjusts the voltage range of all 32 DACs, allowing optimization to the application. The remote-sense feature allows the pin electronic voltages to be referenced to the ground potential at the DUT site. The B grade linearity error of ±2.44mV (max) is more than sufficient for most ATE applications. The A grade device cuts this error to ±1.22mV (max) for higher accuracy. The pipelined register architecture allows all 32 DACs to be updated simultaneously. This is valuable during test setups, as all values in the tester can be set and then updated in unison with a single command. This feature can be accessed through the serial port or the LDAC input. The low output noise of the MAX5734 allows direct connection to the pin electronics, eliminating the cost and PC board area of external filtering. Modern pin electronics integrated circuits (PEICs) are typically fabricated on high-speed processes with low ______________________________________________________________________________________ 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface Additional protection is provided by the MAX5734 glitch-free power-up into the clear state with all DAC outputs set to approximately 0V. Either the serial port or the CLR input can assert the clear function. Power Supplies, Bypassing, Decoupling, and Layout Grounding and power-supply decoupling strongly influence device performance. Digital signals can couple through the reference input, power supplies, and ground connection. Proper grounding and layout can reduce digital feedthrough and crosstalk. Bypass all power supplies with an additional 0.1µF and 1µF on each pin, as close to the device as possible. Refer to the MAX5732– MAX5735 evaluation kit for a suggested layout. The MAX5732–MAX5735 have four separate power supplies. AV DD powers the internal analog circuitry (except for the output buffers) and DVDD powers the digital section of the device. AVCC and VSS power the output buffers. The MAX5732–MAX5735 feature an exposed paddle on the backside of the package for improved power dissipation. The exposed paddle is electrically connected to VSS, and should be soldered to a large copper plane that shares the same potential. For more information on the exposed paddle QFN package, refer to the following website: http://pdfserv.maxim-ic.com/arpdf/AppNotes/ 4hfan081.pdf Selector Guide INL (MAX LSB) OUTPUT VOLTAGE RANGE (V) MAX5732ACTN ±8 0 to +5 MAX5732BCTN ±16 0 to +5 MAX5732CCTN ±64 0 to +5 MAX5732AETN ±8 0 to +5 OUT20 OUT19 OUT18 OUT17 OUT16 PART AVCC REFGND 55 54 53 52 AVDD 56 OUT15 OUT14 OUT13 OUT12 OUT11 TOP VIEW OUT10 Pin Configuration 51 50 49 48 47 46 45 44 43 AVCC 1 42 AVCC OUT9 2 41 OUT21 OUT8 3 40 OUT22 OUT7 4 39 VSS MAX5732BETN ±16 0 to +5 N.C. 5 38 AGND MAX5732CETN ±64 0 to +5 OUT6 6 37 OUT23 MAX5733ACTN ±8 0 to +10 OUT5 7 36 OUT24 OUT4 8 MAX5733BCTN ±16 0 to +10 AGND 9 34 OUT26 MAX5733CCTN ±64 0 to +10 33 OUT27 MAX5733AETN ±8 0 to +10 VSS 11 32 OUT28 MAX5733BETN ±16 0 to +10 OUT2 12 31 OUT29 MAX5733CETN ±64 MAX5734ACTN ±8 -2.5 to +7.5 MAX5734BCTN ±16 -2.5 to +7.5 MAX5734CCTN ±64 -2.5 to +7.5 MAX5734AETN ±8 -2.5 to +7.5 MAX5734BETN ±16 -2.5 to +7.5 MAX5734CETN ±64 -2.5 to +7.5 MAX5735ACTN ±8 -5 to +5 MAX5735BCTN ±16 -5 to +5 TRANSISTOR COUNT: 152,000 MAX5735CCTN ±64 -5 to +5 PROCESS: BiCMOS MAX5735AETN ±8 -5 to +5 MAX5735BETN ±16 -5 to +5 MAX5735CETN ±64 -5 to +5 MAX5732 MAX5733 MAX5734 MAX5735 OUT3 10 OUT1 13 35 OUT25 30 OUT30 EXPOSED PADDLE OUT0 14 29 OUT31 VSS AVDD REF REFGND GS CLR LDAC DGND DVDD DIN SCLK DOUT CS DSP 15 16 17 18 19 20 21 22 23 24 25 26 27 28 8mm x 8mm THIN QFN-EP Chip Information 0 to +10 ______________________________________________________________________________________ 25 MAX5732–MAX5735 breakdown voltages. Some devices require external protection on their reference inputs to satisfy absolute maximum ratings. The MAX5734 features outputs that are almost rail-to-rail. This allows the AVCC and VSS supplies to be set to voltages within the absolute maximum ratings of the PEIC. This guarantees that the PEIC is protected in all situations. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 56L THIN QFN.EPS MAX5732–MAX5735 32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.